Powering an I.MX 6SX-Based System Using the PF3000 PMIC

NXP Semiconductors Document Number: AN5161 Application Note Rev. 1.0, 7/2016 Powering an i.MX 6SX-based system using the PF3000 PMIC

1 Introduction Contents 1 Introduction...... 1 The PF3000 is a highly integrated Power Management IC ideally suited to power NXP's i.MX 6SX, i.MX 6SL, i.MX 6S, i.MX 6DL, 2 PF3000 voltage regulators ...... 2 i.MX 6UL and the i.MX 7 series of applications processors. This 3 i.MX 6SX power management using the PF3000 ...... 3 Application Note discusses the power tree configuration for 4 PF3000 power input ...... 4 powering an i.MX 6SX based system using the PF3000. NXP analog ICs are manufactured using the SMARTMOS 5 PF3000 layout guidelines ...... 5 process, a combinational BiCMOS manufacturing flow that 6 PF3000 software support ...... 5 integrates precision analog, power functions and dense CMOS 7 Schematics...... 6 logic together on a single cost-effective die. 8 References ...... 27 9 Revision history ...... 28

2 PF3000 voltage regulators Table 1 shows a summary of the voltage regulators in the PF3000. Output voltage and startup sequence of the regulators is programmed into the PMIC through One Time Programmable (OTP) memory. For more details, refer to the product datasheet. Table 1. PF3000 voltage regulators Regulator Output voltage range Load current rating 0.7 V to 1.425 V SW1A 1.8 V 1000 mA 3.3 V SW1B 0.7 V to 1.475 V 1750 mA 1.5 V to 1.85 V SW2 1250 mA 2.5 V to 3.3 V SW3 0.9 V to 1.65 V 1500 mA SWBST 5.0 V to 5.15 V 600 mA VSNVS 3.0 V 1.0 mA VLDO1 1.8 V to 3.3 V 100 mA VLDO2 0.8 V to 1.55 V 250 mA VLDO3 1.8 V to 3.3 V 100 mA VLDO4 1.8 V to 3.3 V 350 mA 1.8 V to 1.85 V VCC_SD 100 mA 2.85 V to 3.3 V V33 2.85 V to 3.3 V 350 mA VREFDDR VINREFDDR/2 10 mA

Powering an i.MX 6SX-based system using the PF3000 PMIC, Rev. 1.0 NXP Semiconductors 2 i.MX 6SX power management using the PF3000

3 i.MX 6SX power management using the PF3000

The i.MX 6SX processor features NXP's advanced implementation of the a single ARM® Cortex®-A9 MPCore™ multicore processor, which operates at speeds up to 1 GHz. Table 2 shows how PF3000 can be used to power an i.MX 6SX based system. This include the voltage rails required by the processor as well as memory and common peripherals. As a programming PMIC, the PF3000 can be used in a number of ways to power the i.MX 6SX. Table 2 lists one of the many possibilities. The power tree can be optimized based on specific application requirements.

Table 2. PF3000 + i.MX 6SX power tree Regulator Voltage Sequence Load domain SW1A 1.375 V 2 VDDCORE SW1B 1.375 V 2 VDDSOC SW2 3.3 V 4 NVCC_SD4, NVCC_NAND, NVCC_GPIO, NVCC_KEY, NVCC_QSPI, NVCC_LCD1, NVCC_HIGH (SD3), LCD Connector, CAN, Sensors, SD3 (SD3.0 Card), SD4 (SD Card-boot), QSPI Flash SW3 1.35 V 3 DDR3L SWBST 5.0 V Off N/A VSNVS 3.0 V 0 VDD_SNVS_IN VLDO1 3.3 V Off N/A VLDO2 1.5 V Off Camera Connector, MPCIE VLDO3 2.5 V Off Camera Connector, Audio Codec VLDO4 1.8 V 4 NVCC_LOW(SD3), NVCC_CSI VCC_SD 3.3 V 5 VDD_AFE_3P3, VDDA_ADC_3P3 (12-bit ADC), ADC_VREFH (12-bit ADC) V33 3.0 V 1 VDD_HIGH_IN,VDD_HIGH_CAP VREFDDR 0.625 V 3 DRAM_VREF

Powering an i.MX 6SX-based system using the PF3000 PMIC, Rev. 1.0 NXP Semiconductors 3 PF3000 power input

4 PF3000 power input

PF3000 input voltage range is 2.8 V to 4.5 V or 3.7 V to 5.5 V. 2.8 V to 4.5 V when VIN is used at input. 3.7 V to 5.5 V when VPWR is used as input. For non-battery operated applications, when the input supply voltage exceeds 4.5 V, the front-end LDO can be activated by populating the external PMOS pass FET Q16 in Figure 1 and connecting the VPWR pin to the main supply. In this case, the LDO control block self-starts with a local bandgap reference.

R496 0

PSU_5V0 R497 0 R498 0 VPWR

R499 0 470PF C380 DNP DNP Q16 FDMA908PZ GND LDOG R500 GATE 3 4 SOURCE 0 8 C383 C384 2 5 0.1UF 4.7uF

1 6 GND GND C386 C387 SYS_3V8 47uF 47uF

DRAIN 7 GND GND

C392 C393 C394 47uF 47uF 47uF DNP

GND GND GND

Figure 1. PF3000 5.0 V input circuit

Powering an i.MX 6SX-based system using the PF3000 PMIC, Rev. 1.0 NXP Semiconductors 4 PF3000 layout guidelines

In a battery operated application, BC3770 input is connected directly to the adapter. BC3770 is a fully programmable switching charger with dual-path output. One output path connect to PF3000 VIN as the system power supply. The other output path is for single-cell Li-Ion and Li-Polymer battery. (See Figure 2.) In this case, the PMOS pass FET Q16 should not be populated and VPWR pin should be grounded externally.

WALL_5V_DC_JACK

U44 A1 B1 C447 A2 VBUS_A1 PMID C450 VBUS_A2 2.2UF 2.2UF E1 GND A3 PGND_E1 E2 VL PGND_E2 SW2_3V3 GND C444 B2 R793 0 DNP 1.0UF C3 BOOT C452 SYS_3V8 GND 0.1UF L49 VDDIO 0402_CC R794 0 DNP C1 16V 1 2 GND B4 LX_C1 D1 VIO LX_D1 R787 R788 R786 R789 1UH 1.5K 1.5K 10k 10k ind_vls252010 C449 C445 R792 D4 10UF 0.1UF VSYS_D4 2.2K E3 0402_CC B5 VSYS_E3 E4 INT VSYS_E4 GND GND R790 A5 C5 A 0 (6,11) PMIC_SDA SDA CHGOUT_C5 D5 CHG_OUT 0402_CC D33 R791 A4 CHGOUT_D5 E5 (6,11) PMIC_SCL 0 SCL CHGOUT_E5 LED Green 0402_CC C448 C446 D2 C4 4.7uF 0.1UF CHGEN BAT_REG DNP

D3 C2 VBAT C SHDN NOBAT B3 GND GND J140 BATSNSN GND BATREG 1 MC32BC3770CS BAT_SNS 2 GND NOBAT 3 Main PWR I2C ADDR: 0x92 1803439 C451 1.0UF J24 LED BATT 2 GND 1 Lithium single cell GND B2B-PH-K-S GND battery connectors

Figure 2. BC3770 lithium charger

5 PF3000 layout guidelines

The Application Note AN5094 provides best practices for the layout of the PF3000 device on printed circuit boards. To download AN5094, click on the following link: http://www.nxp.com/files/analog/doc/app_note/AN5094.pdf

6 PF3000 software support

NXP offers PF3000 code support for a custom i.MX 6 board at the NXP Community site https://community.nxp.com/docs/DOC-105064).

Powering an i.MX 6SX-based system using the PF3000 PMIC, Rev. 1.0 NXP Semiconductors 5 Schematics

7 Schematics Power Tree Diagram Note: (*1) - SW2 of PF3000 can be changed to 3.1V after boot-up (by SW) to lower power consumption (*2) - No SW1C and SW4 in PF3000. Legend: 0 - Always On 1 - First start-up supply rail

Figure 3. Schematic part 1

Powering an i.MX 6SX-based system using the PF3000 PMIC, Rev. 1.0 NXP Semiconductors 6 Schematics

2.2K R792 0402_CC D33 LED Green

A C GND Main PWR LED J24 B2B-PH-K-S 2 1 GND BATT J140 1803439 2 3 1 GND SYS_3V8 TP99 DNP DNP 0 C451 1.0UF R794 R793 0 GND C5 47uF 10V 0805_CC VBAT Note: If solder PF3000 5V input circuit in page4 for, then this part is no needed. GND PSU_5V0 1uF 16V C4 0402_cc BATREG BAT_SNS CHG_OUT NOBAT C445 0.1UF GND 0.1uF 25V 0402_CC C3 C449 10UF Note: Over-voltage protection is designed to protect up +20V. C446 0.1UF DNP GND GND

TVS3 ESD5B5.0ST1G

2 1 2 C448 4.7uF Main PWR Switch 1UH ind_vls252010 GND L49 7 GND 1

2 1 4 3 6

6 1

EG2209A

2.2UF C450 5 2 0402_CC DNP JP1 C452 0.1UF 16V

SW1

Lithium single cell battery connectors RC0603_OV R5 3.3K RC0603_OV R4 2.2K 8

GND 4 3 5 2 1 Q1 FDMA530PZ R2 100K C2 E1 E2 C5 D1 E3 E4 C1 B1 B3 C4 D4 D5 E5 B2 PMID Over Voltage Protection BOOT LX_C1 LX_D1 NOBAT 25V C2 0.01uF VSYS_E3 VSYS_E4 VSYS_D4 PGND_E1 PGND_E2 BAT_REG BATSNSN 0402_CC CHGOUT_E5 CHGOUT_C5 CHGOUT_D5 VBUS_A1 VL GND VIO SCL CHGEN SHDN INT VBUS_A2 SDA U44 MC32BC3770CS C A1 A3 B4 A4 B5 A2 A5 D2 D3 C3 Lithium Charger D3 RB521S30T1G A C447 2.2UF MMBT3906TT1G Q2

GND 2 3 C444 1.0UF GND WALL_5V_DC_JACK 1 GND WALL_OV_BASE R789 10k WALL_OVP_LED 10K WALL_5V_DC_JACK R786 10k R3 TP2 TP1 GND R788 1.5K R787 1.5K

D2 MM5Z5V1ST1G

WALL_OV_CTL R1 3.3K RC0603_OV

C A 0 GND 0 C1 0.1uF 0402_CC 25V VDDIO 0402_CC 0402_CC R791 R790 1 2 3 SW2_3V3 PMIC_SCL PMIC_SDA J1 CON_1_PWR (6,11) (6,11)

Figure 4. Schematic part 2

Powering an i.MX 6SX-based system using the PF3000 PMIC, Rev. 1.0 NXP Semiconductors 7 Schematics C401 NVCC_1V8 4.7uF 0 GND VGEN1_1V2 0 C387 47uF C400 0.1UF GND R513 SOURCE GND 4 C386 47uF R516 TPS76912 C423 4.7uF GND NC/FB GND 4 8 5 6 C384 4.7uF Q17 U42 GND EN IN OUT VGEN4_1V8 GND 1 5 3 2

TPS76912 1.2V/0.1A C383 FDMA908PZ 7 0.1UF SOURCE GND 4 8 5 6 3 2 1 GND 0 Q16 C DNP MEM_3V1 R498 R496 0 0 NVCC_3V1

C426 1.0UF 10V

C380 D31 B350A 7 PERI_3V3 FDMA908PZ A GND GATE DRAIN 470PF DNP R512 3 2 1 SH14 SH0805_40 GATE SOLDER SHORT SW Note: Default power-up voltage of SW2_3V3 is 3.3V. Need to change it 3.1V after boot-up to lower power consumption. SYS_3V8 VGEN2_1V5 25V C434 0.1uF CC0402_25 DRAIN LDO outputs 1.2V or adding a schottky diode in series on VGEN2_1V5 rail to generate 1.2V GND C394 47uF DNP 0 PSU_5V0 SW2_3V3 GND R500 47uF C393 10v C433 10uF 0603_CC DNP GND R497 0 R499 0 GND DDR_1V35 LDOG GND 47uF C392 5 4 SYS_3V8 VPWR GND PF3000 5V input circuit SNS

OUT

NCP692MN33T2G

EPAD

SH11 SH0805_40 7

C407 4.7uF SOLDER SHORT

GND 2 GND V33 SWBST_5V C405 47uF EN U43 IN1 IN2 C413 22UF 0603_CC 6.3V 1 6 3 GND BT1 + 2994TR C425 4.7uF

- C417 1.0UF 10V R504 1K 1 GND

2 3 0603_CC 6.3V GND C412 22UF GND R524 10K C GND DRAM_VREF Max output current from NCP692 is 1A P3V15_LICELL GND MBR140SFT VGEN4_1V8 GND VGEN6_3V0 SW3_OUT 0.22uF D30 GND 10v C432 10uF 0603_CC A L44

C441

C442 2

2 1 GND 2.2uH SYS_3V8 LDO decouples are 4.7 uF for BOM consolidation. ind_vls252010 C397 4.7uF 0.22uF 10V GND C406 0603_CC 0603_CC SW2_3V3 1UH 4.7uF CC0402_25 16V L46 C427 0.22uF C402 0.1UF P1V8_VLDO4 0 1 PERI_PWR_EN GND GND P3V15_LICELL DNP 10V GND C411 4.7uF VCC_SDX C382 1.0UF 10V pf0100_bst_lx C396 10uF 10V VPWR <6,13> R520 VSNVS_3V0 LDOG SW3_LX SYS_3V8 0 VGEN5_3V3 25 35 32 26 27 36 28 34 31 29 33 30 0.1UF CC0402_25 16V C395 C429 4.7uF CC0402_25 6.3V GND DDR_1V35 GND V33 PMIC_VLDO34IN GND LDOG VPWR SW3IN LICELL VSNVS SW3LX SW3FB SWBST_5V VCC_SD

GNDREF2 VREFDDR SWBSTLX VGEN3_2V8

R519 0

EPAD

SWBSTFB C440 0.1UF CC0402_25 16V SW3

pf0100_vcore 37 49

CC0402_25 16V GND C421 0.1UF CC0402_25 16V C422 0.1UF

VINREFDDR

VIN2 PMIC_VHALF RC0402_25 38 24

GND

SYS_3V8 VDDOTP VHALF

R501 SYS_3V8 39 23

VLDO4

GNDREF CC0402_25 16V C439 0.1UF

40 22

P3V0_VLDO3

VCORE VLDO34IN

41 21

VIN VLDO3

42 20

GND

SW2FB VCOREDIG SYS_3V8

C438 0.1UF CC0402_25 16V

SYS_3V8 19

43 C420 4.7uF

VCOREREF SW2IN

44 18

MC32PF300XEP 0603_CC 10V C381 1.0UF 10V GND

SDA SW2LX

VCOREDIG 45 17

GND

SCL

VLDO2IN SW1AC437 0.1UF CC0402_25 SW1B16V SW2

46 16

SYS_3V8

VDDIO VLDO2

47 15

PWRON VLDO1

48 14

pf0100_vcoreref SW2_LX C424 4.7uF CC0402_25 C38510V 1.0UF 6.3V

VLDO1IN 13 C419 4.7uF GND P1V5_VLDO2 pf0100_scl pf0100_sda GND 1 DNP C436 68PF 50V CC0402_25 pf0100_pwron U41 0 C443 0.22uF L48 0 SD_VSEL STANDBY SW1AFB SW1BLX SW1BIN SW1BFB GNDREF1 SW1AIN INT RESETBMCU ICTEST SW1ALX GND 1UH P1V8_VLDO1 9 3 5 8 1 2 4 6 7 10 11 12 VDD_SOC_IN RC0402_25 RC0402_25 VGEN2_1V5 GND 2 C435 DNP 68PF 50V CC0402_25 ind_vls252010 R502 R508 R509 0 C418 0.22uF GND SYS_3V8 VDD_ARM_IN C431 22UF SYS_3V8 0603_CC 6.3V GND RC0402_25 GND C428 0.22uF SW1A_LX 0603_CC GND 0 0603_CC 10K NVCC_3V1 PMIC_SCL PMIC_SDA DNP R510 SW2_3V3 GND 22UF 0603_CC 6.3V C430 SW2_OUT GND 1 <22> <22> C414 4.7uF GND C408 4.7uF 10V 10V R515 1UH 0 PMIC_INT_B R503 L45 PMIC_VLDO2IN GND GND

PMIC_ON_REQ PMIC_PWRON 2 SW1B_LX ind_vls252010 <6> NVCC_3V1 SH13 SH0805_40 SW2_3V3 SOLDER SHORT 0 <6> 1 DNP <20> CC0402_25 16V C391 0.1UF C410 22UF 0603_CC 6.3V L47 R514 1UH GND VSNVS_3V0 SYS_3V8 R522 DNP 100K R511 2 SW2_3V3 ind_vls252010 0603_CC C409 22UF 6.3V P1V375_VDDARM_SW1A GND GND 0 J23 C 0603_CC 6.3V C416 22UF R507 100K HDR 1X2 2 1 POR_B PMIC_STBY_REQ DNP VSNVS_3V0 SH10 SH0805_40 R521 D32 LED Green C415 22UF 0603_CC 6.3V <6> SOLDER SHORT A GND P1V375_VDDSOC_SW1B GND SYS_3V8 R506 1K <6,9,17,20,21> PMIC-ON LED DNP VDD_ARM_IN C399 0.01uF 25V CC0402_25 C SH12 SH0805_40 D29 pmic_pwr_on_led R523 330 RC0402_25 SOLDER SHORT DNP RB521S30T1G A V33 VDD_SOC_IN SW2_3V3 Note: This block is used to compensate the weak output drive of PMIC_ON_REQ in TO1.0. TO1.2 or later does not need this.

Figure 5. Schematic part 3

Powering an i.MX 6SX-based system using the PF3000 PMIC, Rev. 1.0 NXP Semiconductors 8 Schematics TP101 DNP C260 22UF 0603_CC 6.3V GND C261 22UF 0603_CC 6.3V VDD_SOC_CAP DNP C242 22UF 0603_CC 6.3V C259 0.22UF 10V 0402_cc GND TP100 C243 22UF 0603_CC 6.3V C258 0.22UF 10V 0402_cc C241 0.22UF 10V 0402_cc C257 0.22UF 10V 0402_cc TP106 C265 4.7uF 6.3V 0402_CC C269 4.7uF 6.3V 0402_CC GND C240 0.22UF 10V 0402_cc C256 0.22UF 10V 0402_cc GND VDD_HIGH_CAP C264 0.22UF 10V 0402_cc C268 0.22UF 10V 0402_cc C239 0.22UF 10V 0402_cc C254 0.22UF 10V 0402_cc VDD_SOC_CAP C263 4.7uF 6.3V 0402_CC C238 0.22UF 10V 0402_cc C253 0.22UF 10V 0402_cc TP105 GND VDD_ARM_CAP C271 0.22UF 10V 0402_cc NVCC_PLL_OUT GND C262 0.22UF 10V 0402_cc PCIE_VP_CAP C236 0.22UF 10V 0402_cc C252 0.22UF 10V 0402_cc VDD_SNVS_CAP GND J16 P17 R2 R3 R6 R17 R20 R21 T15 U6 U21 K16 J9 J10 N10 N11 N12 N13 N14 N17 P6 T7 T8 T9 T10 T11 T12 T13 T14 T16 M18 V9 W19 W22 W23 Y13 Y20 AA3 AA5 AA18 AA20 AB3 AB6 AB19 AB21 Y23 C18 J12 J13 J14 L16 M16 J7 J8 J11 K7 L7 M7 N7 N16 R7 R8 R9 R10 R11 W21 Y7 Y11 Y15 Y17 AA2 AB23 AC1 AC6 AC19 AC21 AC23 L18 Y22 U20 R16 U17 U18 P7 P16 R12 R13 R14 R15 Y10 AA10 J15 N9 R22 R23 T6 T17 U7 V2 V3 V8 VSS95 VSS64 VSS72 VSS73 VSS74 VSS75 VSS76 VSS77 VSS78 VSS79 VSS80 VSS81 VSS90 VSS92 VSS93 VSS94 VSS96 VSS97 VSS98 VSS99 VSS65 VSS66 VSS67 VSS68 VSS69 VSS70 VSS71 VSS82 VSS83 VSS84 VSS85 VSS86 VSS87 VSS88 VSS89 VSS91 VSS100 VSS101 VSS103 VSS104 VSS107 VSS110 VSS112 VSS113 VSS114 VSS115 VSS116 VSS117 VSS118 VSS119 VSS102 VSS105 VSS106 VSS108 VSS109 VSS111 VSS120 VSS121 VSS122 VSS123 VSS124 VSS125 PCIE_VP PCIMX6X4EVM10AB NVCC_PLL PCIE_VPTX NGND_KEL0 VDD_SNVS_CAP VDD_ARM_CAP_5 VDD_ARM_CAP_6 VDD_ARM_CAP_7 VDD_SOC_CAP_3 VDD_SOC_CAP_4 VDD_ARM_CAP_1 VDD_ARM_CAP_2 VDD_ARM_CAP_3 VDD_ARM_CAP_4 VDD_ARM_CAP_8 VDD_ARM_CAP_9 VDD_SOC_CAP_1 VDD_SOC_CAP_2 VDD_SOC_CAP_5 VDD_SOC_CAP_6 VDD_SOC_CAP_7 VDD_SOC_CAP_8 VDD_SOC_CAP_9 VDD_HIGH_CAP_1 VDD_HIGH_CAP_2 VDD_SOC_CAP_10 VDD_SOC_CAP_13 VDD_SOC_CAP_14 VDD_SOC_CAP_15 VDD_SOC_CAP_16 VDD_SOC_CAP_17 VDD_SOC_CAP_11 VDD_SOC_CAP_12 VDD_SOC_CAP_18 VDD_SOC_CAP_19 VDD_SOC_CAP_20 VDD_SOC_CAP_21 VDD_SOC_CAP_22 VDD_SOC_CAP_23 V4 LDO_2P5 LDO_1P1 LDO_PCIE LDO_ARM LDO_SNVS LDO_SOC VDD_ARM_IN_7 VDD_SOC_IN_4 VDD_SOC_IN_11 VSS1 VSS10 VSS11 VSS14 VSS40 VSS54 VDD_ARM_IN_2 VDD_ARM_IN_3 VDD_ARM_IN_4 VDD_ARM_IN_5 VDD_ARM_IN_6 VDD_SOC_IN_1 VDD_SOC_IN_2 VDD_SOC_IN_3 VDD_SOC_IN_5 VDD_SOC_IN_6 VDD_SOC_IN_7 VDD_SOC_IN_8 VDD_SOC_IN_9 VDD_SOC_IN_10 VDD_SOC_IN_12 VDD_SOC_IN_13 VDD_SOC_IN_14 VDD_SOC_IN_15 VDD_SOC_IN_16 VDD_SOC_IN_17 VDD_SNVS_IN VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS12 VSS13 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS27 VSS29 VSS30 VSS31 VSS34 VSS35 VSS36 VSS37 VSS38 VSS39 VSS41 VSS42 VSS43 VSS44 VSS45 VSS46 VSS47 VSS48 VSS49 VSS50 VSS51 VSS52 VSS53 VSS55 VSS56 VSS57 VSS58 VSS59 VSS60 VSS61 VSS62 VDD_ARM_IN_1 VDD_HIGH_IN_1 VDD_HIGH_IN_2 VSS24 VSS25 VSS26 VSS28 VSS32 VSS33 VSS63 U1A J2 J3 J6 L8 L2 L3 L6 L9 F2 F3 P9 A1 K8 K9 P8 A6 B3 B6 K6 H8 H9 N6 D9 C9 N8 C2 C3 C5 D7 H6 H7 N2 N3 M8 G6 G7 G8 M9 J17 J20 J21 L15 L10 L11 L12 L13 L14 L17 F20 K10 K17 K12 K13 K14 K15 K11 P10 P11 P12 P13 P14 P15 V15 A23 D17 N15 D13 D15 D19 H11 H13 H14 H15 U14 U15 H10 H12 H16 H17 D11 M15 M12 M10 M11 M13 M14 M17 M20 M22 M23 GND C234 0.22UF 10V 0402_cc C251 0.22UF 10V 0402_cc VDD_SNVS_IN C270 0.22UF 10V 0402_cc GND GND GND C232 0.22UF 10V 0402_cc C249 0.22UF 10V 0402_cc R321 0 VDD_HIGH_IN C231 0.22UF 10V 0402_cc C248 0.22UF 10V 0402_cc VSNVS_3V0 C DNP D25 RB521S30T1G C247 0.22UF 10V 0402_cc A C235 22UF 0603_CC 6.3V VDD_ARM_IN C246 0.22UF 10V 0402_cc C267 0.22UF 10V 0402_cc C230 22UF 0603_CC 6.3V C266 4.7uF 6.3V 0402_CC C244 22UF 0603_CC 6.3V GND C245 22UF 0603_CC 6.3V R375RC0805_OV 0 VDD_SOC_IN VGEN6_3V0

Figure 6. Schematic part 4

Powering an i.MX 6SX-based system using the PF3000 PMIC, Rev. 1.0 NXP Semiconductors 9 Schematics

Note: When U40 is populated, need to populate these four termination resistors (HCSL-to-LVDS) U1B NVCC_3V1 for PCIe reference clock to i.MX6SX.

W17 U11 <20> ONOFF MPCIE_3V3 V17 ONOFF NVCC_JTAG <4,9,17,20,21> POR_B POR V10 VDD_SNVS_IN JTAG_TCK <17> W14 JTAG_TCK W12 <21> BOOT_MODE0 JTAG_TMS <17> C365 W15 BOOT_MODE0 JTAG_TMS V12 <21> BOOT_MODE1 JTAG_TDI <17> 0.1uF BOOT_MODE1 JTAG_TDI W9 DNP DNP 25V Y16 JTAG_TDO V13 JTAG_TDO <17> R461 R462 <21> TEST_MODE JTAG_TRST_B <17> 0402_cc TEST_MODE JTAG_TRST U9 140 140

NVCC_JTAG JTAG_MOD <17> V14 JTAG_MOD <21> SNVS_TAMPER SNVS_TAMPER GND <4> V16 AA22 PMIC_STBY_REQ W16 CCM_PMIC_STBY_REQ CCM_CLK1_N AA23 CLK1_N <16> <4> PMIC_ON_REQ SNVS_PMIC_ON_REQ CCM_CLK1_P CLK1_P <16> TP65 DNP DNP VDDHIGH_CAP

NVCC_PLL R459 R460 XTALI AB22 W18 TP66 75 75 XTALO AC22 XTALI CCM_CLK2 DNP XTALO U1G

R18 10M VDD_SNVS_CAP V18 IMX_OTG_VBUS GPANAIO RTC_XTALI AB20 VDDHIGH_IN GND W20 Y21 TP64 Y1 RTC_XTALO AC20 RTC_XTALI USB_OTG1_VBUS USB_OTG1_DN AA21 USB_OTG1_DN <11> RTC_XTALO USB_OTG1_DP USB_OTG1_DP <11> 3 GND2 4 32.768kHz C312 V19 2 1 V4 0.47uF USB_OTG1_CHD VDD_USB_CAP GND1 1 2 Y2 16V 0402_cc AA17 24MHZ LDO_USB VDD_USB_CAP C6 C7 PCIMX6X4EVM10AB R19 18PF 18PF C8 C9 GND C313 C314 2.2M 50V 50V 22PF 22PF USB_HOST_VBUS 0.22UF 10uF 0402_CC 0402_CC 25V 25V 10V 10v 0402_cc 0402_cc Y18 Y19 0402_cc 0603_CC USB_OTG2_VBUS USB_OTG2_DN AA19 USB_HOST_DN <11,16> C316 VGEN1_1V2 USB_OTG2_DP USB_HOST_DP <11,16> 0.47uF GND GND GND 16V AA6 Y5 0402_cc NVCC_USB_H USB_H_DATA Y6 HSIC_DATA <11> C350 C317 USB_H_STROBE HSIC_STROBE <11> GND 4.7uF 0.22UF V4 6.3V 10V PCIMX6X4EVM10AB 0402_CC 0402_cc

GND

Pin G11 & G12 share the same de-coupling capacitor.

TP88 TP86 TP89 TP67 TP68 TP87 PERI_3V3 U1L

G12 A15 R79 0 PCIE_WAKE_B <16> NVCC_SD1 SD1_CLK B15 R87 0 Pin G15 & G16 share the same C291 SD1_CMD PCIE_DIS_B <16> 0.22UF B16 R72 0 ACC_INT <18> de-coupling capacitor on Pin G14. 10V SD1_DATA0 A16 R73 0 0402_cc SD1_DATA1 B14 R74 0 PWM4_OUT <13> NVCC_SD1 SD1_DATA2 A14 R75 0 PWM3_OUT <13> ALS_COMP_INT <18> GND SD1_DATA3 NVCC_3V1 U1P

G11 F12 R53 10 NVCC_SD2 SD2_CLK F11 SD2_CLK <9> G16 C23 SD2_CMD SD2_CMD <9> NVCC_KEY KEY_COL0 C22 SD3_CD <9> G13 KEY_COL1 B23 SD3_RST_B <9> SD2_DATA0 F13 SD2_DATA0 <9> KEY_COL2 B22 UART5_RTS_B <19> SD2_DATA1 F10 SD2_DATA1 <9> KEY_COL3 A22 UART5_TXD <19> TP93 NVCC_3V1 NVCC_SD2 SD2_DATA2 G10 SD2_DATA2 <9> KEY_COL4 I2C3_SCL <22> SD2_DATA3 SD2_DATA3 <9> A21 KEY_ROW0 B21 SD3_WP <9> SD4_VSELECT C294 Y12 R94 10 NVCC_KEY KEY_ROW1 C21 0.22UF SD3_CLK W13 SD3_CLK <9> KEY_ROW2 D21 UART5_CTS_B <19> UART5_RXD <19> 10V SD3_CMD SD3_CMD <9> KEY_ROW3 D22 0402_cc AA11 KEY_ROW4 I2C3_SDA <22> NVCC_1V8 U12 SD3_DATA0 W10 SD3_DATA0 <9> GND NVCC_HIGH SD3_DATA1 AA15 SD3_DATA1 <9> G15 A20 V11 SD3_DATA2 Y14 SD3_DATA2 <9> NVCC_GPIO GPIO1_IO00 B20 I2C1_SCL <22> C297 NVCC_LOW SD3_DATA3 AA14 SD3_DATA3 <9> GPIO1_IO01 C20 I2C1_SDA <22> 0.22UF SD3_DATA4 AA13 SD3_DATA4 <9> GPIO1_IO02 D20 I2C2_SCL <22> SD3_DATA5 SD3_DATA5 <9> GPIO1_IO03 I2C2_SDA <22> 10V NVCC_HIGH/LOW AA12 A19 0402_cc SD3_DATA6 W11 SD3_DATA6 <9> GPIO1_IO04 B19 UART1_TXD <17> VCC_SD4 SD3_DATA7 SD3_DATA7 <9> GPIO1_IO05 C19 UART1_RXD <17> NVCC_3V1 GND GPIO1_IO06 A18 UART2_TXD <17> GPIO1_IO07 UART2_RXD <17> R92 0 U10 AB12 R83 10 V4 B18 NVCC_SD4 SD4_CLK SD4_CLK <9> GPIO1_IO08 USB_OTG1_OC <11>

AB13 NVCC_GPIO1 D18 NVCC_1V8 C301 SD4_CMD Y9 SD4_CMD <9> GPIO1_IO09 E19 USB_OTG1_PWR <11> R93 0 0.22UF SD4_RESET SD4_RST_B <9> GPIO1_IO10 E18 USB_OTG1_ID <11> 10V AC10 GPIO1_IO11 A17 USB_OTG2_OC <11> SD4_DATA0 SD4_DATA0 <9> GPIO1_IO12 USB_OTG2_PWR <11> DNP 0402_cc AB10 B17 SD4_DATA1 AC14 SD4_DATA1 <9> GPIO1_IO13 WDOG_B <20> GND SD4_DATA2 AB14 SD4_DATA2 <9> SD4_DATA3 SD4_DATA3 <9> V4 AC13 PCIMX6X4EVM10AB NVCC_SD4 SD4_DATA4 AC12 SD4_DATA4 <9,13> SD4_DATA5 AC11 SD4_DATA5 <9,13> SD4_DATA6 AB11 SD4_DATA6 <9> SD4_DATA7 SD4_DATA7 <9>

PCIMX6X4EVM10AB

U1N TP124

NVCC_3V1 U1O NVCC_3V1 U8 AB8 TP144 NVCC_NAND NAND_CE0 AC9 QSPI2A_DATA2 <10> G14 F16 C308 NAND_CE1 QSPI2A_DATA3 <10> NVCC_QSPI QSPI1A_SS0 F17 0.22UF AB7 C307 QSPI1A_SS1 E17 QSPI1A_SS1_B <10,14> HDMI_INT <13> 10V NAND_ALE AB9 R85 0 QSPI2A_SS0_B <10> 0.22UF QSPI1A_SCLK E13 0402_cc NAND_CLE AA9 QSPI2A_SCLK <10> 10V QSPI1A_DQS QSPI1A_DQS <10,14> NAND_RE AA7 QSPI2B_DATA3 <10> 0402_cc C16 NAND_WE AC8 QSPI2B_DATA2 <10> QSPI1A_DATA0 E16 PERI_PWR_EN <4,13> PMIC_INT_B <4> GND NAND_WP AC7 QSPI2A_DATA0 <10> QSPI1A_DATA1 D16 NAND_READY QSPI2A_DATA1 <10> GND QSPI1A_DATA2 C17 CABC_EN <13> CAP_TCH_INT_B <13> TP129 QSPI1A_DATA3 TP76 TP77

V4 V7 NAND_DATA00 AA8 QSPI2B_DATA1 <10> F14 UART3_TXD

NAND_DATA01 QSPI2B_DATA0 <10> V4 QSPI1B_SS0 W8 R86 0 NVCC_QSPI F15 NAND_DATA02 V6 QSPI2B_SCLK <10> QSPI1B_SS1 E15 UART3_RXD QSPI1B_SS1_B <10,14> NAND_DATA03 W7 QSPI2B_SS0_B <10> QSPI1B_SCLK C13 NVCC_NAND NAND_DATA04 W5 QSPI2B_DQS TP145 QSPI1B_DQS TP119 QSPI1B_DQS <10,14> NAND_DATA05 Y8 C14 TP120 NAND_DATA06 W6 QSPI2A_DQS BT_PWD_B <19> QSPI1B_DATA0 E14 TP121 NAND_DATA07 TP125 TP130 QSPI1B_DATA1 D14 TP131 QSPI1B_DATA2 C15 PCIMX6X4EVM10AB DNP DNP QSPI1B_DATA3 CAN1_2_STBY <14> C335 C336 30PF 30PF PCIMX6X4EVM10AB 50V 50V 0402_CC 0402_CC GND GND GND

VDD_SOC_CAP L32 1 2 VDD_AFE_1P2 TP69 TP71 TP70 TP72 VGEN5_3V3 120OHM C292 4.7uF U1I 6.3V R96 0 VDDA_ADC_3P3 0402_CC L21 L23 VDD_AFE_1P2 VADC_IN0 VADC_IN0 <13> C303 GND TP73 0.1uF U1J VGEN5_3V3 N18 L22 VDDA_AFE_3P3 VADC_IN1 VADC_IN1 <13> 25V 0402_cc VDDA_AFE_3P3 K23 VADC_IN2 VADC_IN2 <13> K22 U13 AC15 VADC_IN3 VADC_IN3 GND C298 GND VDDA_ADC_3P3 ADC1_IN0 AB15 ADC1_IN0 <18> ADC1_IN1 <18> 0.47UF R97 0 ADC_VREFH AA16 ADC1_IN1 AC16 VDDA_AFE_3P3 ADC1_IN2 <18> 6.3V K21 VADC_AFE_BANDGAP ADC_VREFH ADC1_IN2 AB16 VADC_AFE_BANDGAP ADC1_IN3 <18> 0402_cc C305 C306 ADC1_IN3 C299 C300 1.0UF 0.1uF GND V4 0.1uF 1000pF 10V 25V U16 AC17 ADC2_IN0 <18> PCIMX6X4EVM10AB 25V 50V 0402_cc 0402_cc ADC_VREFL ADC2_IN0 AB17 ADC2_IN1 ADC2_IN1 <18>

0402_cc 0402_cc VDDA_ADC_3P3 AC18 ADC2_IN2 AB18 ADC2_IN2 <18> ADC2_IN3 ADC2_IN3 <18> GND V4 GND PCIMX6X4EVM10AB

Figure 7. Schematic part 5

Powering an i.MX 6SX-based system using the PF3000 PMIC, Rev. 1.0 NXP Semiconductors 10 Schematics ENET1_REF_CLK_IN <15> DNP C346 0.01uF 25V 0402_CC DNP R390 47K DNP R391 47K GND PERI_3V3 Note: This block is reserved for testing external ENET reference clock to i.MX6SX TP63 ENET_MDIO <15> ENET_RST_B <15> BT_WAKEUP <19> ENET_REF_CLK_25M <15> ENET_MDC <15> PCIE_RST_BPCIE_PWR_EN <16> <16> ENET_PWR_EN_B <15> ENET_INT <15> PCIE_RX_NPCIE_RX_P <16> <16> PCIE_TX_N <16> PCIE_TX_P <16> UNC2 <20> UNC1 <20> CODEC_INT <12> KEY_F KEY_F HP_DET_B <12> AUD_TXCAUD_TXFS <12> <12> AUD_MCLKAUD_RXD <12> <12> I2C4_SDA <22> AUD_TXD <12> I2C4_SCL <22> R338 200 1% ENET_REF_CLK_IN R339 10 OSC_32K GND B7 F7 D6 F9 E7 E6 D5 A7 C6 C7 P22 M21 P21 P23 P20 T19 N23 R19 P19 N21 N19 N20 N22 U19 M19 L19 L20 PCIMX6X4EVM10AB PCIMX6X4EVM10AB PCIMX6X4EVM10AB ENET1_COL ENET2_COL ENET1_CRS ENET2_CRS ENET1_MDC CSI_MCLK ENET1_MDIO PCIE_TX_P PCIE_TX_N PCIE_RX_P

PCIE_RX_N PCIE_REXT CSI_VSYNC CSI_PIXCLK CSI_HSYNC

CSI_DATA01 CSI_DATA02 CSI_DATA03 CSI_DATA04 CSI_DATA05 CSI_DATA06 CSI_DATA07 CSI_DATA00

ENET1_TX_CLK ENET2_TX_CLK PCIE_VPTX ENET1_RX_CLK ENET2_RX_CLK

NVCC_ENET NVCC_CSI

V4 V4 V4 NVCC_CSI U1F PCIE_VPH NVCC_ENET U1M U1H P18 F6 R18 C309 0.22UF 10V 0402_cc 0.22UF 10V 0402_cc C295 0.22UF C296 10V 0402_cc GND GND GND PERI_3V3 NVCC_1V8 VDD_HIGH_CAP RGMII2_RXD3 <15> RGMII1_RXD0RGMII1_RXD2 <15> RGMII1_RXD3 <15> <15> RGMII2_RXD2 <15> RGMII2_RXDV <15> RGMII1_RXCLKRGMII1_RXDV <15> <15> RGMII2_RXD0RGMII2_RXD1 <15> <15> RGMII1_RXD1 <15> RGMII2_RXCLK <15> RGMII1_TXD0 <15> RGMII2_TXD3 <15> RGMII2_TXEN <15> RGMII1_TXD1RGMII1_TXD3 <15> <15> RGMII2_TXCLK <15> RGMII1_TXD2 <15> RGMII1_TXCLKRGMII1_TXEN <15> <15> RGMII2_TXD0RGMII2_TXD1RGMII2_TXD2 <15> <15> <15> TP139 TP135 LVDS_DATA3_N <13> LVDS_DATA0_NLVDS_DATA0_P <13> <13> LVDS_CLK_N <13> LVDS_DATA1_NLVDS_DATA1_P <13> <13> LVDS_DATA2_NLVDS_DATA2_P <13> <13> LVDS_DATA3_P <13> LVDS_CLK_P <13> TP134 LCD1_DATA1LCD1_DATA2 <13,21> <13,21> LCD1_DATA9LCD1_DATA10 <13,21> <13,21> LCD1_DATA14 <13,21> LCD1_DATA18 <13,21> LCD1_DATA21LCD1_DATA22 <13,21> <13,21> TP138 LCD1_CLK <13> LCD1_VSYNCLCD1_RESET <13> <13> LCD1_DATA4LCD1_DATA5 <13,21> <13,21> LCD1_DATA13 <13,21> LCD1_DATA16LCD1_DATA17 <13,21> <13,21> LCD1_ENABLELCD1_HSYNC <13> <13> LCD1_DATA0 <13,21> LCD1_DATA3 <13,21> LCD1_DATA6LCD1_DATA7LCD1_DATA8 <13,21> <13,21> <13,21> LCD1_DATA11LCD1_DATA12 <13,21> <13,21> LCD1_DATA15 <13,21> LCD1_DATA19LCD1_DATA20 <13,21> <13,21> LCD1_DATA23 <13,21> Pin R18 & T18 share the same de-coupling capacitor. E8 C11 A10 E11 B10 E12 B13 D10 C10 B11 E22 J19 J18 H23 G21 E20 A11 D8 E9 A9 B9 A8 B8 D23 C12 D12 B12 K18 H18 G19 F19 F18 U22 C8 K20 K19 G23 G22 G20 E10 T21 J23 H20 F22 V21 U23 T20 E23 V20 T22 E21 J22 H22 H19 G18 F23 A12 A13 V22 F21 V23 T23 H21 PCIMX6X4EVM10AB PCIMX6X4EVM10AB PCIMX6X4EVM10AB LCD1_CLK RGMII1_TD3 RGMII1_TD2 RGMII2_TD3 RGMII1_TD0 RGMII1_TD1 RGMII2_TD0 RGMII2_TD1 RGMII2_TD2 RGMII1_RD2 RGMII1_RD3 RGMII1_RD0 RGMII1_RD1 RGMII2_RD0 RGMII2_RD1 RGMII2_RD2 RGMII2_RD3 RGMII1_TXC RGMII2_TXC RGMII2_RXC RGMII1_RXC LVDS_CLK_P LVDS_CLK_N LCD1_RESET LCD1_VSYNC LCD1_HSYNC LCD1_DATA00 LCD1_DATA09 LCD1_DATA18 LCD1_DATA01 LCD1_DATA05 LCD1_DATA06 LCD1_DATA07 LCD1_DATA08 LCD1_DATA10 LCD1_DATA14 LCD1_DATA16 LCD1_DATA17 LCD1_DATA23 LCD1_DATA04 LCD1_DATA11 LCD1_DATA15 LCD1_DATA19 LCD1_DATA21 LCD1_DATA22 LCD1_DATA02 LCD1_DATA03 LCD1_DATA12 LCD1_DATA13 LCD1_DATA20 LCD1_ENABLE

LVDS_DATA0_P LVDS_DATA3_P LVDS_DATA1_P LVDS_DATA2_P LVDS_DATA1_N LVDS_DATA3_N LVDS_DATA0_N LVDS_DATA2_N RGMII1_TX_CTL RGMII2_TX_CTL RGMII1_RX_CTL RGMII2_RX_CTL

NVCC_LVDS NVCC_LCD1

NVCC_RGMII1 NVCC_RGMII2

V4 V4 V4 NVCC_LVDS U1E NVCC_RGMII1 NVCC_RGMII2 NVCC_LCD1 U1K U1D T18 F8 G9 G17 0.01uF 0.01uF C362 25V 0402_CC C361 25V 0402_CC 0.22UF 0402_cc C310 10V GND 0.22UF 0402_cc 0.22UF 10V C289 10V C290 0402_cc GND GND VDD_HIGH_CAP NVCC_3V1 NVCC_RGMII1 NVCC_RGMII2

Figure 8. Schematic part 6

Powering an i.MX 6SX-based system using the PF3000 PMIC, Rev. 1.0 NXP Semiconductors 11 Schematics R54 470 R55 470 C32 0.22UF 10V 0402_cc C20 0.22UF 10V 0402_cc DRAM_SDCLK0_P DRAM_SDCLK0_N DRAM_SDCLK0_P DRAM_SDCLK0_N C19 0.22UF 10V 0402_cc C31 0.22UF 10V 0402_cc C18 0.22UF 10V 0402_cc C30 0.22UF 10V 0402_cc Note: CLK Place R54 close to termination: U2 Note: Place R55 close to U3 CLK termination: C29 0.22UF 10V 0402_cc C17 0.22UF 10V 0402_cc DRAM_DATA[0:31] DRAM_DATA[0:31] C28 0.22UF 10V 0402_cc C16 0.22UF 10V 0402_cc GND GND C15 0.22UF 10V 0402_cc C27 0.22UF 10V 0402_cc DRAM_DATA0 DRAM_DATA7 DRAM_SDQS0_N DRAM_DATA30 DRAM_DATA14 DRAM_SDQS3_N DRAM_DATA21 DRAM_DATA6 DRAM_SDQS2_P DRAM_SDQS2_N DRAM_SDQS0_P DRAM_DATA24 DRAM_DATA27 DRAM_DATA31 DRAM_DATA12 DRAM_SDQS3_P DRAM_DATA16 DRAM_DATA17 DRAM_DATA23 DRAM_DATA18 DRAM_DATA20 DRAM_DATA22 DRAM_DATA19 DRAM_DATA3 DRAM_DATA2 DRAM_DATA5 DRAM_DATA1 DRAM_DATA4 DRAM_DATA25 DRAM_DATA29 DRAM_DATA28 DRAM_DATA26 DRAM_DATA8 DRAM_DATA13 DRAM_DATA9 DRAM_DATA11 DRAM_DATA10 DRAM_DATA15 DRAM_SDQS1_P DRAM_SDQS1_N C2 J1 J9 L1 L1 L9 E3 F7 H8 G2 F8 H3 H8 D7 C3 G3 B7 G3 B7 F3 F3 C7 M7 L9 F2 F8 H3 H7 D7 C3 E3 F7 F2 G2 H7 C8 C2 A7 A2 C8 A2 B8 A3 C7 M7 J1 J9 B8 A3 A7 U2 U3 C26 0.22UF 10V 0402_cc MT41K256M16HA-125:E C14 0.22UF 10V 0402_cc MT41K256M16HA-125:E DQ0 DQ1 DQ5 DQ6 DQ3 DQ4 DQ5 DQ8 DQ9 DQ2 DQ3 DQ4 DQ7 DQ8 DQ9 DQ0 DQ1 DQ2 DQ6 DQ7

DQ10 DQ11 DQ12 DQ13 DQ10 DQ13 DQ14 DQ15 DQ14 DQ15 DQ11 DQ12

LDQS LDQS LDQS LDQS

UDQS UDQS UDQS UDQS

NC_J1 NC_J9 NC_J1 NC_J9 NC_L1 NC_L1 NC_L9 NC_L9 VSSQ9

NC_M7 VSSQ9 NC_M7

G9 G9

VSSQ8 VSSQ8

G1 G1

VDDQ9 VSSQ7 VDDQ9 VSSQ7

H9 F9 H9 F9

VDDQ8 VSSQ6 VDDQ8 VSSQ6

C25 0.22UF 10V 0402_cc C13 0.22UF 10V 0402_cc H2 E8 H2 E8

VDDQ7 VSSQ5 VDDQ7 VSSQ5

F1 E2 F1 E2

VDDQ6 VSSQ4 VDDQ6 VSSQ4

E9 D8 E9 D8

VDDQ5 VSSQ3 VDDQ5 VSSQ3

D2 D1 D2 D1

VDDQ4 VSSQ2 VDDQ4 VSSQ2

C9 B9 C9 B9

VDDQ3 VSSQ1 VDDQ3 VSSQ1

C1 B1 C1 B1

VDDQ2 VDDQ2

C12 0.22UF 10V 0402_cc C24 0.22UF 10V 0402_cc A8 A8

VDDQ1 VSS12 VDDQ1 VSS12

A1 T9 A1 T9

VSS11 VSS11

GND GND T1 T1

VDD9 VSS10 VDD9 VSS10

R9 P9 R9 P9

VDD8 VSS9 VDD8 VSS9

R1 P1 R1 P1

VDD7 VSS8 VDD7 VSS8

N9 M9 N9 M9

VDD6 VSS7 VDD6 VSS7

C23 0.22UF 10V 0402_cc C11 0.22UF 10V 0402_cc N1 M1 N1 M1

VDD5 VSS6 VDD5 VSS6

K8 J8 K8 J8

VDD4 VSS5 VDD4 VSS5

K2 J2 K2 J2

VDD3 VSS4 VDD3 VSS4

G7 G8 G7 G8

VDD2 VSS3 VDD2 VSS3

4G_DDR3_SDRAM_256MX16 4G_DDR3_SDRAM_256MX16 D9 E1 D9 E1

VDD1 VSS2 VDD1 VSS2

B2 B3 B2 B3

VSS1 VSS1

A9 A9 DDR_1V35 DDR_1V35 A2 A7 LDM A0 A4 CKE VREFDQ A0 A1 A3 A4 A5 A6 A8 A9 A10/AP A11 A12/BC A13 A14 BA0 BA1 BA2 CS RAS CAS WE CK CK CKE RESET ZQ ODT VREFCA VREFDQ UDM A1 A2 A3 A6 A7 A8 A9 A10/AP A11 A12/BC A13 A14 BA0 BA1 BA2 CS RAS CAS WE CK CK RESET ZQ ODT LDM UDM A5 VREFCA C10 22UF 0603_CC 6.3V C22 22UF 0603_CC 6.3V J7 J3 J3 J7 L2 L2 L3 L3 L7 L8 L7 L8 E7 K9 P7 P8 P2 T8 T3 T7 K9 K1 P7 P3 T8 T3 T7 K1 E7 P2 K3 K7 T2 K3 K7 T2 P3 P8 H1 N3 N2 R8 R3 R7 N8 H1 D3 N2 R8 R2 R3 R7 N8 D3 N7 N7 R2 N3 M2 M3 M8 M2 M3 M8 GND GND DRAM_DQM0 DRAM_DQM2 DRAM_DQM3 DRAM_DQM1 DRAM_ADDR0 DRAM_ADDR1 DRAM_ADDR2 DRAM_ADDR3 DRAM_ADDR4 DRAM_ADDR5 DRAM_ADDR6 DRAM_ADDR7 DRAM_ADDR8 DRAM_ADDR9 DRAM_ADDR10 DRAM_ADDR11 DRAM_ADDR12 DRAM_ADDR13 DRAM_ADDR14 DRAM_SDBA0 DRAM_SDBA1 DRAM_SDBA2 DRAM_CS0_B DRAM_RAS_B DRAM_CAS_B DRAM_SDWE_B DRAM_SDCLK0_P DRAM_SDCLK0_N DRAM_SDCKE0 DRAM_RESET_B DRAM_ODT0 DRAM_ADDR0 DRAM_ADDR1 DRAM_ADDR2 DRAM_ADDR3 DRAM_ADDR4 DRAM_ADDR5 DRAM_ADDR6 DRAM_ADDR7 DRAM_ADDR8 DRAM_ADDR9 DRAM_ADDR10 DRAM_ADDR11 DRAM_ADDR12 DRAM_ADDR13 DRAM_ADDR14 DRAM_SDBA0 DRAM_SDBA1 DRAM_SDBA2 DRAM_CS0_B DRAM_RAS_B DRAM_CAS_B DRAM_SDWE_B DRAM_SDCLK0_P DRAM_SDCLK0_N DRAM_SDCKE0 DRAM_RESET_B DRAM_ODT0 C34 0.22UF 10V 0402_cc C282 0.22UF 10V 0402_cc C33 0.22UF 10V 0402_cc C281 0.22UF 10V 0402_cc GND GND DRAM_VREF DRAM_VREF DRAM_ZQ0 DRAM_ZQ1 R21 240 RC0402_25 1% R23 240 RC0402_25 1% DRAM_ADDR[0:15] DRAM_ADDR[0:15] GND GND VDD_HIGH_CAP 0402_CC R323 10K R324C280 0 0.22UF 10V 0402_cc GND GND R20 10K 0402_CC R322 10K 0402_CC GND C273 0.22UF 10V 0402_cc GND DRAM_VREF R24 240 RC0402_25 1% GND DRAM_ADDR0 DRAM_ADDR2 DRAM_ADDR6 DRAM_ADDR8 DRAM_ADDR9 DRAM_ADDR11 DRAM_ADDR12 DRAM_ADDR14 DRAM_SDBA1 DRAM_SDBA2 DRAM_CS0_B DRAM_CS1_B DRAM_SDCKE0 DRAM_SDCKE1 DRAM_ODT0 DRAM_ODT1 DRAM_SDCLK0_P DRAM_SDCLK0_N DRAM_ADDR1 DRAM_ADDR3 DRAM_ADDR4 DRAM_ADDR5 DRAM_ADDR7 DRAM_ADDR10 DRAM_ADDR13 DRAM_ADDR15 DRAM_SDBA0 DRAM_RAS_B DRAM_CAS_B DRAM_SDWE_B DRAM_RESET_B NVCC_DRAM_2V5 ZQPAD DRAM_SDCLK0_N DRAM_DATA30 DRAM_SDQS3_P DRAM_SDQS3_N C21 10uF 10v 0603_CC P3 V4 E3 M2 C4 J4 D3 L4 K4 K3 M1 G4 F4 W3 H4 U3 M4 AA4 E5 M3 N4 Y4 H3 R4 G3 Y3 T3 U4 T4 P4 W4 E4 D4 M6 GND DDR_1V35 TP48 TP52 TP38 TP44 PCIMX6X4EVM10AB DRAM_CS0 DRAM_CS1 DRAM_RAS DRAM_CAS DRAM_VREF TP46 DRAM_ODT0 DRAM_ODT1 TP36 TP42 TP50 DRAM_SDWE DRAM_SDBA0 DRAM_SDBA1 DRAM_SDBA2 DRAM_RESET DRAM_ZQPAD Note: integrity for signal Test points measurement C279 4.7uF 6.3V 0402_CC DRAM_ADDR02 DRAM_ADDR07 DRAM_ADDR12 DRAM_ADDR00 DRAM_ADDR01 DRAM_ADDR03 DRAM_ADDR04 DRAM_ADDR05 DRAM_ADDR06 DRAM_ADDR08 DRAM_ADDR09 DRAM_ADDR10 DRAM_ADDR11 DRAM_ADDR13 DRAM_ADDR14 DRAM_ADDR15 DRAM_SDCKE0 DRAM_SDCKE1 DRAM_SDCLK0_P NVCC_DRAM_2P5 DRAM_SDCLK0_N V4 C276 4.7uF 6.3V 0402_CC GND DRAM_DATA00 DRAM_DATA01 DRAM_DATA02 DRAM_DATA03 DRAM_DATA05 DRAM_DATA06 DRAM_DATA07 DRAM_SDQS0_P DRAM_DQM0 DRAM_DATA08 DRAM_DATA11 DRAM_DATA12 DRAM_DATA13 DRAM_SDQS1_N DRAM_DQM1 DRAM_DATA16 DRAM_DATA18 DRAM_DATA19 DRAM_DATA20 DRAM_SDQS2_P DRAM_SDQS2_N DRAM_DATA25 DRAM_DATA26 DRAM_DATA27 DRAM_DATA28 DRAM_DATA30 DRAM_DATA31 DRAM_SDQS3_P DRAM_SDQS3_N NVCC_DRAM_1 NVCC_DRAM_2 NVCC_DRAM_3 NVCC_DRAM_6 NVCC_DRAM_7 NVCC_DRAM_8 NVCC_DRAM_9 NVCC_DRAM_11 NVCC_DRAM_12 NVCC_DRAM_13 DRAM_DATA04 DRAM_SDQS0_N DRAM_DATA09 DRAM_DATA10 DRAM_DATA14 DRAM_DATA15 DRAM_SDQS1_P DRAM_DATA17 DRAM_DATA21 DRAM_DATA22 DRAM_DATA23 DRAM_DQM2 DRAM_DATA24 DRAM_DATA29 DRAM_DQM3 NVCC_DRAM_4 NVCC_DRAM_5 NVCC_DRAM_10 U1C C278 0.22UF 10V 0402_cc J1 J5 L1 L5 F1 F5 V1 P2 T1 T2 K1 Y2 B2 B1 B5 A5 A3 A2 P5 T5 V5 P1 K2 E2 E1 Y1 B4 A4 K5 U2 N1 R1 H2 D1 D2 H5 N5 U5 U1 H1 C1 R5 G2 G1 G5 M5 W2 W1 AB1 AB4 AB2 AB5 AA1 AC5 AC2 AC3 AC4 DRAM_SDCLK0_P DRAM_ADDR0 DRAM_SDQS0_P DRAM_SDQS0_N DRAM_DATA0 TP57 TP56 TP58 Figure 9. Schematic part 7

Powering an i.MX 6SX-based system using the PF3000 PMIC, Rev. 1.0 NXP Semiconductors 12 Schematics N9 N8 M14 M12 M11 L12 K3 N12 N7 N3 N1 M13 M8 M7 M3 M2 M1 K12 M10 P1 N14 N6 M9 L3 L2 L1 L14 L13 K14 K13 K2 N13 N11 N10 DNP U4B MTFC8GLCDM NC_L3 NC_L2 NC_L1 NC_K3 NC_K2 NC_P1 NC_N9 NC_N8 NC_N6 NC_N7 NC_N3 NC_N1

NC_M9 NC_M8 NC_M7 NC_M3 NC_M2 NC_M1

NC_L14 NC_L13 NC_L12 NC_K12 NC_K14 NC_K13 NC_N14 NC_N13 NC_N12 NC_N11 NC_N10 NC_M10 NC_M14 NC_M12 NC_M11 NC_M13 NC_P2

1 P2

NC_P8 NC_K1

P8 K1

NC_P9 NC_J14

P9 J14

NC_P11 NC_J13

P11 J13

NC_P12 NC_J12

P12 J12

NC_P13 NC_J3

P13 J3

NC_P14 NC_J2

P14 J2

NC_J1

NC_H14

H14

NC_H13

H13

NC_H12

H12

NC_H3

NC_H2

NC_H1

RFU17 NC_G14

P7 G14

RFU16 NC_G13

P10 G13

RFU15 NC_G12

K7 G12

RFU14 NC_G2

K6 G2

RFU13 NC_G1

K10 G1

RFU12 NC_F14

J5 F14

RFU11 NC_F13

VCC_SD3 H5 F13

RFU10 NC_F12

G3 F12

RFU9 NC_F3

G10 F3

RFU8 NC_F2

F10

F2 3 RFU7 NC_F1

E9 F1

RFU6 NC_E14

IRLML6401 E8 E14

RFU5 NC_E13

E5 E13

RFU4 NC_E12

DNP R25 0 1 E10 E12

RFU3

EMMC5_0_RCLK NC_E3

Q12 C5 E3

RFU2 NC_E2

E2 2 RFU1 NC_E1

A6 E1 NC_D14

TP140 D14 C46 1.0UF 10V 0402_cc EMMC5_0_VSS EMMC5_0_VSS NC_A1 NC_A8 NC_A12 NC_A13 NC_A14 NC_B1 NC_B10 NC_B11 NC_C7 NC_C12 NC_C13 NC_C14 NC_D4 NC_D12 NC_A2 NC_A9 NC_A10 NC_A11 NC_B7 NC_B8 NC_B9 NC_B12 NC_B13 NC_B14 NC_C1 NC_C3 NC_C8 NC_C9 NC_C10 NC_C11 NC_D1 NC_D2 NC_D3 NC_D13 A9 B9 A1 A8 B1 A2 B7 B8 C8 C9 D1 D2 C7 D4 C1 C3 D3 DNP DNP A12 A13 A14 A10 A11 B12 B13 B14 B10 B11 C13 C14 C10 C11 D13 C12 D12 R50 10K MEM_3V1 2.2K Remove R51 when R25 is populated. R453 0 R452 0 These are reserved for eMMC5.0 part. R33 GND

Q11 MMBT3904T

3 2 GND DNP R464 100K 1 C44 4.7uF 10V 0603_CC DNP R28 10K GND GND VCC_SD4 10K C43 0.22UF 10V 0402_cc R52 SD3_PWR_ON 2 2 C45 1.0UF 10V 0402_cc C42 0.22UF 10V 0402_cc GND 4

DNP U5 NC7SZ08P5X

3 C 5 25V 0402_cc GND C364 0.1uF EMMC_VDDIM C38 0.22UF 10V 0402_cc MEM_3V1 2 1 D8 RB521S30T1G A R464 is reserved for testing only - turning on Q11 by default. GND Note: i) Place next to J4. ii) Remove R88 and R89 when populate U4. DNP 0 C2 N2 N5 P4 P6 C4 C6 M4 P5 P3 N4 R27 10K DNP U4A MTFC8GLCDM

VDDIM

VSSQ1 VSSQ2 VSSQ3 VSSQ4 VSSQ5 VCCQ1 VCCQ3 VCCQ2 VCCQ4 VCCQ5

R29 0 MEM_3V1 R32

VCC4 VSS4

K9 K8

VCC3 VSS3

H10

E6 GND VCC2 VSS2

MEM_3V1 F5 G5

VCC1 VSS1

eMMC 4GB E7 J10 1 R51 51 RC0402_25

C41 0.22UF 10V 0402_cc 3 2 DAT0 DAT1 DAT2 DAT3 DAT5 DAT6 DAT7 CMD CLK DAT4 RST GND VCC_SD3 GND B5 B6 B3 K5 A3 A4 A5 B2 B4 M5 M6 Q13 2N7002 C40 0.22UF 10V 0402_cc Power switch circuit for External SD Card (SD3) DNP DNP R51 is the VCC_SD3 discharge path when Q12 is off DNP R463 10K DNP DNP DNP DNP DNP DNP DNP DNP POR_B SD3_RST_B GND <6> 10V 0603_CC C37 4.7uF R37R36R35 0 0 R245 0 R31R30 0 R39 0 0 R40 0 0 R34R246 0 0 <4,6,17,20,21> eMMC 4.5 Footprint SD4_DATA4 SD4_RST_B SD4_DATA1 SD4_DATA2 SD4_DATA3 SD4_DATA5 SD4_DATA6 SD4_CMD SD4_DATA0 SD4_DATA7 SD4_CLK <6> <6,9> <6,9> <6,9> <6,9> <6,9> <6,9> <6,9> <6,9> <6,9,13> <6,9,13> 3 3 C36 47uF 10V 0805_CC 4 4 C50 47uF 10V 0805_CC VCC_SD3 C48 10uF 10v 0603_CC C39 0.1uF PERI_3V3 25V 0402_cc MEM_3V1 GND C49 0.1uF 25V 0402_cc 0.1uF 25V 0402_cc C47 GND GND GND GND GND S3 S4 S5 S1 S2 S3 S4 S5 S6 S6 S7 S7 4 4 3 6 3 6 S1 S2 S5 S6 4 3 6 S1 S2 S3 S4 S7 VDD VDD VSS1 VSS2 VSS1 VSS2 GND6 GND7 GND7 GND1 GND2 GND3 GND4 GND5 GND1 GND2 GND3 GND4 GND5 GND6 VDD VSS1 VSS2 GND1 GND2 GND3 GND4 GND5 GND6 GND7 8-bit SD For WiFi CONN CRD 19 CONN CONN CRD 19 CONN DAT3 DAT4 DAT5 DAT6 DAT7 CLK DAT3 DAT4 DAT5 DAT6 CLK CMD DAT0 DAT1 DAT2 CMD CD WP DAT0 DAT1 DAT2 DAT7 CD WP CONN CRD 19 CONN DAT3 DAT5 DAT6 WP J3 DAT0 DAT1 DAT2 DAT4 DAT7 CLK CMD CD J5 1 5 1 7 8 9 2 7 8 9 5 2 J4 10 11 14 15 13 14 15 10 11 12 13 12 9 1 7 8 5 2 10 11 12 15 13 14 BOOT SD CARD SD BOOT R430 100K TP3 VCC_SD3 0 0 0 0 SD4_WP SD4_CD R429 100K Either SD Card on SD4 or eMMC on SD4 is used as boot device TP92 DNP DNP DNP DNP 100K R434 0 0 0 0 SD3_CON_CLK R42 R43 R44 R45 PERI_3V3 R433 100K 10 R432 100K R255R256R257 0 0 R46 0 R47 R48 R258 0 R49 VCC_SD4 R26 R431 100K 5 5 SD2_DATA0 SD2_DATA1 SD2_DATA2 SD2_CLK SD2_CMD SD2_DATA3 SD3_CLK SD3_CD SD3_WP SD3_CMD SD3_DATA0 SD3_DATA4 SD3_DATA5 SD3_DATA7 SD3_DATA1 SD3_DATA2 SD3_DATA3 SD3_DATA6 SD4_DATA6 SD4_DATA0 SD4_DATA1 SD4_DATA2 SD4_DATA3 SD4_DATA4 SD4_DATA5 SD4_CLK SD4_CMD SD4_DATA7 <6> <6> <6> <6> <6> <6> SD4 - For Boot Code <6> <6> <6> <6> <6> <6> <6> <6> <6> <6> <6> <6> <6,9> <6,9> <6,9> <6,9> <6,9> <6,9> <6,9> <6,9> SD3 - For Primary External Card Slot (SD3.0) <6,9,13> <6,9,13> SD2 - for WiFi and SD Accessories

Figure 10. Schematic part 8

Powering an i.MX 6SX-based system using the PF3000 PMIC, Rev. 1.0 NXP Semiconductors 13 Schematics C318 0.1uF 25V 0402_cc GND MEM_3V1 DNP R342 47K ECSPI5_SCLK ECSPI5_MOSI ECSPI5_MISO ECSPI5_MOSI ECSPI5_SCLK ECSPI5_SS0 8 6 7 5 DNP DNP DNP DNP SI DNP SCK VCC HOLD R343R344 0 R345 0 R346 0 0 WP VSS CS SO U8 25LC320A-I/SN 3 4 1 2 DNP R341 47K GND QSPI1A_SS1_B QSPI1B_DQS QSPI1A_DQS QSPI1B_SS1_B ECSPI5_SS0 ECSPI5_MISO SPI EEPROM FOOTPRINT <6,14> <6,14> <6,14> <6,14> These four signals are routed to CAN transceivers also. For SPI EEPROM test, the 0-ohm jumpers on CAN transceiver side are required to be removed. 0 MEM_3V1 R336 QSPI_VCC QSPI2B_DATA1 <6> QSPI2A_DATA1 <6> C54 4.7uF 10V 0603_CC C52 4.7uF 10V 0603_CC GND GND 25V C51 0.1uF 25V 0402_cc C53 0.1uF 0402_cc 2 2 DQ1 DQ1

N25Q256A13EF840 N25Q256A13EF840

VCC VSS VCC VSS

8 4 8 4

EP EP

9 9 GND GND DQ0 C S W/VPP/DQ2 HOLD/DQ3 DQ0 C S W/VPP/DQ2 HOLD/DQ3 U7 U9 1 3 3 5 6 5 6 7 1 7 R348 10K R347 10K TP126 GND TP122 TP128 TP127 TP123 2 x 256 Mbit QSPI FLASH QSPI2B_DATA0 QSPI2A_SCLK QSPI2A_DATA0 QSPI2B_SS0_B QSPI2B_DATA2 QSPI2B_DATA3 QSPI2A_SS0_B QSPI2A_DATA2 QSPI2A_DATA3 QSPI2B_SCLK <6> <6> <6> <6> <6> <6> <6> <6> <6> <6>

Figure 11. Schematic part 9

Powering an i.MX 6SX-based system using the PF3000 PMIC, Rev. 1.0 NXP Semiconductors 14 Schematics VDD_USB_CAP DNP R477 0 R478 DNP 0 CGND S2 S4 IMX_OTG_VBUS

C458 DNP 4.7uF 10V CC0603_OV 5

TVS5 ESD5B5.0ST1G

4 2 1 GND 3 GND 5

Ra Q6 3 R56 DNP

NTA4151PT1G 2 OUT DNP

270K 1% DNP R471 1 1 5V D- D+ ID G

Micro USB-AB Receptacle J7 5 AB USB MICRO 3 2 1 IN EN GND ADJ MIC5205 GND U46

S1 S3 2 2 4 1 3 TVS2 ESD5B5.0ST1G

50V 0402_CC DNP C456 470PF 2 1 GND D28 USB_OTG1_VBUS GND DNP R472 100K 1% DNP C388 1000pF 50V 0402_CC ESD7C5.0DT5G USB_5V_OTG USBOTG1_DN USBOTG1_DP USBOTG1_ID DNP R480 0 GND 2 3 Rb DNP Q7 2N7002 L4 10K R60 100K

90OHM

3 2 C57 4.7uF 16V 0603_CC R479 GND 1 4 GND 1 0 GND DNP DNP C457 1uF 16V 0402_cc L2 470 Ohm IND0603_CC 10K R475 10K R59 R476 NVCC_3V1 USB_OTG1_PWR 6 USB_OTG1_VBUS USB_OTG1_DN USB_OTG1_DP USB_OTG1_ID Need to use MIC5225 for ceramic output cap. Max output current from MIC5225 is 150mA Vo = 1.24V x (1+Ra/Rb) USB Boot/Host/Device Port <6> <6> <6> This block is reserved for USB OTG certification test. USB_OTG1_OC <6> USB_OTG2_OC <6> CGND S2 R62 DNP 47K USB_HOST_VBUS USB_TYPE_A_FEMALE DNP R61 47K VD-D+G HSIC_DATA <6> USB_OTG1_VBUS J6 S1 A4 A3 A1 A2 NVCC_3V1

D27 ESD7C5.0DT5G

1 3 2 8 5 3 GND

FLGA FLGB OUTB OUTA 2 1

TVS1 ESD5B5.0ST1G 2 3

2 1 GND USBHOST_DN USBHOST_DP IN GND ENA ENB U12 MIC2026-1YM DNP J9 6 4 7 1 2 3 128-0711-20 GND L3 90OHM 1 USB_5V_HOST 4 R69 10K C56 4.7uF 16V 0603_CC R68 10K USBOTG2_PWR USBOTG1_PWR DNP C55 150 UF 0 0 + GND HSIC_STROBE <6> 0 0 R57 R58 R65 L1 470 Ohm IND0603_CC R63 C59 47uF 10V 0805_CC

2 3 GND USB Host Port USB_OTG1_PWR USB_OTG2_PWR USB_HOST_VBUS DNP J8 USB_HOST_DP USB_HOST_DN <6> <6> 128-0711-20 C58 0.1uF 25V 0402_cc GND USB 5V Control PSU_5V0 <6,16> <6,16>

Figure 12. Schematic part 10

Powering an i.MX 6SX-based system using the PF3000 PMIC, Rev. 1.0 NXP Semiconductors 15 Schematics DNP R71 10K GND HPOUTR DNP R70 10K GND HPOUTL HeadPhone SPKOUTLN SPKOUTRN SPKOUTLP SPKOUTRP Audio Jack J10 4 3 2 1 1 5 6 4

Speaker Out CON1 HDR 1X4 DNP

2 1 GND TVS4 0 2 2 ESD5B5.0ST1G Layout note: C66 & C67 close to HP Jack, for EMI purpose 1 1 CODEC_INT <7> R76 DNP C67 50V 0402_CC L5 100 OHM@100MHZ L6 100 OHM@100MHZ 1000pF TP112 HP_DET_B GND R84 10K 0402_CC <7> HPOUTR HPOUTL DNP C66 50V 0402_CC GND C76 2.2UF 6.3V 0402_CC 1000pF GND Layout note: Zobel Networks(C64,C65,R77,R78) close to WM8962 C78 4.7uF 6.3V 0402_CC GND C74 should be as close to the WM8962 possible. layout note: C75 2.2UF 6.3V 0402_CC C65 0.1uF R78 20 25V 0402_CC

GND GND HPOUTR_ZOBEL GND 2.2UF C74 6.3V 0402_CC C77 1.0UF 10V TP5 0402_CC C64 0.1uF 0402_CC TP4 R77 20 25V

MICBIAS HPOUTL_ZOBEL CPCA SPKOUTLP SPKOUTRP CPCB CPVOUTP SPKOUTLN SPKOUTRN CPVOUTN R248 0 GND GND GND E4 B1 F4 B3 F3 B5 A1 B2 D7 C1 A5 G5 C3 C5 A7 G6 E3 B4 A4 B7 A6 C7 B6 G1 CPCA CPCB AGND DGND GPIO5 VMIDC CPGND MICBIAS PLLGND HPOUTL HPOUTR CLKOUT5 CS/GPIO6 SPKGND1 SPKGND2 HPOUTFB CPVOUTP CPVOUTN SPKOUTLP SPKOUTLN SPKOUTRP SPKOUTRN CLKOUT2/GPIO2 CLKOUT3/GPIO3 MICVDD DCVDD AVDD CPVDD PLLVDD IN1L IN3L DBVDD IN2L IN2R IN3R SDA CIFMODE DACDAT MCLK/XTI XTO SPKVDD1 SPKVDD2 IN1R IN4L IN4R SCLK BCLK LRCLK ADCDAT U13 WM8962BECSN/R F6 F5 F2 F7 F1 E5 E2 A2 E6 E7 E1 A3 D6 C6 D5 D1 C2 D4 D3 D2 C4 G2 G3 G7 G4 Audio CODEC GND C62 C68 0.1uF 0402_CC 0.1uF 25V 0402_CC 25V IN3R C71 4.7uF 6.3V 0402_CC GND GND TP111 SPKVDD GND NVCC_1V8 GND C61 0603_CC 4.7uF 16V 10V C72 TP110 GND GND C70 4.7uF 1.0UF 6.3V 0402_CC 0 CODEC_1V8 0402_CC 6.3V TP109 C63 4.7uF MICVDD 0402_CC C73 1.0UF 10V 0402_CC C60 TP108 4.7uF 16V 0603_CC Layout note: Widen the trace SPKVDD Max ~0.6A C69 4.7uF 6.3V 0402_CC R81 TP107 R80 2.2K MICBIAS 1 2 R349 0 0 + - DNP POM-2244P-C3310-2-R P1 PSU_5V0 R350 0 R98 VGEN3_2V8 AUD_RXD AUD_SDA AUD_TXD AUD_MCLK AUD_TXC AUD_TXFS AUD_SCL or WM-63PR or CMC-2242PBL-A <7> <7> <7> <7> <7> <22> <22> SW4_1V8 VGEN4_1V8

Figure 13. Schematic part 11

Powering an i.MX 6SX-based system using the PF3000 PMIC, Rev. 1.0 NXP Semiconductors 16 Schematics GND S1 S2 J12 30 CON 2 6 7 8 3 4 5 9 1 10 11 12 13 14 15 16 17 18 19 21 22 23 24 25 26 27 28 29 30 20 LVDS_BL_5V0 GND 3 C319 0.1uF 25V 0402_cc IRLML6401 R436 10K Q15 MMBT3904T TP78

LVDS_CLKIN_P GND 1 3 2 LVDS_TX2_N LVDS_TX2_P LVDS_CLKIN_N GND Q14 2 LVDS_TX0_N LVDS_TX0_P LVDS_TX1_N LVDS_TX1_P LVDS_TX3_N LVDS_TX3_P 1 LVDS_VDD C79 4.7uF 10V CC0603_OV C349 1uF 16V 0402_cc C320 0.1uF 25V 0402_cc R437 100K R435 100K L38 470 Ohm IND0603_CC 2 3 2 3 2 3 2 3 2 3 90OHM 90OHM 90OHM 90OHM 90OHM LVDS_VLED PSU_5V0 DNP C80 4.7uF 16V 0603_CC GND 4 1 1 1 4 4 1 4 4 1 BL_BRIGHTNESS L7 L35 L8 L10 L9 LVDS PERI_3V3 L39 470 Ohm IND0603_CC PERI_PWR_EN R353 330 R185 0 R182 10K <4,6> DNP R337 10K GND Layout: Route 100 ohm DIFF NVCC_3V1 LVDS_BL_5V0 PWM4_OUT CABC_EN LVDS_DATA3_N LVDS_DATA0_N LVDS_DATA1_N LVDS_DATA1_P LVDS_DATA3_P LVDS_DATA0_P LVDS_DATA2_N LVDS_DATA2_P LVDS_CLK_N LVDS_CLK_P CAP_TCH_INT_B <6> <6> LVDS_I2C_SCL_EDID LVDS_I2C_SCL_TCH LVDS_I2C_SDA_EDID LVDS_I2C_SDA_TCH <7> <7> <7> <7> <7> <7> <7> <7> <7> <7> <6> <22> <22> <22> <22> The camera connector (J13) and the LCD Expansion connector (J11) share the same signals and CANNOT be used at the same time. One of these two peripherals MUST BE REMOVED when a developer wishes to use the other. VADC_IN2 <6> VADC_IN1 <6> VADC_IN0 <6> VGEN3_2V8 VGEN2_1V5 0402_cc 0402_cc 0402_cc 2 L13 C35116V 0.047UF C35216V 0.047UF C353 0.047UF16V 0603_CC 120OHM 1 PWM3_OUT <6> R115 0 R242 75 0.1uF 25V 0402_cc C83 GND SD4_DATA4 <6,9> SD4_DATA5 <6,9> GND PERI_3V3 10V R241 75 R243 75 C85 1.0UF GND GND 0402_cc C82 4.7uF 6.3V 0402_CC LCD1_DATA8 <7,13,21> LCD1_DATA0 <7,21> LCD1_DATA9 <7,13,21> LCD1_DATA16 <7,13,21> LCD1_DATA1LCD1_DATA2 <7,21> <7,21> LCD1_DATA17LCD1_DATA18 <7,13,21> <7,21> LCD1_DATA10 <7,13,21> LCD1_DATA14LCD1_DATA15 <7,13,21> <7,13,21> LCD1_DATA21LCD1_DATA22 <7,21> <7,21> LCD1_HSYNCLCD1_ENABLE <7> <7> LCD1_DATA3LCD1_DATA5 <7,21> LCD1_DATA6LCD1_DATA7 <7,13,21> <7,13,21> <7,13,21> LCD1_DATA11LCD1_DATA12LCD1_DATA13 <7,13,21> <7,13,21> <7,13,21> LCD1_DATA19LCD1_DATA20 <7,21> <7,21> LCD1_DATA23LCD1_VSYNC <7,21> <7,13> LCD1_DATA4 <7,13,21> GND R113 0 25V 0402_cc 25V C81 0.1uF C84 0.1uF 0402_cc AF_GND R88 0 R89 0 51EXP_UART2_TX HDMI_SPDIF_OUT 51EXP_UART2_RX GND GND LCD1_DATA7 <7,13,21> PSU_5V0 VGEN3_2V8 R110 0 10K 0402_CC 2 Note: Remove R88 and R89 when populate eMMC (U4) L12 0603_CC 120OHM 1 VIDEO_G_Y VIDEO_B_CB VIDEO_R_CR R114 SPDIF_OUT LCD_PWM 51EXP_CSI_VSYNC 51EXP_CSI_HSYNC 51EXP_CSI_PIXCLK 51EXP_CSI_MCLK 51EXP_CSI_D9 51EXP_CSI_D8 51EXP_CSI_D7 51EXP_CSI_D6 51EXP_GPIO 51EXP_CAM_PWDN 51EXP_RESET AF_GND 51EXP_CSI_D5 51EXP_CSI_D4 51EXP_CSI_D3 51EXP_CSI_D2 51EXP_CSI_D1 51EXP_CSI_D0 TP6 GND AF_VCC COMS_AVDD AF_PD GND DOVDD CMOS_MCLK CMOS_DVDD GND 16 20 68 78 116 SH2 2 4 10 12 14 24 26 36 38 44 46 48 50 54 56 58 60 62 66 72 74 76 84 86 92 94 96 102 104 106 108 112 114 120 SH8 6 8 18 22 28 30 32 34 40 42 52 SH4 SH6 64 70 80 82 88 90 98 100 110 118 6 8 10 20 28 38 46 42 2 4 12 14 16 18 22 24 26 30 32 34 40 44 36 J11 QSH-060-01-L-D-A 1 3 7 9 5 J13 11 13 15 17 19 21 23 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 73 75 77 79 81 83 85 87 89 91 93 95 97 99 25 71 103 105 107 113 115 117 119 101 109 111 SH1 SH7 SH3 SH5 GND 9 1 5 3 7 41 11 15 19 21 23 31 43 45 17 25 27 29 33 35 37 39 13 CONN PLUG 40 CON_BBC_40P_0P4_SM_MIRROR NVCC_1V8 GND 51EXP_SPDIF_OUT C360 0.1uF 25V 0402_cc MEM_3V1 MEM_3V1 PSU_5V0 SYS_3V8 GND MEM_3V1 LCD_PWR_EN LCD Expansion Port CMOS_AGND 51EXP_CSI_SDA 51EXP_CSI_SCL R66 0 CMOS_AGND CSI_RST_B CSI_PIXCLK CSI_VSYNC CSI_HSYNC CSI_PWDN CSI_D9 CSI_D8 CSI_D7 CSI_D6 CSI_D5 CSI_D4 CSI_D3 CSI_D2 CSI_D1 CSI_D0 0 C359 0.1uF 25V 0402_cc 2 SPDIF_OUT GND L11 Use Omnivision OV5640/5642 5M Pixel Sensor with this connector (not included) 0603_CC 120OHM 1 R64 PSU_5V0 LCD1_DATA6 LCD1_DATA9 LCD1_DATA10 LCD1_DATA14 LCD1_DATA4 LCD1_DATA8 LCD1_DATA11 LCD1_DATA12 LCD1_DATA13 LCD1_DATA15 LCD1_DATA16 LCD1_DATA17 LCD1_DATA5 Camera Expansion Connector GND DNP R247 10K 0402_CC LCD_CSI_SDA LCD_CSI_SCL HDMI_INT LCD_CSI_SDA LCD_CSI_SCL LCD1_CLK LCD_CSI_SDA LCD_CSI_SCL Note: Pin#33 is NC on MCIMX28LCD VGEN3_2V8 <6> <7,13,21> <7,13,21> <7,13,21> <7,13,21> <7,13,21> <7,13,21> <7,13,21> <7,13,21> <7,13,21> <7,13,21> <7,13,21> <7,13,21> <7,13,21> <7> <13,22> <13,22> <13,22> <13,22> <13,22> <13,22> LCD1_RESET LCD1_VSYNC LCD1_RESET <7,13> <7,13> <7,13>

Figure 14. Schematic part 12

Powering an i.MX 6SX-based system using the PF3000 PMIC, Rev. 1.0 NXP Semiconductors 17 Schematics CAN2_TX CAN2_RX CAN1_TX CAN1_RX R355R356 0 R357 0 R358 0 0 QSPI1A_DQS QSPI1B_DQS QSPI1B_SS1_B QSPI1A_SS1_B P2A P2B

<6,10> <6,10> These four signals are routed to SPI EEPROM also. For CAN test, the 0-ohm jumpers on SPI EEPROM side are required to be removed. DDB9_M DDB9_M

<6,10> <6,10>

10 22 20 21 CGND CGND 4 3 2 1 5 9 8 7 6 15 14 18 13 17 12 16 11 19 UPPER PORT LOWER PORT GND GND C96 56PF 50V 0402_cc C91 56PF 50V 0402_cc GND GND C90 56PF 50V 0402_cc C95 56PF 50V 0402_cc DNP C97 0.01UF 50V 0402_CC DNP C89 0.01UF 50V 0402_CC R126 62 CAN R120 62 R121 62 R125 62

L40 100 uH L41 100 uH

4 2 4 2

DNP DNP

3 1 3 1 R450 0 R447 0 R448 0 R451 0 NVCC_3V1 CAN2H CAN2L CAN1H CAN1L C86 1uF 16V 0402_cc C92 1uF 16V 0402_cc R205 0 6 7 6 7 GND GND

MC34901WEF MC34901WEF

VIO VIO

CANL CANL 5 CANH 5 CANH

VDD GND VDD GND

CAN_VIO_3V1 CAN_VIO_3V1 3 2 3 2 GND GND U15 U17 RXD TXD RXD STB TXD STB 4 1 4 8 1 8 C87 0.1uF 25V 0402_cc C93 0.1uF 25V 0402_cc GND GND PSU_5V0 PSU_5V0 C347 1uF 16V 0402_cc C348 1uF 16V 0402_cc CAN1_TX CAN1_RX CAN2_TX CAN2_RX GND GND CAN1_2_STBY R188 10K CAN_VIO_3V1 CAN1_2_STBY <6>

Figure 15. Schematic part 13

Powering an i.MX 6SX-based system using the PF3000 PMIC, Rev. 1.0 NXP Semiconductors 18 Schematics

hi ch

CHASSIS_GND2

CHASSIS_GND1 S1 CGND small a is GND CGND isolated extend pl ane w should under RJ 45 connect or oe Port Lower DNP R153 10K 0402_CC RJ 5 TRP3- RJ 8 TRP4- RJ 1 TRP1+ RJ 2 TRP1- RJ 6 TRP2- RJ 4 TRP3+ RJ 7 TRP4+ RJ 3 TRP2+ GREEN LED2_YA LED2_YC PHY1_2V5 GND DNP R152 10K 0402_CC TRD1- TRCT1 TRD1+ TRD2- TRCT2 TRD2+ TRD3- TRCT3 TRD3+ TRD4- TRCT4 TRD4+ GND1 LED1_C LED1_A LED2_GC LED2_GA P3A RJ45 13X2PORTS C 21 14 15 16 22 23 24 17 18 19 25 26 20 27 28 29 30 GND GND D11 LED_ORANGE 10K DNP 10K 10K 10K 10K 10K 10K 10K A GND R145 R147 R148 R149 R151 R155 R156 R157 DNP R143 10K 0402_CC DNP C122 0.1uF 25V 0402_cc R362R363 270 270 R133 270 ENET1_VDDIO_REG R142 10K 0402_CC DNP R168 10K 0402_CC PHY2_2V5 DNP C121 0.1uF 25V 0402_cc DNP R167 10K 0402_CC RGMII1_LED_ACT RGMII1_LED_10_100 RGMII1_LED_1000 RGMII1_RXD0 RGMII1_RXD1 RGMII1_RXD2 RGMII1_RXD3 RGMII1_RXCLK RGMII1_RXDV RGMII1_LED_1000 RGMII1_LED_ACT GND DNP C120 0.1uF 25V 0402_cc Pl indi t Gbi cates speed. near ace LED D11 LED RJ - 45 connectOrange or . 10K 10K DNP 10K 10K 10K 10K 10K 10K GND TP7 Pin 5 mode: 0: INT ; 1:GPIO Select the core voltage level: 0:1.1V, 1:1.2V R160 R161 R162 R164 R166 R169 R170 R171 R159 10K 0402_CC PHYADDRESS0 PHYADDRESS1 MODE[1] MODE[3] MODE[2] MODE[0] SEL_GPIO_INT ANA_MOD DNP C129 470PF differential pairs differential C112 0.1uF 25V 0402_cc GND GND ENET2_VDDIO_REG DNP R158 10K 0402_CC 2 L16 120OHM C111 0.1uF 25V 0402_cc DNP C128 470PF 1 GND PHY1_DVDDL EMI Filter Reserved 470pF are for LED C106 0.1uF 25V 0402_cc C110 0.1uF 25V 0402_cc RGMII2_RXD0 RGMII2_RXD1 RGMII2_RXD2 RGMII2_RXD3 RGMII2_RXCLK RGMII2_RXDV RGMII2_LED_1000 RGMII2_LED_ACT DNP C127 470PF GND GND PHY1 Power-on Strapping Pins Strapping Power-on PHY1 C109 0.1uF 25V 0402_cc Layout : 100 ohm 1.1V C105 10uF 10v 0603_CC PHY1_AVDDL GND GND RGMII1_TRXP0 RGMII1_TRXN0 RGMII1_TRXP1 RGMII1_TRXN1 RGMII1_TRXP2 RGMII1_TRXN2 RGMII1_TRXP3 RGMII1_TRXN3 To Processor To I / suppl O y is required. I/O Popul at i e R368 RGMII f 2. 5V 2 RGMII1_LED_10_100 RGMII1_LED_1000 RGMII1_LED_ACT Pin 5 mode: 0: INT ; 1:GPIO Select the core voltage level: 0:1.1V, 1:1.2V L15 4.7UH PHYADDRESS0 PHYADDRESS1 MODE[1] MODE[3] MODE[2] MODE[0] SEL_GPIO_INT ANA_MOD 24 26 11 14 17 20 12 15 18 21 47 23 8 44 13 19 MODE[3:0] 1 (Default assemble: 0000) assemble: RGMII (Default 0000 10Base-T/100Base-T/1000Base-T, NVCC_RGMII1 GND TRXP0 TRXP1 TRXP2 TRXP3 TRXN0 TRXN1 TRXN2 TRXN3 DVDDL AVDDL1 AVDDL2 AVDDL3 AVDDL4

LED_ACT

DNP

PHY1_LX LX C102 1.0UF 10V 0402_cc 3 LED_LINK1000

LED_LINK10_100

L36 470 Ohm IND0603_CC VDDH_REG

R368 0 PHY1_2V5 GND

VDDIO_REG GND 29

PHY2 Power-on Strapping Pins Strapping Power-on PHY2

AVDD33

C99 0.1uF 25V 0402_cc VDD33 4 GND C101 0.1uF 25V 0402_cc U18 GTX_CLK TXD0 TXD1 TXD2 TXD3 TX_EN RX_CLK RXD0 RXD1 RXD2 RXD3 RX_DV SIP SIN SOP SON SD RST WOL_INT INT PPS CLK_25M MDC MDIO XTLO XTLI RBIAS GND AR8031 2 5 1 6 7 9 35 36 37 38 39 34 33 31 30 28 27 32 46 45 43 42 41 40 22 25 48 GND C104 0.1uF 25V 0402_cc ENET1_AVDD33 GND GND ENET1_VDDIO_REG C98 1.0UF 10V 0402_cc MODE[3:0] (Default assemble: 0000) assemble: RGMII (Default 0000 10Base-T/100Base-T/1000Base-T, C100 1.0UF 10V 0402_cc R136 2.37K 1% PHY1_RBIAS TP8

GND

C103 10uF 10v 0603_CC CHASSIS_GND4

DNP CHASSIS_GND3 R130 4.7K DNP C131 33PF 50VDC 0402_cc S3 PHY1_XTLO PHY1_XTLI L14 470 Ohm IND0603_CC GND TP137 GND CGND Uppe r P or t RJ 5 TRP3- RJ 8 TRP4- PHY1_DVDDL RJ 1 TRP1+ RJ 2 TRP1- RJ 6 TRP2- RJ 4 TRP3+ RJ 7 TRP4+ RJ 3 TRP2+ 4 3 GREEN TP136 R251R134 0 0 LED2_YA LED2_YC DNP ENET_3V3 GND TRD1- TRCT1 TRD1+ TRD2- TRCT2 TRD2+ TRD3- TRCT3 TRD3+ TRD4- TRCT4 TRD4+ GND2 LED3_C LED3_A LED4_GC LED4_GA P3B RJ45 13X2PORTS C X1 25MHz 7 6 5 4 3 2 9 8 1 13 12 11 10 31 32 33 34 1 2 GND D12 LED_ORANGE A DNP C130 33PF 50VDC 0402_cc DNP R129 10K 0402_CC GND GND RGMII1_TXCLK RGMII1_TXD0 RGMII1_TXD1 RGMII1_TXD2 RGMII1_TXD3 RGMII1_TXEN RGMII1_RXCLK RGMII1_RXD0 RGMII1_RXD1 RGMII1_RXD2 RGMII1_RXD3 RGMII1_RXDV ENET_3V3 <7> <7> <7> <7> <7> <7> <7> <7> <7> <7> <7> <7> ENET_MDC 270 270 ENET1_REF_CLK_IN <7,15> ENET1_WOL_INT <7> DNP C134 0.1uF 25V 0402_cc R144 270 R127 0 R163 R165 DNP R128 10K 0402_CC R150 1.5K GND TP103 ENET_3V3 DNP C133 0.1uF 25V 0402_cc R131 10K 0402_CC ENET_PHY_CLK1 RGMII2_LED_ACT RGMII2_LED_10_100 RGMII2_LED_1000 DNP C132 0.1uF 25V 0402_cc ENET_3V3 Pl indi t Gbi cates speed. near ace LED D12 LED RJ - 45 connectOrange or . GND ENET_MDIO TP9 ENET_INT <7,15> ENET_RST_B <7> C137 470PF DNP <7> differential pairs differential C126 0.1uF 25V 0402_cc GND GND 2 L19 120OHM C125 0.1uF 25V 0402_cc C136 470PF DNP 1 GND PHY2_DVDDL EMI Filter Reserved 470pF are for LED C119 0.1uF 25V 0402_cc C124 0.1uF 25V 0402_cc C135 470PF DNP GND GND C123 0.1uF 25V 0402_cc Layout : 100 ohm PHY2_AVDDL 1.1V C118 10uF 10v 0603_CC GND GND RGMII2_TRXP0 RGMII2_TRXN0 RGMII2_TRXP1 RGMII2_TRXN1 RGMII2_TRXP2 RGMII2_TRXN2 RGMII2_TRXP3 RGMII2_TRXN3 RGMII I/O is required. I/O Popul at i e R369 RGMII f 2. 5V To Processor To I / suppl O y 2 RGMII2_LED_10_100 RGMII2_LED_1000 RGMII2_LED_ACT L18 4.7UH 24 26 11 14 17 20 12 15 18 21 47 23 8 44 13 19 1 C285 0.1uF 25V 0402_cc ENET_PHY_CLK1 ENET_PHY_CLK2 NVCC_RGMII2 GND TRXP0 TRXP1 TRXP2 TRXP3 TRXN0 TRXN1 TRXN2 TRXN3 DVDDL GND AVDDL1 AVDDL2 AVDDL3 AVDDL4

LED_ACT

DNP ENET_3V3

PHY2_LX LX VGEN1_1V2 GND C115 1.0UF 10V 0402_cc 3 LED_LINK1000

LED_LINK10_100

L37 470 Ohm IND0603_CC VDDH_REG 7 6 10 5 8

R369 0 PHY2_2V5 GND 49

B1 B2 VDDIO_REG

GND

1 GND 29 VCCB

IRLML6401

2 AVDD33

NLSV2T244MUTAG U20 16 VCCA A1 A2 OE

DNP C321 0.1uF 25V 0402_cc R361 1K

C108 0.1uF 25V 0402_cc VDD33 4 1 2 3 4 GND C114 0.1uF 25V 0402_cc U19 GTX_CLK TXD0 TXD1 TXD2 TXD3 TX_EN RX_CLK RXD0 RXD1 RXD2 RXD3 RX_DV SIP SIN SOP SON SD RST WOL_INT INT PPS CLK_25M MDC MDIO XTLO XTLI RBIAS R360 10K 0402_CC GND AR8031 2 5 1 6 7 9 35 36 37 38 39 34 33 31 30 28 27 32 46 45 43 42 41 40 22 25 48 GND C117 0.1uF 25V 0402_cc ENET2_AVDD33 C286 0.1uF 25V 0402_cc GND GND PERI_3V3 GND ENET2_VDDIO_REG C107 1.0UF 10V 0402_cc PERI_3V3 ENET_PWR_EN_B PHY2_RBIAS C113 1.0UF 10V 0402_cc R154 2.37K 1% TP10 GND ENET_PWR_EN_B C116 10uF 10v 0603_CC DNP R139 4.7K DNP C139 33PF 50VDC 0402_cc PHY2_XTLO PHY2_XTLI L17 470 Ohm IND0603_CC GND GND <7> TP133 PHY2_DVDDL 4 3 ENET_REF_CLK_25M R252R146 0 0 ENET_3V3 TP132 DNP <7> ENET_RST_B X2 25MHz 1 2 ENET2_REF_CLK_IN DNP C138 33PF 50VDC 0402_cc DNP R138 10K 0402_CC GND RGMII2_TXCLK RGMII2_TXD0 RGMII2_TXD1 RGMII2_TXD2 RGMII2_TXD3 RGMII2_TXEN RGMII2_RXCLK RGMII2_RXD0 RGMII2_RXD1 RGMII2_RXD2 RGMII2_RXD3 RGMII2_RXDV ENET_3V3 TP102 <7> <7> <7> <7> <7> <7> <7> <7> <7> <7> <7> <7> ENET2_WOL_INT R141 0 TP104 ENET_INT ENET_PHY_CLK2 ENET_MDC ENET_MDIO <7,15> <7,15>

Figure 16. Schematic part 14

Powering an i.MX 6SX-based system using the PF3000 PMIC, Rev. 1.0 NXP Semiconductors 19 Schematics TP90 TP91 GND

MPCIE_1V5

R176 470 D15 LED_YELLOW

A C LD_WPAN_B SH9

SOLDER SHORT

D14 LED_GREEN R175 470

A C LD_WLAN_B MPCIE_3V3 VGEN2_1V5

LED_ORANGE

D13 R174 470

A C LD_WWAN_B PCIE_UIM_DATA PCIE_UIM_VPP GND Max output current from VGEN2_1V5 is 250mA 6 5 4 I/O VPP GND VCC CLK RESET J14 CARD 6 SIM CON PCIE_I2C_SCLPCIE_I2C_SDAUSB_HOST_DN <22> <22> <6,11> USB_HOST_DP <6,11> 1 3 2 PCIE_DIS_B <6> PCIE_RST_B <7> PCIE_UIM_CLK PCIE_UIM_RST PCIE_UIM_PWR DNP DNP J22 DNP HDR 1X2 HDR 1 2 R428 10K R420 10K R177 0 R178 0 GND GND MPCIE_3V3 C146 100uF 10V 1206_CC 1 4 L20 90OHM MPCIE_3V3 2 3 C148 0.1uF 25V 0402_cc GND MPCIE_1V5 SH8 C147 4.7uF 10V CC0603_OV PCIE_UIM_PWR PCIE_UIM_DATA PCIE_UIM_CLK PCIE_UIM_RST PCIE_UIM_VPP PCIE_USB_DM PCIE_USB_DP LED_WWAN_B LED_WLAN_B LED_WPAN_B Vo = 0.6V x (1+Ra/Rb) SOLDER SHORT Max output current from NCP1593A is 3A C154 4.7uF 10V 0603_CC GND Rb Ra R184 220K 1% R187 47K 1% GND GND C337 0.1uF 25V 0402_cc 2 24 22 20 36 2 6 28 48 52 10 46 40 50 4 30 12 8 44 42 16 32 38 34 18 26 14 GND L21 4.7uH C153 47uF 10V 0805_CC GND7 GND8 GND9 3.3V_1 1.5V_1 1.5V_2 1.5V_3 3.3V_2 GND11 GND12 GND10 MPCIE_3V3 C145 100uF 10V 1206_CC USB_D- PERST# 1 USB_D+ +3.3Vaux UIM_CLK UIM_VPP SMB_CLK UIM_PWR UIM_DATA SMB_DATA UIM_RESET GND GND LED_WLAN# LED_WPAN# W_DISABLE# LED_WWAN# C144 100uF 10V 1206_CC 6 3 2 Place C155 close to VCCA pin (#8) C155 0.1uF 25V 0402_cc U30 GND FB CON 2X26 MINI PCI EXPRESS 2X26 MINI CON NCP1593AMNTWG LX1 LX2

Reserved2 CLKREQ# PERp0 Reserved3 Reserved4 Reserved10 WAKE# Reserved1 GND1 REFCLK- GND2 Reserved/UIM_C8 Reserved/UIM_C4 GND3 PERn0 GND4 GND5 PETn0 PETp0 GND6 Reserved5 Reserved6 Reserved7 Reserved8 Reserved9 REFCLK+

J15

VCCP2

10 5 7 1 3 9

VCCP1 11 15 17 19 23 27 29 31 33 41 43 45 47 49 13 25 37 39 51 21 35

C143 0.1uF 25V 0402_cc 9

EPAD

11 VCCA

PSU_5V0 GND GND 8 TP28 TP26 TP29 TP30 TP31 TP33 TP34 TP27 TP32 EN PG SS NC_1 C142 4.7uF 10V CC0603_OV TP12 TP13 TP14 TP18 TP19 TP11 TP15 TP16 TP17 5 4 7 1 GND GND GND C322 0.1uF 25V 0402_cc DNP C323 1000pF 50V 0402_cc DNP C141 100uF 10V 1206_CC GND TP62 GND PCIE_CREFCLKM PCIE_CREFCLKP R180 56 Step-down DCDC for mPCIe +3.3V C140 DNP 100uF 10V 1206_CC R186 10K GND 56 GND R179 R443 470 GND Mini-PCIE R442 470 MPCIE_3V3 TP142 TP143 PCIE_PWR_EN <7> PCIE_CRXM PCIE_CRXP PCIE_CTXM PCIE_CTXP 25V 25V 25V 25V 0.1uF 0.1uF 0.1uF 0.1uF 0402_cc 0402_cc C149 C150 R172R173 0 0 0402_cc 0402_cc C152 C151 TP80 PCIE_CREFCLKM PCIE_CREFCLKP CLK1_N CLK1_P TP79 VGEN4_1V8 2 DNP L43 25V DNP 25V DNP 120OHM 1 0.1uF 0.1uF DNP C371 1.0UF 10V 0402_CC DNP DNP GND CLK1_N CLK1_P 0402_cc 0402_cc PCIE_WAKE_B PCIE_RX_N PCIE_RX_P PCIE_TX_N PCIE_TX_P R454R455 0 0 TP141 C368 C377 <6> <6> DNP 25V 0402_CC C370 0.01uF <6> <7> <7> <7> <7> 13 17 4 14 18

9FGV0241AKLF

DIF0 EPAD DIF0 DIF1 DIF1

DNP 25V 0402_CC C379 0.01uF 25

VDDXTAL1.8

GNDXTAL

VDDA1.8

SADR/REF1.8 GNDA

VDDDIG1.8

GNDREF

VDD1.8_2

VDD1.8_1 GNDDIG

11 6

GND_2

GND_1 10 C375 GND GND DNP 0.01uF 25V 0402_CC SCLK_3.3 SDATA_3.3 X1_25 OE1 X2 CKPWRGD_PD OE0 SS_EN_TRI DNP 25V 0402_CC VGEN4_1V8 DNP U40 C378 0.01uF 8 9 1 2 23 19 22 12 C376 1.0UF 10V 0402_CC DNP C372 0.01uF 25V 0402_CC GND Layout Note: i) Place termination resistors, R179, R180, R442 & R443, as close to the mPCIe connector possible. ii) Place C149, C150, C151 and C152 close to mPCIe connector. iii) Place R454, R455 close to C149 and C150. iv) Place C368, C377 close to C149 and C150. DNP DNP DNP DNP 10V 0402_CC R456 0 R458 0 C373 1.0UF R457 0 PCIE_PWR_EN GND 2 DNP C367 18pF 50V CC0402_25 DNP L42 120OHM 1 3 2 DNP GND1 GND 25MHz GND2 Y4 Layout: Route 100 ohm DIFF for CLK1_P/N Layout: Route 85 ohm DIFF for PCIE_TX/RX VGEN4_1V8 4 1 PCIE_CLK_GEN_SCL PCIE_CLK_GEN_SDA DNP C366 18pF 50V <22> <22> CC0402_25 Note: All components in this block are needed to be populated for PCIe GEN2 clock jitter test. When U40 is populated - i) Remove R442, R443, R179, R180, C149, C150, and use U40 to output PCIe refclk i.MX6SX and mPCIe connector. ii) Mount R459-R462 on i.MX6SX side for termination.

Figure 17. Schematic part 15

Powering an i.MX 6SX-based system using the PF3000 PMIC, Rev. 1.0 NXP Semiconductors 20 Schematics R325 0

S2 S4 5

GND 4

JTAG_PWR

2 4 6 8 16 20 2 10 12 14 18 1 5V D- D+ ID G DEBUG_SHL_GND J16 5 AB USB MICRO J17 TST-110-05-T-D-RA 5 7 9 3 1 20 20 11 13 15 19 17 S1 S3 DEBUG_USB_5V R196 R195 R216 10K 0402_CC 2 JTAG_RTCK JTAG_DE JTAG_VREF JTAG_DACK R209 100 L22 0603_CC 120OHM R215 10K 0402_CC 1 10K 0402_CC C161 4.7uF R208 16V 0603_CC 10K 0402_CC R214 DEBUG_USB_DM DEBUG_USB_DP GND DEBUG_5V GND R207 10K 0402_CC Layout note: 90ohm diff pairs R206 10K 0402_CC R194 1.5K R204 10K 0402_CC 0402_CC R203 10K R199 10K 0402_CC DEBUG_5V R444 0 NVCC_3V1 3 R218 DNP R217 10K 1K 6 MHZ POR_B

GND 2 GND NVCC_3V1 X3 25V C160 0.1uF 0402_cc 1 JTAG_TDI JTAG_TCK JTAG_TRST_B JTAG_TMS JTAG_TDO JTAG_nSRST GND R326 1.0M 25V 0402_cc C158 0.1uF GND <4,6,9,20,21> <6> <6> <6> <6> <6> GND 44 6 47 5 2 4 48 43 1 8 7 JTAG_MOD JTAG U22 XTIN EESK TEST EECS USBDP <6> XTOUT USBDM RESET# 3V3OUT EEDATA

RSTOUT# AVCC

R189 470 RC0603_OV 46

AGND

VCC1

GND1

VCC2 GND2

42 18

GND3

VCCIOA GND4

DEBUG_5V 14 34

GND

VCCIOB 31 C157 0.1uF 25V 0402_cc FT2232D ADBUS2 ADBUS3 ADBUS4 SI/WUA BDBUS5 PWREN# ADBUS5 ADBUS6 ACBUS0 ACBUS1 ACBUS2 ACBUS3 BDBUS3 BDBUS4 BDBUS6 BDBUS7 BCBUS0 BCBUS1 BCBUS3 SI/WUB ADBUS0 ADBUS1 ADBUS7 BDBUS0 BDBUS1 BDBUS2 BCBUS2 26 24 23 38 22 21 20 10 35 41 19 17 15 13 12 11 37 36 33 32 30 29 27 16 40 39 28 C156 0.1uF 25V 0402_cc GND R191 10K 0402_CC 10K 0402_CC R190 TP59 UART2_TX232 UART2_RX233 DEBUG_UART2_EN 0.1uF 0402_cc C164 25V UART1_TX232 UART1_RX232 DEBUG2_RX_LED DEBUG2_TX_LED GND 0402_cc C159 0.1uF 25V 6 6 3 3 GND 470 470 2Y 2Y 1Y 1Y DEBUG1_RX_LED DEBUG1_TX_LED SN74LVC2G126 SN74LVC2G126 8 8 4 4 470 470 GND GND VCC VCC GND GND NVCC_3V1 DEBUG_UART1_EN U24 U23 2A 1OE 2A 1A 2OE 1OE 1A 2OE R213 R212 5 2 7 2 7 5 1 1 R210 R211 NVCC_3V1 4 4 2 2 Red Red Grn Grn D17 LED_RED-GRN D16 LED_RED-GRN 1 3 1 3 DEBUG_5V DEBUG_5V R192 10K 0402_CC R193 0 R198 10K 0402_CC R201 0 R197 0 R202 0 NVCC_3V1 TP20 TP21 TP23 TP24 Debug UART to USB Converter UART1_TXD UART2_TXD UART2_RXD UART1_RXD <6> <6> <6> <6> Debug UART for A9 Debug UART for M4

Figure 18. Schematic part 16

Powering an i.MX 6SX-based system using the PF3000 PMIC, Rev. 1.0 NXP Semiconductors 21 Schematics ADC2_IN1ADC2_IN3 <6> <6> ADC1_IN1ADC1_IN3 <6> <6> DNP 1000pF 50V 0402_CC SEN_3V1 C345 1 ACC_INT <6> L23 120OHM 2 DNP C344 1000pF 50V 0402_CC 1.0UF 10V C167 0402_cc 1000pF DNP C343 50V 0402_CC GND All interrupts are routed to INT2 by default. GND 1000pF DNP DNP C342 50V 0402_CC 0.1uF C166 25V 0402_cc R111R112 0 0 GND GND GND AGND 13 15 16 9 8 11 3 C165 0.1uF 25V 0402_cc 6 8 2 4 10

GND

NC3 NC8

VDD INT2 INT1

NC13 NC15 NC16 ACC_3V3 14 J20

HDR_2X5 VDDIO

R140 0 1 5 7 9 3 1

GND3

12 GND2

AGND 10 GND1

AGND 5 DNP C341 1000pF 50V 0402_CC SCL SDA SA0 BYP U26 MMA8451Q 4 6 2 7 DNP C340 1000pF 50V 0402_CC 12-bit ADC Connector GND C169 0.1uF 25V 0402_cc DNP C339 1000pF 50V 0402_CC ACCL_A0 ACCL_BYP 3-AXIS ACC GND DNP C338 1000pF 50V 0402_CC DNP 10K R220 R222 10K GND ADC1_IN0 ADC1_IN2 ADC2_IN2 ADC2_IN0 ALS_COMP_INT <6> (Active High) SW Note: Enable built-in Pull-up for normal operation; Disable built-in Pull-up during DSM. <6> <6> <6> <6> ACC_SDA ACC_SCL SEN_3V1 R250 10K DNP <22> <22> 0 SEN_3V1 5 4 R225 VCC MEM_3V1 GND NC7SP126 U39 3 2 1 GND COMP_INT ALS_INT_B R219 0 C168 0.1uF 25V 0402_cc GND SEN_3V1 (Active Low) (Active High) R221 499.0K 1% GND ALS_REXT ALS_3V3 COMP_SCLCOMP_SDA <22> <22> GND 3 1 2 U25 VDD GND REXT COMP_INT ISL29023 R224 0 C170 25V 0402_cc 0.1uF EP SDA SCL INT GND 7 4 6 5 6 7 9 SEN_3V1 MAG3110

GND

SCL SDA INT1

VDDIO GND2

8 10

GND1

COMP_3V3 VDD 2 5 GND CAP_A CAP_R NC U27 3 1 4 R223 10K R226 0 DNP ALS_INT_B COMP_CAPR COMP_NC COMP_CAPA Ambient Light Sensor Digital eCompass GND C172 25V 0.1uF 0402_cc GND ALS_SDA ALS_SCL C171 0.1uF 25V 0402_cc GND <22> <22>

Figure 19. Schematic part 17

Powering an i.MX 6SX-based system using the PF3000 PMIC, Rev. 1.0 NXP Semiconductors 22 Schematics Cable Pin 1 Cable Pin 20 NOTE: Pin 1 of the cable connector on the Smart Device board is opposite Pin 20 of the WIFI/BT module. For the FFC to lie flat, pin order number needs to be reversed on the schematics. J19 20 FPC/FFC CON 1 2 3 5 4 6 7 8 9 11 13 14 15 16 10 12 17 18 19 20 C284 0.1uF 25V 0402_cc GND GND PERI_3V3 Input to BT Input to BT Output from BT Output from BT SILEX_BT_DISABLE SILEX_BT_WAKEUP SILEX_BT_PWD_L BT_HOST_WAKE WOW BT_UART_RXD BT_UART_TXD BT_UART_CTS BT_UART_RTS TP61 TP60 DNP DNP R327R328 0 0 R329 0 R330 0 R332R333 330 330 R331 0 BLUETOOTH CABLE CONNECTOR TP113 UART5_RXD UART5_RTS_B BT_WAKEUP UART5_CTS_B BT_PWD_B UART5_TXD <6> <6> <7> <6> <6> <6> BT_WAKEUP is not used in current SW driver.

Figure 20. Schematic part 18

Powering an i.MX 6SX-based system using the PF3000 PMIC, Rev. 1.0 NXP Semiconductors 23 Schematics 4 4,6,9,17,21 POR_B PMIC_PWRON DNP R230 0 R229 0 POR Reset 1

RST

VCC1 VSS

6 2 GND See Note (ii) below This RC adds ~400ms on top of the default delay set in STM6779YWB6F (210ms (typ)). VSNVS_3V0 U45 RSTIN MRC MR 5 4 3 STM6779YWB6F GND GND DNP C455 33PF 50VDC 0402_cc VSNVS_3V0 C454 2.2UF 6.3V 0402_CC DNP R468 100K R470 470K A A D19 GND RB521S30T1G D18 Note: This block is added in Rev.C for two purposes - i) Fix the SW reboot issue by togling WDOG_B to issue power reset (ENGR00338067). ii) Delay the PMIC_PWRON >500ms for 1st-time power-on (VSNVS_3V0 is first applied), to ensure 32.768kHz xtal osc output is stable. C R469 330K R82 100 RB521S30T1G C174 1000pF 50V 0402_CC C R465 1M GND VSNVS_3V0 C453 1.0UF 10V 0402_CC 1 2 SW3 SPST PB RESET WDOG_B 3 4 6 See Note (i) below GND RESET button is far away from reset circuit. This RC is used to enhance the EMC susceptibility. GND GND 2 2 1 1 FUNC1 FUNC2 SW4 SW5 SPST PB SPST PB 3 4 3 4 Buttons ONOFF <6> R183 1K R181 1K DNP C173 0.1uF 25V 0402_cc GND 3 4 KEY_FUNC2 KEY_FUNC1 ON/OFF <7> SW2 SPST PB <7> On/Off 2 1 GND

Figure 21. Schematic part 19

Powering an i.MX 6SX-based system using the PF3000 PMIC, Rev. 1.0 NXP Semiconductors 24 Schematics BOOT_MODE1 <6> TEST_MODESNVS_TAMPER <6> <6> BOOT_MODE0 <6> 4 3 S1 SW_DIP-2/SM 1 2 R365 1K DNP R367 10K R234 1K DNP R364 10K R366 1K R233 1K GND VSNVS_3V0 VSNVS_3V0 SW Design Note: LCD_DATA lines should be set at Input with Keeper enable during Deep Sleep Mode. LCD1_DATA1LCD1_DATA2LCD1_DATA3 <7,13> <7,13> <7,13> LCD1_DATA4LCD1_DATA5LCD1_DATA6 <7,13> LCD1_DATA7 <7,13> <7,13> <7,13> LCD1_DATA8LCD1_DATA9LCD1_DATA10 <7,13> LCD1_DATA11 <7,13> <7,13> <7,13> LCD1_DATA12LCD1_DATA14 <7,13> LCD1_DATA15 <7,13> <7,13> LCD1_DATA16LCD1_DATA17LCD1_DATA18 <7,13> LCD1_DATA19 <7,13> <7,13> <7,13> LCD1_DATA20LCD1_DATA22 <7,13> <7,13> LCD1_DATA0 <7,13> LCD1_DATA13 <7,13> LCD1_DATA21LCD1_DATA23 <7,13> <7,13> Note: i.MX6SX reads values approximately 300uS to 1mS after reset released. Buffers are active while unit is in reset and 1ms-10ms after is released. R264 4.7K R270R272R274 4.7K 4.7K 4.7K R276R280R282 4.7K 4.7K 4.7K R298R300 4.7K R302R306 4.7K 4.7K 4.7K R260R262R266 4.7K 4.7K R268 4.7K 4.7K R278 4.7K R284R286R288R290 4.7K 4.7K 4.7K 4.7K R292R294R296 4.7K 4.7K 4.7K R304 4.7K C334 0.1uF 25V 0402_cc C333 0.1uF 25V 0402_cc NVCC_3V1 NVCC_3V1 NVCC_3V1 GND GND GND 20 16 16 14 3 14 3 14 12 3 5 7 9 18 12 5 7 9 18 12 7 9 10 18 10 10 20 20 16 5 GND C332 0.1uF 25V 0402_cc 1Y1 1Y1 1Y2 2Y0 1Y1 1Y2 2Y0 2Y1 1Y2 1Y3 2Y0 2Y1 2Y2 2Y3 1Y0 1Y3 2Y1 2Y2 2Y3 1Y0 1Y3 2Y2 2Y3 1Y0 VCC VCC VCC GND GND GND GND DNP NVCC_3V1 1A0 1A1 1OE 2A2 2A3 2OE 1A0 1A1 1A3 1OE 2A0 2A1 2A3 2OE 1A0 1A1 1A2 1OE 2A2 2OE 1A2 1A3 2A0 2A1 1A2 2A2 1A3 2A0 2A1 2A3 U36 74LVC244APW U37 74LVC244APW U35 74LVC244APW 6 6 8 6 8 1 1 1 2 4 2 4 8 2 4 17 11 19 19 19 13 11 17 15 11 13 15 13 17 15 R238 0 Note: i) SW10 settings are all "0". ii) BT_CFG1 must be "1" for SD3 operation on SDB, as it has a power switch control for VCC_SD3. BT_CFG0 BT_CFG1 BT_CFG3 BT_CFG6 BT_CFG7 BT_CFG9 BT_CFG10 BT_CFG11 BT_CFG12 BT_CFG28 BT_CFG29 BT_CFG30 BT_CFG31 BT_CFG2 BT_CFG4 BT_CFG5 BT_CFG8 BT_CFG13 BT_CFG14 BT_CFG15 BT_CFG24 BT_CFG25 BT_CFG26 BT_CFG27 R237C331 1.0UF 0 10V 0402_CC SW12 SW DIP-8

R232 47K GND 9 8

10 7

11 6

NVCC_3V1 12 5

13 4

14 3

15 2

16 1 C175 0.1uF 25V 0402_cc 8 7 6 5 GND 2G 1Y 2A SW11 SW DIP-8

VCC

NVCC_3V1

9 8

10 7

11 SN74LVC2G125 6

U38

2Y GND 1G 1A 12 5

BOOT MODE 13 2 3 4 4 1

14 3

15 2

16 1 GND

SW10 SW DIP-8

9 8

VCC_BOOTSTRAP 10 7

11 6

12 5

13 4

14 3

15 2

16 1 POR_B DNP R235 0 R236 0 <4,6,9,17,20> R269R273 33K 33K R275R277 33K R281 33K 33K R297 33K R299R303 33K 33K R259R261R263 33K R265 33K 33K 33K R267R271 33K 33K R279 33K R283R285R287 33K R289 33K 33K 33K R291R293R295 33K 33K 33K R301R305 33K 33K NVCC_3V1 GND

Figure 22. Schematic part 20

Powering an i.MX 6SX-based system using the PF3000 PMIC, Rev. 1.0 NXP Semiconductors 25 Schematics AUD_SDA <12> PCIE_CLK_GEN_SDA <16> PCIE_CLK_GEN_SCL <16> AUD_SCL <12> DNP DNP R408 0 R412 0 R410R405 0 0 R413 2.2K R409 2.2K NVCC_1V8 CGND NVCC_1V8 0 DNP 4C2I C358 10uF R441 I2C4_SCL I2C4_SDA GND <7> <7> CGND 0 DNP C330 10uF PCIE_I2C_SDA <16> COMP_SDA <18> ALS_SDA <18> ACC_SDA <18> PCIE_I2C_SCL <16> ACC_SCL <18> ALS_SCL <18> COMP_SCL <18> R124 GND R418 0 R404 0 R415 0 R416 0 R414 0 R407 0 R417 0 R419 0 R406 CGND R403 1K 1K 0 DNP NVCC_3V1 NVCC_3V1 C329 10uF 3C2I R123 GND I2C3_SCL I2C3_SDA <6> <6> CGND 0 DNP C328 10uF R122 GND CGND is connected to the connectors enclosure or chassis. Resistor and capacitor footprints are arranged for ESD test. LVDS_I2C_SCL_TCH <13> LVDS_I2C_SCL_EDID <13> LVDS_I2C_SDA_EDID <13> LVDS_I2C_SDA_TCH <13> System GND and Chassis GND Connections R423 0 R398 0 R401 0 R424 0 R397 2.2K R400 2.2K NVCC_3V1 NVCC_3V1 2C2I I2C2_SCL I2C2_SDA <6> <6> TP32 TP31 GND H4 .635" LONG TP30 PMIC_SDA <4> LCD_CSI_SDA <13> TP29 LCD_CSI_SCL <13> PMIC_SCL <4> GND H3 .635" LONG TP28 H2 GND GND .635" LONG R393 0 R395 0 R392 0 R396 0 R394 2.2K TP27 R12 2.2K H1 GND .635" LONG NVCC_3V1 NVCC_3V1 TP26 Note: Pull-up resistor must be sized to meet the signal rise times and also the Vil spec of all the bus components. Due to board loadings this resistor was reduced. Validate your design, with the largest allowable resistor to reduce current consumption. TP25 I2C1 I2C1_SCL I2C1_SDA IMPORTANT NOTE : Use non-conducting nut/bolts to mount the board on a Use non-conducting nut/bolts to mount the board on so metallic chasis connected to external GND. Not doing may cause board damage due to GND potential difference. Board Mounting Holes for 4-40 Screws 4-40 for Holes Mounting Board <6> <6>

Figure 23. Schematic part 21

Powering an i.MX 6SX-based system using the PF3000 PMIC, Rev. 1.0 NXP Semiconductors 26 References

8 References

Following are URLs where you can obtain information on related NXP products and application solutions:

Support pages Description URL

i.MX 6SX Product Summary Page http://www.nxp.com/webapp/sps/site/prod_summary.jsp?code=i.MX6SX

PF3000 Product Summary Page http://www.nxp.com/webapp/sps/site/prod_summary.jsp?code=PF3000

PF3000 Layout Application Note http://www.nxp.com/files/analog/doc/app_note/AN5094.pdf Guidelines

NXP Community Support Site https://community.nxp.com/docs/DOC-105064

Powering an i.MX 6SX-based system using the PF3000 PMIC, Rev. 1.0 NXP Semiconductors 27 Revision history

9 Revision history

Revision Date Description 7/2015 • Initial release 1.0 7/2016 • Updated to NXP document form and style

Powering an i.MX 6SX-based system using the PF3000 PMIC, Rev. 1.0 NXP Semiconductors 28 How to Reach Us: Information in this document is provided solely to enable system and software implementers to use NXP products. There Home Page: are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on NXP.com the information in this document. NXP reserves the right to make changes without further notice to any products herein. Web Support: NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, http://www.nxp.com/support nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation, consequential or incidental damages. "Typical" parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each customer application by the customer's technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address:

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Document Number: AN5161 Rev. 1.0 7/2016