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MACHXO3L DSI Breakout Board Schematics

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MACHXO3L DSI Breakout Board Schematics 5 4 3 2 1 XO3L Breakout Board Revision B May, 2014 D D LEDS(1-4) RGB LED PMOD I/Os BANK 1 Header I/Os FPGA SMA INPUT I/Os LCMXO3L-6900C-6BG256C C U7 C BANK 2 & 3 BANK 0 & 5 SMA OUTPUT Header BANK 4 SPI I/Os FLASH Optional I2C PMOD Configuration USB to JTAG USB CONNECTOR USB to I2C Optional JTAG Configuration B B FPGA I/Os I/Os LCMXO3L-2100E-6UWG49CTR U9 MIPI_INPUT MIPI_OUTPUT A A Lattice Semiconductor Applications Email: [email protected] Title Block Diagram Size Project Schematic Rev B C MachXO3L DSI Breakout Board Board Rev B Date: May, 2014 Sheet of 71 5 4 3 2 1 5 4 3 2 1 D D 3.3V FB4 3.3V Optional JTAG VCCIO Header when C5 C6 C7 C8 C9 FB_60ohm 1 C1 C2 VCCIO is 2.5V R211 R212 R213 PART_NUMBER = HI0603P600R-10 VCCIO 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 3.3V Manufacturer = Laird-signal 4.7uF 0.1uF 4.7K 4.7K 4.7K 2 J1 FB5 1 1 2 2 FTDI_TDO [Pg7] 3 FTDI_TDI [Pg5] 3 4 FB_60ohm 1 C3 C4 4 5 PART_NUMBER = HI0603P600R-10 5 6 FTDI_TMS [Pg5,7] Manufacturer = Laird-signal 4.7uF 0.1uF 6 7 2 7 8 FTDI_TCK [Pg5,7] 3.3V 8 header_1x8 DNI R220 1K TP6 3.3V U1 FT2232HL 4 9 12 37 64 20 31 42 56 VPLL VPHY VCCIO VCCIO VCCIO VCCIO VCORE VCORE VCORE 16 0 R5 50 ADBUS0 17 0 R6 VREGIN ADBUS1 18 0 R7 C 49 ADBUS2 19 0 R8 C VREGOUT ADBUS3 21 ADBUS4 22 ADBUS5 DM[Pg3] 7 23 8 DM ADBUS6 24 DP[Pg3] DP ADBUS7 C10 C11 26 VCCIO R218 1K 14 ACBUS0 27 10uF 0.1uF RESET# ACBUS1 28 3.3V ACBUS2 29 R221 12K 6 ACBUS3 30 3.3V REF ACBUS4 32 R216 R217 ACBUS5 33 R16 R17 R18 ACBUS6 34 1K 1K 10K 10K 10K 63 ACBUS7 62 EECS 38 0 R203 DNL SCL_2 [Pg7] U2 61 EECLK BDBUS0 39 0 R204 DNL SDA_2 [Pg7] 8 1 EEDATA BDBUS1 40 0 R205 DNL 7 VCC CS 2 BDBUS2 41 6 NU CLK 3 2 BDBUS3 43 C12 5 ORG DI 4 OSCI BDBUS4 44 VSS DO R219 1K BDBUS5 45 0.1uF 93LC56-SO8 X1 BDBUS6 46 DNI R11 SCL_1 [Pg5] Optional I2C 1 3 3 BDBUS7 DNI R12 SDA_1 [Pg5] 1 3 OSCO 48 DNI R13 Configuration 2 4 BCBUS0 52 C13 G1 G2 C14 BCBUS1 53 BCBUS2 18pF 12MHZ 18pF 13 54 TEST BCBUS3 55 BCBUS4 57 BCBUS5 FTDI High-Speed USB 58 BCBUS6 59 BCBUS7 FT2232H 60 PWREN# 36 SUSPEND# J50 B B AGND GND GND GND GND GND GND GND GND 1 5 XO3L_2100E_TDO 1 4 XO3L_6900C_TDI 10 11 15 25 35 47 51 2 5 FTDI_TDI FTDI_TDO 3 6 XO3L_6900C_TDO XO3L_2100E_TDI Value = 3X2_HEADER DEFAULT_OPTION = 1&4 and 3&6 A A Lattice Semiconductor Applications Email: [email protected] Title USB to JTAG Size Project Schematic Rev B C MachXO3L DSI Breakout Board Board Rev B Date: May, 2014 Sheet of 72 5 4 3 2 1 5 4 3 2 1 Test Points TP1 12V 1 D D TP_LOOP_RED TP3 5V 1 TP_LOOP_RED TP5 1 TP_LOOP_BLACK 12V Power Options 5V Power Options 1) External 12V DC Supply 1) Regulated 5V Supply 2) Signet Main Board Connector 2) USB 5V Current Sense TP 5V_Reg D1 5V 5V Rail 12V DC JACK PWR Jack_12V MIPI_VCC_12V_IN VBUS_5V 5V U5 3.31V 3.3V 1 TP33H TP33L 3.3V Rail 2 R36 3 RB496EA R30 18 3 17 IN1_1 OUT1_1 J2 RB496EA 14 IN1_2 4 C25 0.1 D2 1K 1 13 IN2_1 OUT1_2 R37 C29 R38 0.1 OHM 1/2W 1% 0805 C30 C26 D3 IN2_2 0.01uF 12V C16 Green C27 R39 R40 20 2 357K 10uF 127 22uF 0.1uF C L1 SHDN1 BYP1 R41 210K C 0.1uF 10uF 1M 1M 11 1 600 Ohm 500 mA SHDN2 ADJ1 2 1.22V TP12H TP12L 1.2V 19 R42 J3 PWRGD1 7 1.2V Rail 1 12 OUT2_1 VCC 2 PWRGD2 8 C40 0.1 D- DM [Pg2] OUT2_2 3 DP [Pg2] C38 R43 0.1 OHM 1/2W 1% 0805 C39 D+ 4 R31 0 0.01uF ID 5 21 9 4.7uF 127 22uF GND C17 0.1uF THERMPAD BYP2 10 SKT_MINIUSB_B_RA ADJ2 USB Power GND1 GND2 GND3 GND4 5 6 16 15 LT3030EFE#TRPBF 12V U11 5V_Reg LT3680 4 1 VIN BD C20 C129 10uF 5 R231 47uF RUN_SS 536K VCCIO Select 9 - 3.3V Default VC 8 R232 Current Sense TP FB 100K - 2.5V Optional 10 2 RT BOOST 5V U6 2.51V 2.5V 2.5V Rail 3.3V 2.5V VCCIO TP25H TP25L C128 R229 7 R44 PG 15K 0.47uF L3 R32 R33 18 3 R230 3 17 IN1_1 OUT1_1 B SW 0 DNI IN1_2 B 34K 6 4.7uH 14 4 C44 0.1 SYNC 11 13 IN2_1 OUT1_2 R48 C43 R45 0.1 OHM 1/2W 1% 0805 C48 C49 C127 EPAD D12 IN2_2 0.01uF 680pF LT3680 Manufacturer = ON Semi C45 R46 R47 20 2 255K 10uF 127 22uF 0.1uF Manufacturer = Linear PART_NUMBER = MBRA340T3G SHDN1 BYP1 R49 243K PART_NUMBER = LT3680EDD#PBF 10uF 1M 1M 11 1 SHDN2 ADJ1 1.81V TP18H TP18L 1.8V 19 R50 1.8V Rail PWRGD1 7 12 OUT2_1 PWRGD2 8 C57 R51 0.1 OUT2_2 C58 R52 C59 0.01uF 113K 0.1 OHM 1/2W 1% 0805 21 9 4.7uF 127 22uF THERMPAD BYP2 R53 237K 10 ADJ2 GND1 GND2 GND3 GND4 5 6 16 15 LT3030EFE#TRPBF A A Lattice Semiconductor Applications Email: [email protected] Title Board Power Size Project Schematic Rev B C MachXO3L DSI Breakout Board Board Rev B Date: May, 2014 Sheet of 73 5 4 3 2 1 5 4 3 2 1 MIPI RX Termination Place resistors as close to the bank 2 pins on XO3 as possible. Arrange them so they do not influence the *HS* trace path. Match trace length for all P and N signals. Match lengths between HS signals, match lengths between LP signals. U7C SMA Connectors BANK2 [Pg4] PIO_P4 P4 M8 PIO_M8 [Pg4] T4 PB3A/PB3A/PB4A PB16C/PB18A/PB21A N9 [Pg4] PIO_T4 PB3B/PB3B/PB4B PB16D/PB18B/PB21B PIO_N9 [Pg4] 3 2 3 2 51 R54 CLKIN0_LP_P [Pg4] T2 T9 J4 J5 [Pg4] PIO_T2 CLKIN0_HS_P [Pg4] 3 2 3 2 R3 PB3C/PB3C/PB4C PB16A/PB20A/PB23A || PCLKT2_1 P9 [Pg4] PIO_R3 PB3D/PB3D/PB4D PB16B/PB20B/PB23B || PCLKC2_1 CLKIN0_HS_N [Pg4] SMA73391-0060 1 CLKIN0_HS_P [Pg4] SMA73391-0060 1 CLKIN1_HS_P [Pg4] 51 R55 CLKIN0_LP_N [Pg4] 1 1 [Pg4] SSn_256 R5 R9 PIO_R9 [Pg4] 4 5 4 5 P5 PB5A/PB4A/PB6A || CSSPIN PB18A/PB21A/PB26A T10 D PB5B/PB4B/PB6B PB18B/PB21B/PB26B PIO_T10 [Pg4] 4 5 4 5 D [Pg4] DIN7_HS_P T3 M9 PIO_M9 [Pg4] R4 PB6C/PB6A/PB7A PB18C/PB21C/PB26C L10 [Pg4] DIN7_HS_N PB6D/PB6B/PB7B PB18D/PB21D/PB26D PIO_L10 [Pg4] [Pg4] DIN5_HS_P T5 N10 PIO_N10 [Pg4] R6 PB6A/PB7A/PB9A PB19C/PB23C/PB28A M11 [Pg4] DIN5_HS_N PB6B/PB7B/PB9B PB19D/PB23D/PB28B PIO_M11 [Pg4] 3 2 3 2 51 R56 DIN0_LP_P [Pg4] N6 P10 J6 J7 [Pg4] DIN3_HS_P PB8C/PB9C/PB10A PB19A/PB23A/PB29A DIN0_HS_P [Pg4] 3 2 3 2 L7 R10 SMA73391-0060 SMA73391-0060 [Pg4] DIN3_HS_N PB8D/PB9D/PB10B PB19B/PB23B/PB29B DIN0_HS_N [Pg4] 1 CLKIN0_HS_N [Pg4] 1 CLKIN1_HS_N [Pg4] 51 R57 DIN0_LP_N [Pg4] 1 1 4 5 4 5 [Pg4] SCLK_256 P6 T11 T6 PB8A/PB9A/PB12A || MCLK/CCLK PB21A/PB24A/PB31A P11 [Pg4] MISO_256 PB8B/PB9B/PB12B || SO/SPISO PB21B/PB24B/PB31B 4 5 4 5 [Pg4] DIN1_LP_P 51 R58 [Pg4] DIN1_HS_P R7 M10 PIO_M10 [Pg4] P7 PB9A/PB10A/PB13A PB21C/PB24C/PB31C N11 [Pg4] DIN1_HS_N PB9B/PB10B/PB13B PB21D/PB24D/PB31D PIO_N11 [Pg4] [Pg4] DIN1_LP_N 51 R59 [Pg4] PIO_M7 M7 N7 PB9C/PB10C/PB13C R13 [Pg4] PIO_N7 PB9D/PB10D/PB13D PB22C/PB26A/PB34A DIN2_HS_P [Pg4] 3 2 3 2 T14 DIN2_HS_N [Pg4] M6 PB22D/PB26B/PB34B J8 J9 [Pg4] PIO_M6 PB11C/PB12A/PB15A 3 2 3 2 [Pg4] PIO_L8 L8 R11 DIN4_HS_P [Pg4] VCCIO SMA73391-0060 DIN0_HS_P [Pg4] SMA73391-0060 DIN1_HS_P [Pg4] PB11D/PB12B/PB15B PB22A/PB27A/PB35A Pull-up resistor R62 is for 1 1 T12 DIN4_HS_N [Pg4] 1 1 PB22B/PB27B/PB35B cases where I2C is used. If 4 5 4 5 [Pg4] CLKIN1_LP_P 51 R60 T7 P12 R62 I2C is not used for programming [Pg4] CLKIN1_HS_P DIN6_HS_P [Pg4] this pull-up is not required. 4 5 4 5 R8 PB11A/PB13A/PB16A || PCLKT2_0 PB24A/PB29A/PB37A T13 [Pg4] CLKIN1_HS_N PB11B/PB13B/PB16B || PCLKC2_0 PB24B/PB29B/PB37B DIN6_HS_N [Pg4] 4.7K [Pg4] CLKIN1_LP_N 51 R61 [Pg4] PIO_P8 P8 R12 T8 PB12A/PB15A/PB18A PB25A/PB30A/PB38A || SN P13 R222 DNI [Pg4] PIO_T8 PB12B/PB15B/PB18B PB25B/PB30B/PB38B || SI/SISPI MOSI_256 [Pg4] N8 T15 L9 PB12C/PB15C/PB18C PB25C/PB30C/PB38C R14 VCCIO 3 2 3 2 PB12D/PB15D/PB18D PB25D/PB30D/PB38D J10 J11 3 2 3 2 SMA73391-0060 DIN0_HS_N [Pg4] SMA73391-0060 DIN1_HS_N [Pg4] 1 1 1 1 0 4 5 4 5 R64 K8 N5 4 5 4 5 C C63 C64 K9 VCCIO2/VCCIO2/VCCIO2 VCCIO2/VCCIO2/VCCIO2 N12 C VCCIO2/VCCIO2/VCCIO2 VCCIO2/VCCIO2/VCCIO2 C66 C67 C61 0.1uF 0.1uF 2K/4K/7K || 2nd_Fn. 0.1uF 0.1uF 1uF 3 2 3 2 LCMXO3L-6900C-6BG256C J12 J13 3 2 3 2 SMA73391-0060 DIN2_HS_P [Pg4] SMA73391-0060 DIN3_HS_P [Pg4] 1 1 1 1 4 5 4 5 4 5 4 5 3 2 3 2 J14 J15 3 2 3 2 SMA73391-0060 DIN2_HS_N [Pg4] SMA73391-0060 DIN3_HS_N [Pg4] 1 1 1 1 4 5 4 5 4 5 4 5 XO3L Configuration SPI Flash 3.3V IO Header 3 2 3 2 J17 J18 3 2 3 2 C122 SMA73391-0060 DIN4_HS_P [Pg4] SMA73391-0060 DIN5_HS_P [Pg4] 3.3V 3.3V 1 1 1 1 0.1uF J16 4 5 4 5 2 1 4 5 4 5 [Pg4] PIO_P4 4 3 PIO_M8 [Pg4] U10 6 5 1k R196 1k R195 1k R194 B 8 [Pg4] PIO_T4 PIO_N9 [Pg4] B 10K R197 8 7 Place close to U10 [Pg4] PIO_T2 PIO_R9 [Pg4] [Pg4] PIO_R3 10 9 PIO_T10 [Pg4] Place close to U7 5 2 12 11 [Pg4] MOSI_256 MISO_256 [Pg4] [Pg4] PIO_P8 PIO_M9 [Pg4] 3 2 3 2 SDI VCC SDO [Pg4] PIO_T8 14 13 PIO_L10 [Pg4] 20R227 6 16 15 J19 J20 [Pg4] SCLK_256 [Pg4] PIO_M7 PIO_N10 [Pg4] 3 2 3 2 SCK 18 17 [Pg4] PIO_N7 PIO_M11 [Pg4] SMA73391-0060 1 DIN4_HS_N [Pg4] SMA73391-0060 1 DIN5_HS_N [Pg4] 3 [Pg4] PIO_M6 20 19 PIO_M10 [Pg4] 1 1 WP 4 5 4 5 C130 [Pg4] PIO_L8 22 21 PIO_N11 [Pg4] Place close to U10 30pF 1 7 24 23 [Pg4] SSn_256 4 5 4 5 DNI CS HOLD GND HEADER 12X2 4 M25PX16-VMN6TP DNI 3 2 3 2 J21 J22 3 2 3 2 SMA73391-0060 DIN6_HS_P [Pg4] SMA73391-0060 DIN7_HS_P [Pg4] 1 1 1 1 4 5 4 5 4 5 4 5 U7D 3 2 3 2 BANK3 J23 J24 3 2 3 2 N2 SMA73391-0060 DIN6_HS_N [Pg4] SMA73391-0060 DIN7_HS_N [Pg4] L1 PL13C/PL18C/PL23C P1 1 1 1 1 L3 PL11A/PL16A/PL19A PL13D/PL18D/PL23D 4 5 4 5 PL11B/PL16B/PL19B M3 CLKIN0_LP_P [Pg4] 4 5 4 5 K4 PL13A/PL19A/PL24A N1 [Pg4] CLKIN1_LP_P CLKIN0_LP_N [Pg4] L5 PL11C/PL16C/PL19C PL13B/PL19B/PL24B [Pg4] CLKIN1_LP_N PL11D/PL16D/PL19D M2 DIN0_LP_P [Pg4] K5 PL14A/PL20A/PL25A N3 [Pg4] DIN1_LP_P L4 PL12C/PL17C/PL21C PL14B/PL20B/PL25B DIN0_LP_N [Pg4] A [Pg4] DIN1_LP_N A PL12D/PL17D/PL21D R1 PL14C/PL20C/PL25C P2 PL14D/PL20D/PL25D 1.2V L2 M1 PL12A/PL17A/PL22A || PCLKT3_0 PL12B/PL17B/PL22B || PCLKC3_0 0 R65 Lattice Semiconductor Applications M4 VCCIO3/VCCIO3/VCCIO3 Email: [email protected] C70 C71 2K/4K/7K || 2nd_Fn.
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