MARIE: An Introduction to a Outline Simple Computer Learn the components common to every modern computer system. Be able to explain how each component contributes to program execution. Understand a simple architecture invented Machine Architecture that is Really to illuminate these basic concepts, and how Intuitive and Easy it relates to some real architectures. Know how the program assembly works.

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44..11 Introduction 44..22 CPU Basic and Organization

Chapter 1 presented a general overview of The computer’s CPU fetches, decodes, and computer systems. executes program iiinstructions. In Chapter 2, we discussed how data is stored and manipulated by various The two principal parts of the CPU are the computer system components. and the . Chapter 3 described the fundamental The datapath consists of an arithmetic-logic unit components of digital circuits. and storage units (registers) that are Having this background, we can now interconnected by a data that is also unddhderstand how computer components connected to main memory. work, and how they fit together to create Various CPU components perform sequenced useful computer systems. operations according to signals provided by its control unit.

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1 44..22 CPU Basic and Organization 44..33 The BUS

Registers hold data -- addresses, program counters, The CPU shares data with other system data -- that can be readily accessed by the CPU. comppyyonents by way of a data bus. Size of a register varies according to the design. A bus is a set of wires that simultaneously convey a single bit along each line. The number of registers varies from architecture to Two types of buses are commonly found in architecture. computer systems: point-to-point, and multipoint They can be implemented using D flip-. buses. A 32-bit register requires 32 D flip-flops. The arithmetic-logic unit (ALU) carries out logical and arithmetic operations as directed by the control unit. The control unit determines which actions to carry out according to the values in a program register and a .

point-to-point bus configuration multipoint configuration

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44..33 The BUS 44..33 The BUS

Buses consist of data lines, control lines, and address lines. A multipoint bus is shown below. Data lines convey bits from one device to another Because a multipoint bus is a shared Control lines determine the direction of data flow resource, access to it is controlled through when each device can access the bus protocols, which are built into the Acknowledge bus request, interrupts, and clock synchronization signals hardware. Address lines determine the location of the source or destination of the data.

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2 44..33 The BUS 44..33 The BUS

Bus transactions: In a master-slave configuration, where more than one Sending an address for a read or write device can be the bus master, concurrent bus master Transferring data from memory to a register for memory read requests must be arbitrated. Transferring data from a register to memory for memory write Four categories of bus arbitration are: I/O reads and writes from peripheral devices Daisy chain: Permissions are passed from the Each transfer occurs within a bus cycle highest-priority device to the lowest. Centralized parallel: Each device is directly connected to an arbitration circuit. Distributed using self-detection: Devices decide which gets the bus among themselves. Distributed using collision-detection: Any device can try to use the bus. If its data collides with the data of another device, it tries again.

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44..44 Clocks 44..44 Clocks

Every computer contains at least one clock that Clock speed should not be confused with CPU synchronizes the activities of its components. performance. A fixed number of clock cycles are required to carry The CPU time required to run a program is given by out each data movement or computational operation. the general performance equation: The clock frequency, measured in megahertz or gigahertz, determines the speed with which all operations are carried out. We see that we can improve CPU throughput when Clock cycle time is the reciprocal of clock frequency. we reduce the number of instructions in a program, An 800 MHz clock has a cycle time of 1.25 ns. reduce the number of cyypcles per instruction, or reduce the number of nanoseconds per clock cycle. Multiplication operation Intel 286 required 20 clock cycles Pentium required 1 clock cycle

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3 44..66 Memory Organization and 44..55 Input/Output Subsystem Addressing

Computer memory consists of a linear array of addressable A computer communicates with the outside storage cells that are similar to registers. world through its input/output (I/O) Memory can be btbyte-addressa ble, or word-addressa ble, where a subsystem. word typically consists of two or more bytes. Memory is constructed of RAM chips, often referred to in terms of I/O devices connect to the CPU through length  width. various interfaces. If the memory word size of the machine is 16 bits, then a 4M  16 RAM chip gives us 4 megabytes of 16-bit memory locations. I/O can be memory-mapped-- where the I/O device behaves like main memory from the CPU’s point of view. O/OOr I/O can be instruction-bdhbased, where th e CPU has a specialized I/O instruction set.

We study I/O in detail in chapter 7.

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44..66 Memory Organization and 44..66 Memory Organization and Addressing Addressing How does the computer access a memory Physical memory usually consists of more location corresponds to a particular than one RAM chip. address? Access is more efficient when memory is We observe that 4M can be expressed as organized into banks of chips with the 22  220 = 222 words. addresses interleaved across the chips The memory locations for this memory are With low-order interleaving, the low order numbered 0 through 222 1. bits of the address specify which memory Thus, the memory bus of this system bank contains the address of interest. requires at least 22 address lines. Accordldingly, in hhhigh-ordlder interleaving, the The address lines “count” from 0 to 222 -1 in high order address bits specify the memory binary. Each line is either “on” or “off” indicating bank. the location of the desired memory element.

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4 44..66 Memory Organization and Addressing Problem 4 Page 260

How many bits would you need to address a 2M  32 memory if a. The memory is byte-addressable?

Low-Order Interleaving b. The memory is word-addressable?

a. There are 2M × 4 byyqtes which equals 2 × 220 × 22 = 223 total bytes, so 23 bits are needed for an address b. There are 2M words which equals 2 × 220 = 221, so 21 bits are required for an address

High-Order Interleaving

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Problem 5 Page 260 Problem 9 Page 260

Suppose that a 2M  16 main memory is built using How many bits would you need to 256K  8 RAM chips and memory is word-addressable. address a 4M  16 memory if a. How many RAM chips are necessary? a. The memory is byte-addressable? b. How many RAM chips are there per memory word? c. How many address bits are needed for each RAM b. The memory is word-addressable? chip? d. How many banks will this memory have? e. How many address bits are needed for all of 20 2 23 a. There are 2M × 4 byyqtes which equals 2 × 2 × 2 = 2 total memory? bytes, so 23 bits are needed for an address b. There are 2M words which equals 2 × 220 = 221, so 21 bits f. If high-order interleaving is used, where would are required for an address address 14 (which is E in hex) be located? g. Repeat Exercise 6f for low-order interleaving.

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5 Problem 9 Page 260 Problem 11 Page 261

A digital computer has a memory unit with 24 bits per 000 218  23 218  23 00000 – 3FFFF word. The instruction set consists of 150 different operations. All instructions have an operation code 001 218  23 218  23 00000 – 3FFFF part (opcode) and address part (allowing for only one address). Each instruction is stored in one word of 010 218  23 218  23 00000 – 3FFFF memory. 011 218  23 218  23 00000 – 3FFFF a. How many bits are needed for the opcode?

100 218  23 218  23 00000 – 3FFFF b. How many bits are left for the address part of the instruction? 18 3 18 3 101 2  2 2  2 00000 – 3FFFF c. What is the maximum allowable size for memory? 110 218  23 218  23 00000 – 3FFFF d. What is the largest unsigned binary number that can be accomplished in one word memory? 111 218  23 218  23 00000 – 3FFFF

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44..77 Interrupts 44..88 MARIE

The normal execution of a program is altered when an We can now bring together many of the ideas that we event of higher-ppyriority occurs. The CPU is alerted to have discussed to this ppgypoint using a very simple such an event through an interrupt. model computer. Interrupts can be triggered by I/O requests, Our model computer, the Machine Architecture that is arithmetic errors (such as division by zero), or when Really Intuitive and Easy, MARIE, was designed for an invalid instruction is encountered. the singular purpose of illustrating basic computer Each interrupt is associated with a procedure that system concepts. directs the actions of the CPU when an interrupt While this system is too simple to do anything useful occurs. in the real world, a deep understanding of its Nonmaskable interrupts are high-priority interrupts that functions will enable you to comprehend system cannot be ignored. architectures that are much more complex.

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6 44..88 MARIE 44..88 MARIE

The MARIE architecture has the following MARIE’s seven registers are: Accumulator, AC, a 16-bit general-purpose register that holds a characteristics: conditiona l opera tor (e.g., "less than") or one operand of a two- Binary, two's complement data representation. operand instruction. , MAR, a 12-bit register that holds the Stored program, fixed word length data and memory address of an instruction or the operand of an instruction. instructions. , MBR, a 16-bit register that holds the data 4K words of word-addressable main memory. after its retrieval from, or before its placement in memory. , PC, a 12-bit register that holds the address of 16-bit data words. the next program instruction to be executed. 16-bit instructions, 4 for the opcode and 12 for the Instruction register, IR, which holds an instruction immediately addaddress.ress. preceding its execution. Input register, InREG, an 8-bit register that holds data read from A 16-bit (ALU). an input device. Seven registers for control and data movement. Output register, OutREG, an 8-bit register, that holds data that is ready for the output device.

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44..88 MARIE 44..88 MARIE

The registers are interconnected, and connected with This is the MARIE architecture shown main memoryyg through a common data bus. graphically. Each device on the bus is identified by a unique number that is set on the control lines whenever that device is required to carry out an operation. Separate connections are also provided between the accumulator and the memory buffer register, and the ALU and the accumulator and memory buffer register. This permits data transfer between these devices without use of the main data bus.

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7 44..88 MARIE 44..88 MARIE

This is the MARIE A computer’s instruction set architecture (ISA) specifies the format of its instructions data path shown and the primitive operations that the graphically. machine can perform. The ISA is an interface between a computer’s hardware and its software. Some ISAs include hundreds of different instructions for processing data and controlling program execution. The MARIE ISA consists of only thirteen instructions.

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44..88 MARIE 44..88 MARIE

This is the format This is a bit pattern for a LOAD instruction of a MARIE instructi on: as it would appear in th e IR: The fundamental MARIE instructions are:

We see that the opcode is 1 and the address from which to load the data is 3.

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8 44..88 MARIE 44..88 MARIE This is a bit pattern for a SKIPCOND instruction as it Each of our instructions actually consists of would appear in the IR: a sequence of smaller instructions called microoperations. The exact sequence of microoperations that are carried out by an instruction can be specified using register transfer language (RTL). We see that the opcode is 8 and bits 11 and 10 are In the MARIE RTL, we use the notation 10, meaning that the next iitnstructi on will be skipped M[X] to indicate the actual data value if the value in the AC is greater than zero. stored in memory location X, and  to 00 if AC < 0, 01 if AC = 0, 10 if AC > 0 indicate the transfer of bytes to a register or memory location. What is the hexadecimal representation of this instruction?

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44..88 MARIE 44..88 MARIE

The RTL for the LOAD instruction is: The RTL for the Store instruction is: MAR  X MAR  X  This operation requires two  MBR M[MAR] bus cycle. MBR AC AC  MBR M[MAR]  MBR Similarly, the RTL for the ADD Similarly, the RTL for the Subt instruction is: instruction is: MAR  X MAR  X MBR  M[MAR] MBR  M[MAR] AC  AC + MBR AC  AC - MBR

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9 44..88 MARIE 44..88 MARIE

The RTL for the Input instruction is: Recall that SKIPCOND skips the next instruction according to the value of the AC. The RTL for the this instruction is the most AC  InReg complex in our instruction set: Similarly, the RTL for the Output If IR[11 - 10] = 00 then instruction is: If AC < 0 then PC  PC + 1 else If IR[11 - 10] = 01 then If AC = 0 then PC  PC + 1 OuReg  AC else If IR[11 - 10] = 10 then If AC > 0 then PC  PC + 1

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44..99 Instruction Processing 44..99 Instruction Processing

The fetch-decode-execute cycle is the series of steps that a compppguter carries out when it runs a program. We first have to fetch an instruction from memory, and place it into the IR. Once in the IR, it is decoded to determine what needs to be done next. If a memory value (operand) is involved in the operation, it is retrieved and placed into the MBR. With everything in place, the instruction is executed.

The next slide shows a flowchart of this process.

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10 44..99 Instruction Processing 44..99 Instruction Processing

Interrupt processing involves adding another step to All computers provide a way of interrupting the fetch-decode-execute cycle as shown below. the fetch -dddecode-execute cycle. Interrupts occur when: A user break (e.,g., Control+C) is issued I/O is requested by the user or a program A critical error occurs Interrupts can be caused by hardware or software. Software interrupts are also called traps or exceptions.

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44..99 Instruction Processing 44..99 Instruction Processing

For general-purpose systems, it is common to disable all interrupts during the time in which an interrupt is being processed. Typically, this is achieved by setting a bit in the flags register. Interrupts that are ignored in this case are called maskable. Nonmaskable interrupts are those interrupts that must be processed in order to keep the system in a stable condition.

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11 44..99 Instruction Processing 44..1010 A Simple Program

Interrupts are very useful in processing I/O. Consider the simple MARIE program given below. We However, interrupt-driven I/O is complicated, and is show a set of mnemonic instructions stored at addresses beyond the scope of our present discussion. 100 - 106 (hex): We will look into this idea in greater detail in Chapter 7. MARIE, being the simplest of simple systems, uses a modified form of programmed I/O. All output is placed in an output register, OutREG, and the CPU polls the input register, InREG, until input is sensed, at which time the value is copied into the accumulator.

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44..1010 A Simple Program 44..1010 A Simple Program

Let’s look at what happens inside the computer Our second instruction is ADD 105: when our ppgrogram runs. This is the LOAD 104 instruction:

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12 44..1010 A Simple Program 44..1111 A Discussion on Assemblers

Our second instruction is store 106: Mnemonic instructions, such as LOAD 104, are easy for humans to write and understand. They are impossible for computers to understand. Assemblers translate instructions that are comprehensible to humans into the machine language that is comprehensible to computers We note the distinction between an assembler and a compiler: In assembly language, there is a one-to-one correspondence between a mnemonic instruction and its machine code. With compilers, this is not usually the case.

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44..1111 A Discussion on Assemblers 44..1111 A Discussion on Assemblers

Assemblers create an object program file Consider our example from mnemonic source code in two passes. program (top). During the first pass, the assembler assembles Note that we have as much of the program as it can, while it builds included two a symbol table that contains memory references directives HEX and for all symbols in the program. DEC that specify the During the second pass, the instructions are radix of the completed using the values from the symbol constants. table. During the first pass, we have a symbol table and the partial instructions shown at the bottom.

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13 44..1111 A Discussion on Assemblers 44..1212 Extending Our Instruction Set After the second pass, So far, all of the MARIE instructions that we the assembly is complete. have discussed use a direct . This means that the address of the operand is explicitly stated in the instruction. It is often useful to employ an indirect addressing, where the address of the address of the operand is given in the instruction. If you have ever used pointers in a program, you are already familiar with indirect addressing.

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44..1212 Extending Our Instruction Set 44..1212 Extending Our Instruction Set

To help you see what happens at the machine level, we have included an indirect addressing mode instruction to the MARIE instruction set. The ADDI instruction specifies the address of the address of the operand. The following RTL tells us what is happening at the register level:

MAR  X MBR  M[MAR] MAR  MBR MBR  M[MAR] AC  AC + MBR

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14 44..1212 Extending Our Instruction Set 44..1212 Extending Our Instruction Set Another helpful programming tool is the use of Our last helpful instruction is the subroutines. The jump-and-store instruction, JNS, gives us limited CLEAR instruction. subroutine functionality. The details of the JNS All it does is set the contents of the instruction are given by the following RTL: accumulator to all zeroes. MBR  PC This is the RTL for CLEAR: MAR  X M[MAR]  MBR Does JNS permit AC  0 MBR  X recursive calls? AC  1 We put our new instructions to work AC  AC + MBR in the program on the following slide. PC  AC

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44..1212 Extending Our Instruction Set

100 | LOAD Addr 10E | SKIPCOND 000 101 | STORE Next 10F | JUMP Loop 102 | LOAD Num 110 | HALT 103 | SUBT One 111 |Addr HEX 117 104 | STORE Ctr 112 |Next HEX 0 105 |Loop LOAD Sum 113 |Num DEC 5 106 | ADDI Next 114 |Sum DEC 0 107 | STORE Sum 115 |Ctr HEX 0 108 | LOAD Next 116 |One DEC 1 109 | ADD One 117 | DEC 10 10A | STORE Next 118 | DEC 15 10B | LOAD Ctr 119 | DEC 2 10C | SUBT One 11A | DEC 25 10D | STORE Ctr 11B | DEC 30

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15 44..1212 Example 4.4.22 –if/else Construct 44..1212 Example 4.4.33 --Subroutine

ORG 100 ORG 100 Load X /Load the first number to be doubled. If, Load X /Load the first value Store Temp /Use Temp as a parameter to pass value to Subr. Subt Y /Subtract the value of Y, store result in AC JSJnS SbSubr /Store the re turn a ddress, an d jump to SbSubr. Skipcond 400 /If AC=0, skip the next instruction Store X /Store the first number, doubled Jump Else /Jump to Else part if AC is not equal to 0 Load Y /Load the second number to be doubled. Then, Load X /Reload X so it can be doubled Store Temp Add X /Double X JnS Subr /Store the return address and jump to the procedure. Store X /Store the new value Loop, Store Y /Store the second number doubled. Jump Endif /Skip over the false, or else, part to end of if Halt /End program. Else, Load Y /Start the else part by loading Y X, DEC 20 Subt X /Subtract X from Y Y, DEC 48 Store Y /Store Y-X in Y Temp, DEC 0 Endif,Halt /Terminate program Subr, HEX 0 / Store return address here. X, Dec 12 /Load the loop control variable Load Temp / Actual subroutine to double numbers. Y, Dec 20 /Subtract one from the loop control variable Add Temp / AC now holds double the value of Temp. END JumpI Subr / Return to calling code. END

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44..1313 A Discussion on Decoding 44..1313 A Discussion on Decoding

A computer’s control unit keeps things Your text provides a complete list of the register synchronized, making sure that bits flow to transfer language for each of MARIE’s instructions. the correct components as the components The microoperations given by each RTL define the are needed. operation of MARIE’s control unit. There are two general ways in which a Each microoperation consists of a distinctive signal control unit can be implemented: hardwired pattern that is interpreted by the control unit and control and microprogrammed control. results in the execution of an instruction. Recall, the RTL for the Add instruction is: With microprogrammed control, a small program is placed into read-only memory in the . MAR  X Hardwired controllers implement this program MBR  M[MAR] using digital logic components. AC  AC + MBR

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16 44..1313 A Discussion on Decoding 44..1313 A Discussion on Decoding

Each of MARIE’s Let us define two sets registers and main of three signals. memory have a unique One set, P0, P1, P2, address along the controls reading from datapath. memory or a register, The addresses take the and the other set form of signals issued consisting of P3, P4, P5, by the control unit controls writing to memory or a register.

How many signal lines does The next slide shows a close MARIE’s control unit need? up view of MARIE’s MBR.

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44..1313 A Discussion on Decoding 44..1313 A Discussion on Decoding Careful inspection of MARIE’s RTL reveals that the ALU has only three operations: add, subtract, and clear. We will also define a fourth “do nothing” state. The entire set of MARIE’s control signals consists of: Register controls: P0 through P5. ALU controls: A0 through A3 Timing: T0 through T7 and counter reset Cr

This register is enabled for reading when P0 and P1 are high, and it is enabled for writing when P3 and P4 are high.

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17 44..1313 A Discussion on Decoding 44..1313 A Discussion on Decoding

Consider MARIE’s Add instruction. It’s RTL is: Here is the complete signal sequence for MAR  X MARIE’ s Add instruction: MBR  M[MAR] P0 P1 P2 P3 T0: MAR  X AC  AC + MBR  After an Add instruction is fetched, the address, X, is P0 P2 T1: MBR M[MAR] in the rightmost 12 bits of the IR, which has a A0 P0 P1 P2 P5 T2: AC  AC + MBR datapath address of 7. Cr T3: [Reset counter] X is copied to the MAR, which has a datapath address These signals are ANDed with of 1. to bring about the Thus we need to raise signals P2, P1, and P0 to read from the IR, and signal P3 to write to the MAR. desired machine behavior. The next slide shows the timing diagram for this instruction..

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44..1313 Decoding 44..1313 A Discussion on Decoding

We note that the signal Notice the ppjattern just described is concurrent siilgnal the same whether our machine used states during each hardwired or machine cycle: C0 microprogrammed control. through C3. In microprogrammed control, the bit pattern P0 P1 P2 P3 T0: MAR  X of an instruction feeds directly into the P0 P2 T1: MBR  M[MAR] combinational logic A0 P0 P1 P2 P5 T2: AC  AC + MBR within the control unit. Cr T3: [Reset counter]

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18 44..77 A Discussion on Decoding

For example, a hardwired control unit for our simple system would need a 4-to-14 decoder to decode the This is the opcode of an hardwired logic for instruction. MARIE’s Add = 0011 instruction. The block diagram at the right, shows a general configuration for a hardwired control unit.

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44..1313 A Discussion on Decoding 44..1313 A Discussion on Decoding

In microprogrammed control, instruction In microprogrammed control, the control store is kept in ROM, PROM, or EPROM , as shown below. midicrocode produces control siilgnal changes. Machine instructions are the input for a microprogram that converts the 1s and 0s of an instruction into control signals. The microprogram is stored in firmware, which is also called the control store. A instruction is retrieved during each clock cycle.

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19 44..1313 A Discussion on Decoding 44..1313 A Discussion on Decoding If MARIE were microprogrammed, the The table below contains MARIE’s microoperation microinstruction format might look like this: codes alonggpg with the corresponding RTL:

MicroOp1 and MicroOp2 contain binary codes for each instructinstructionion. Jump is a single bit indicating that the value in the Dest field is a valid address and should be placed in the .

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44..1313 A Discussion on Decoding 44..1313 A Discussion on Decoding

The first nine lines of MARIE’s microprogram are given The first four lines are the fetch-decode-execute cycle. below ((gusing RTL for clarit y): The remaininggggjp lines are the beginning of a jump table.

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20 44..1313 A Discussion on Decoding 44..88 Real World Architectures

It’s important to remember that a microprogrammed MARIE shares many features with modern control unit works like a system-in-miniature. architectures but it is not an accurate Microinstructions are fetched, decoded, and executed depiction of them. in the same manner as regular instructions. In the following slides, we briefly examine This extra level of instruction interpretation is what two machine architectures. makes microprogrammed control slower than hardwired control. We will look at an Intel architecture, which The advantages of microprogrammed control are that is a CISC machine and MIPS it can support ver y complicated instructions and only ( without Interlocked the microprogram needs to be changed if the Pipeline Stages), which is a RISC machine. instruction set changes (or an error is found). CISC is an acronym for complex instruction set computer. RISC stands for reduced instruction set computer.

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44..88 Real World Architectures 44..88 Real World Architectures The classic Intel architecture, the 8086, The 8086 had four 16-bit general-purpose registers was born in 1979. It is a CISC that could be accessed by the half-word. architecture. It also had a flags register, an instruction register, and a stack accessed through the values in two other It was adopted by IBM for its famed PC, registers, the base pointer and the stack pointer. which was released in 1981. The 8086 had no built in floating-point processing. The 8086 operated on 16-bit data words In 1980, Intel released the 8087 numeric , but few users elected to install them and supported 20-bit memory addresses. because of their cost. Later, to lower costs, the 8-bit 8088 was introddkhduced. Like the 8086, it used 20-bit memory addresses.

What was the largest memory that the 8086 could address?

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21 44..88 Real World Architectures 44..88 Real World Architectures

In 1985, Intel introduced the 32-bit 80386. Currently, Intel’s most advanced 32-bit It also had no built-in floating-point unit. microprocessor is the Pentium 4. The 80486, introduced in 1989, was an It can run as fast as 3.06 GHz. This clock 80386 that had built-in floating-point rate is over 350 times faster than that of processing and memory. the 8086. The 80386 and 80486 offered downward compatibility with the 8086 and 8088. Speed enhancing features include multilevel cache and . Software written for the smaller word systems was directed to use the lower 16 Intelll, along wit h many ot hers, is marrying bits of the 32-bit registers. many of the ideas of RISC architectures with that are largely CISC.

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44..88 Real World Architectures 44..88 Real World Architectures The MIPS family of CPUs has been one of MIPS was one of the first RISC microprocessors. the most successful in its class. The original MIPS architecture had only 55 different instructions, as compared with the 8086 which had In 1986 the first MIPS CPU was announced. over 100. It had a 32-bit word size and could address MIPS was designed with performance in mind: It is a 4GB of memory. load/store architecture, meaning that only the load and store instructions can access memory. Over the years, MIPS processors have been The large number of registers in the MIPS architecture used in general purpose computers as well keeps bus traffic to a minimum. as in games. The MIPS architecture now offers 32- and 64-bit versions. How does this design affect performance?

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The major components of a computer Computers run programs through iterative system are its control unit, registers, fetch-decode-execute cycles. memory, ALU, and data path. Computers can run programs that are in A built-in clock keeps everything machine language. synchronized. An assembler converts mnemonic code to Control units can be microprogrammed or machine language. hardwired. The Intel architecture is an example of a Hardddwired contro l units give better CSCCISC arc hitecture; MIPS is an exampl e of a performance, while microprogrammed units RISC architecture. are more adaptable to changes.

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