DOCSLIB.ORG

Lecture 12: TOY Machine Architecture TOY Machine

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Lecture 12: TOY Machine Architecture TOY Machine The TOY Machine Lecture 12: TOY Machine Architecture TOY machine. ! 256 16-bit words of memory. ! 16 16-bit registers. ! 1 8-bit program counter. 8 16 ! 16 instructions types. pc for branch, addr for loads, result of arithmetic, logic, jump stores or addr for load addr Cond = 0 What we've done. Eval Registers Fetch 0 > 0 ! Written programs for the TOY machine. pc for jal 8 W Data load ! Software implementation of fetch-execute cycle. 2 Memory A Data A IR L – TOY simulator. PC Addr op U B Data d W Addr 5 R Execute A Addr Our goal today. Data s 16 ! + W Data t B Addr Hardware implementation of fetch-execute cycle. 1 W – TOY computer. W 0 addr 8 pc + 1 8 store data COS126: General Computer Science • http://www.cs.Princeton.EDU/~cos126 2 Designing a Processor Instruction Set Architecture How to build a microprocessor? Instruction set architecture (ISA). ! 16-bit words, 256 words of memory, 16 registers. ! Develop instruction set architecture (ISA). ! Determine set of primitive instructions. – 16-bit words, 16 TOY machine instructions – too narrow ! cumbersome to program – too broad ! cumbersome to build hardware ! Determine major components. ! TOY machine: 16 instructions. – ALU, memory, registers, program counter Instructions Instructions ! Determine datapath requirements. 0: halt 8: load – "flow" of bits 1: add 9: store 2: subtract A: load indirect ! Establish clocking methodology. 3: and B: store indirect – 2-cycle design: fetch, execute 4: xor C: branch zero 5: shift left D: branch positive ! Analyze how to implement each instruction. – determine settings of control signals 6: shift right E: jump register 7: load address F: jump and link 3 4 Designing a Processor Arithmetic Logic Unit How to build a microprocessor? TOY ALU. ! Big combinational circuit. technical hack ! Develop instruction set architecture (ISA). ! 16-bit bus. – 16-bit words, 16 TOY machine instructions ! Add, subtract, and, xor, shift left, shift right, copy input 2. ! Determine major components. – ALU, memory, registers, program counter 16 Input 1 op 2 1 0 ! Determine datapath requirements. +, - 0 0 0 – "flow" of bits ALU 16 & 0 0 1 ^ 0 1 0 ! Establish clocking methodology. <<, >> 0 1 1 16 – 2-cycle design: fetch, execute input 2 1 0 0 Input 2 3 ALU select ! Analyze how to implement each instruction. – determine settings of control signals shift subtract direction 5 6 Arithmetic Logic Unit: Implementation Main Memory 16 TOY main memory: 256 x 16-bit register file. Input 1 + 000 16 00 10 20 30 40 50 60 70 80 90 A0 B0 C0 D0 E0 F0 Input 2 01 11 21 31 41 51 61 71 81 91 A1 B1 C1 D1 E1 F1 ~ carry in 02 12 22 32 42 52 62 72 82 92 A2 B2 C2 D2 E2 F2 03 13 23 33 43 53 63 73 83 93 A3 B3 C3 D3 E3 F3 04 14 24 34 44 54 64 74 84 94 A4 B4 C4 D4 E4 F4 & 001 05 15 25 35 45 55 65 75 85 95 A5 B5 C5 D5 E5 F5 06 16 26 36 46 56 66 76 86 96 A6 B6 C6 D6 E6 F6 16 16 16 07 17 27 37 47 57 67 77 87 97 A7 B7 C7 D7 E7 F7 MUX 08 18 28 38 48 58 68 78 88 98 A8 B8 C8 D8 E8 F8 Read ^ 010 Write 09 19 29 39 49 59 69 79 89 99 A9 B9 C9 D9 E9 F9 Data Data 0A 1A 2A 3A 4A 5A 6A 7A 8A 9A AA BA CA DA EA FA 0B 1B 2B 3B 4B 5B 6B 7B 8B 9B AB BB CB DB EB FB << 0C 1C 2C 3C 4C 5C 6C 7C 8C 9C AC BC CC DC EC FC 011 >> 0D 1D 2D 3D 4D 5D 6D 7D 8D 9D AD BD CD DD ED FD op 2 1 0 0E 1E 2E 3E 4E 5E 6E 7E 8E 9E AE BE CE DE EE FE +, - 0 0 0 100 0F 1F 2F 3F 4F 5F 6F 7F 8F 9F AF BF CF DF EF FF 3 & 0 0 1 ^ 0 1 0 <<, >> 0 1 1 8 input 2 1 0 0 subtract shift direction ALU control Cl Write Address 7 8 Registers Designing a Processor TOY registers: fancy 16 x 16-bit register file. How to build a microprocessor? ! Want to be able to read two registers, and write to a third in the same instructions: R1 " R2 + R3. ! Develop instruction set architecture (ISA). ! 3 address inputs, 1 data input, 2 data outputs. – 16-bit words, 16 TOY machine instructions ! Add decoders and muxes for additional ports. ! Determine major components. – ALU, memory, registers, program counter 16 R0 R8 Write Data R1 R9 ! Determine datapath requirements. 16 4 R2 RA – "flow" of bits A Data Write Address R3 RB 16 R4 RC ! Establish clocking methodology. 4 B Data A Address R5 RD – 2-cycle design: fetch, execute 4 R6 RE B Address R7 RF ! Analyze how to implement each instruction. – determine settings of control signals Cl Write 9 10 Datapath and Control Datapath and Control Datapath. Datapath. ! Layout and interconnection of components. ! Layout and interconnection of components. ! Must accommodate all instruction types. ! Must accommodate all instruction types. Control. Control. ! Choreographs the "flow" of information on the datapath. ! Choreographs the "flow" of information on the datapath. ! Depending on instruction, different control wires are turned on. ! Depending on instruction, different control wires are turned on. 8 datapath wires 8 datapath wires Result of jump 5E PC Result of jump 5E PC 1 8 1 8 or branch 5E or branch 11 MUX MUX 8 8 Result of adding 1 to 11 Result of adding 1 to 11 0 0 old PC old PC control wire control wire 1 0 11 12 The TOY Datapath The TOY Datapath: Add 8 16 pc for branch, addr for result of arithmetic, logic, jump loads, stores or addr for load addr Cond = 0 Eval Registers 0 > 0 8 pc for jal W Data load 201 ?1?23?4? 2 Memory A Data A Memory IR IR L 20 Addr 20 Addr 1 PC op U PC op B Data 2 d W Addr 5 21 21 d R Data R Data 3 s A Addr 1234 s 16 21 4 + W Data t B Addr + W Data t 1 W 1 W 0 W 8 addr pc + 1 8 store data Before fetch: After fetch: pc = 20, mem[20] = 1234 pc = 21 IR = 1234: R[2] " R[3] + R[4] 15 16 The TOY Datapath: Add The TOY Datapath: Jump and Link 008C Cond = 0 Cond = 0 Eval Eval Registers Registers 008C > 0 > 0 W Data W Data 21 1234 20 ???? 2 0028 2 Memory A Data A Memory A Data A IR 008C IR L L Addr 1 0064 Addr PC op U PC op U 2 B Data B Data d W Addr 5 d W Addr 35 R Data 3 R Data s A Addr s A Addr 4 + W Data t B Addr + W Data t B Addr 1 W 1 W W W Before execute: After execute: pc = 21 pc = 21 Before fetch: IR = 1234: R[2] " R[3] + R[4] R[2] = 008C pc = 20 R[3] = 0028, R[4] = 0064 mem[20] = FF30 17 18 The TOY Datapath: Jump and Link The TOY Datapath: Jump and Link Cond = 0 Cond = 0 Eval Eval Registers Registers > 0 > 0 W Data W Data 201 ?F?F?30? 21 FF30 2 2 Memory A Data A Memory A Data A 20 IR IR F L F L 20 Addr 21 Addr PC op U PC op U F B Data F B Data 21 21 d W Addr 35 d W Addr 35 R Data 3 R Data 3 FF30 s A Addr s A Addr 21 0 0 + W Data t B Addr + W Data t B Addr 1 W 1 W W W 30 Before fetch: After fetch: Before execute: pc = 20 pc = 21 pc = 21 mem[20] = FF30 IR = FF30: R[F] " 21; pc " 30 IR = FF30: R[F] " 21; pc " 30 19 20 The TOY Datapath: Jump and Link Do Try This At Home 0030 8 16 pc for branch, addr for result of arithmetic, logic, jump loads, stores or addr for load addr Cond = 0 Cond = 0 Eval Eval Registers Registers > 0 0 > 0 8 21 21 pc for jal W Data W Data 2310 FF30 load 2 2 Memory A Data A Memory A Data A 30 IR IR F L L 21 Addr Addr PC op U PC op U F B Data B Data d W Addr 35 d W Addr 5 R Data 3 R Data s A Addr s A Addr 0 16 + W Data t B Addr + W Data t B Addr 1 W 1 W W W 0 8 addr 30 pc + 1 8 store data Before execute: After execute: pc = 21 pc = 30 Trace the flow of some other instructions through the datapath picture. IR = FF30: R[F] " 21; pc " 30 R[F] = 21 21 22 Designing a Processor Clocking Methodology How to build a microprocessor? Two cycle design (fetch and execute). ! Use 1-bit counter to distinguish between 2 cycles. ! Develop instruction set architecture (ISA). ! Use two cycles since fetch and execute phases each access memory – 16-bit words, 16 TOY machine instructions and alter program counter. ! Determine major components. 1-bit – ALU, memory, registers, program counter counter Execute Clock Q Cl Execute ! Determine datapath requirements.
Load more

Recommended publications
  • 18-447 Computer Architecture Lecture 6: Multi-Cycle and Microprogrammed Microarchitectures
    18-447 Computer Architecture Lecture 6: Multi-Cycle and Microprogrammed Microarchitectures Prof. Onur Mutlu Carnegie Mellon University Spring 2015, 1/28/2015 Agenda for Today & Next Few Lectures n Single-cycle Microarchitectures n Multi-cycle and Microprogrammed Microarchitectures n Pipelining n Issues in Pipelining: Control & Data Dependence Handling, State Maintenance and Recovery, … n Out-of-Order Execution n Issues in OoO Execution: Load-Store Handling, … 2 Reminder on Assignments n Lab 2 due next Friday (Feb 6) q Start early! n HW 1 due today n HW 2 out n Remember that all is for your benefit q Homeworks, especially so q All assignments can take time, but the goal is for you to learn very well 3 Lab 1 Grades 25 20 15 10 5 Number of Students 0 30 40 50 60 70 80 90 100 n Mean: 88.0 n Median: 96.0 n Standard Deviation: 16.9 4 Extra Credit for Lab Assignment 2 n Complete your normal (single-cycle) implementation first, and get it checked off in lab. n Then, implement the MIPS core using a microcoded approach similar to what we will discuss in class. n We are not specifying any particular details of the microcode format or the microarchitecture; you can be creative. n For the extra credit, the microcoded implementation should execute the same programs that your ordinary implementation does, and you should demo it by the normal lab deadline. n You will get maximum 4% of course grade n Document what you have done and demonstrate well 5 Readings for Today n P&P, Revised Appendix C q Microarchitecture of the LC-3b q Appendix A (LC-3b ISA) will be useful in following this n P&H, Appendix D q Mapping Control to Hardware n Optional q Maurice Wilkes, “The Best Way to Design an Automatic Calculating Machine,” Manchester Univ.
    [Show full text]
  • A 4.7 Million-Transistor CISC Microprocessor
    Auriga2: A 4.7 Million-Transistor CISC Microprocessor J.P. Tual, M. Thill, C. Bernard, H.N. Nguyen F. Mottini, M. Moreau, P. Vallet Hardware Development Paris & Angers BULL S.A. 78340 Les Clayes-sous-Bois, FRANCE Tel: (+33)-1-30-80-7304 Fax: (+33)-1-30-80-7163 Mail: [email protected] Abstract- With the introduction of the high range version of parallel multi-processor architecture. It is used in a family of the DPS7000 mainframe family, Bull is providing a processor systems able to handle up to 24 such microprocessors, which integrates the DPS7000 CPU and first level of cache on capable to support 10 000 simultaneously connected users. one VLSI chip containing 4.7M transistors and using a 0.5 For the development of this complex circuit, a system level µm, 3Mlayers CMOS technology. This enhanced CPU has design methodology has been put in place, putting high been designed to provide a high integration, high performance emphasis on high-level verification issues. A lot of home- and low cost systems. Up to 24 such processors can be made CAD tools were developed, to meet the stringent integrated in a single system, enabling performance levels in performance/area constraints. In particular, an integrated the range of 850 TPC-A (Oracle) with about 12 000 Logic Synthesis and Formal Verification environment tool simultaneously active connections. The design methodology has been developed, to deal with complex circuitry issues involved massive use of formal verification and symbolic and to enable the designer to shorten the iteration loop layout techniques, enabling to reach first pass right silicon on between logical design and physical implementation of the several foundries.
    [Show full text]
  • Embedded Multi-Core Processing for Networking
    12 Embedded Multi-Core Processing for Networking Theofanis Orphanoudakis University of Peloponnese Tripoli, Greece [email protected] Stylianos Perissakis Intracom Telecom Athens, Greece [email protected] CONTENTS 12.1 Introduction ............................ 400 12.2 Overview of Proposed NPU Architectures ............ 403 12.2.1 Multi-Core Embedded Systems for Multi-Service Broadband Access and Multimedia Home Networks . 403 12.2.2 SoC Integration of Network Components and Examples of Commercial Access NPUs .............. 405 12.2.3 NPU Architectures for Core Network Nodes and High-Speed Networking and Switching ......... 407 12.3 Programmable Packet Processing Engines ............ 412 12.3.1 Parallelism ........................ 413 12.3.2 Multi-Threading Support ................ 418 12.3.3 Specialized Instruction Set Architectures ....... 421 12.4 Address Lookup and Packet Classification Engines ....... 422 12.4.1 Classification Techniques ................ 424 12.4.1.1 Trie-based Algorithms ............ 425 12.4.1.2 Hierarchical Intelligent Cuttings (HiCuts) . 425 12.4.2 Case Studies ....................... 426 12.5 Packet Buffering and Queue Management Engines ....... 431 399 400 Multi-Core Embedded Systems 12.5.1 Performance Issues ................... 433 12.5.1.1 External DRAMMemory Bottlenecks ... 433 12.5.1.2 Evaluation of Queue Management Functions: INTEL IXP1200 Case ................. 434 12.5.2 Design of Specialized Core for Implementation of Queue Management in Hardware ................ 435 12.5.2.1 Optimization Techniques .......... 439 12.5.2.2 Performance Evaluation of Hardware Queue Management Engine ............. 440 12.6 Scheduling Engines ......................... 442 12.6.1 Data Structures in Scheduling Architectures ..... 443 12.6.2 Task Scheduling ..................... 444 12.6.2.1 Load Balancing ................ 445 12.6.3 Traffic Scheduling ...................
    [Show full text]
  • Introduction to Microcoded Implementation of a CPU Architecture
    Introduction to Microcoded Implementation of a CPU Architecture N.S. Matloff, revised by D. Franklin January 30, 1999, revised March 2004 1 Microcoding Throughout the years, Microcoding has changed dramatically. The debate over simple computers vs complex computers once raged within the architecture community. In the end, the most popular microcoded computers survived for three reasons - marketshare, technological improvements, and the embracing of the principles used in simple computers. So the two eventually merged into one. To truly understand microcoding, one must understand why they were built, what they are, why they survived, and, finally, what they look like today. 1.1 Motivation Strictly speaking, the term architecture for a CPU refers only to \what the assembly language programmer" sees|the instruction set, addressing modes, and register set. For a given target architecture, i.e. the architecture we wish to build, various implementations are possible. We could have many different internal designs of the CPU chip, all of which produced the same effect, namely the same instruction set, addressing modes, etc. The different internal designs could then all be produced for the different models of that CPU, as in the familiar Intel case. The different models would have different speed capabilities, and probably different prices to the consumer. But the same machine languge program, say a .EXE file in the Intel/DOS case, would run on any CPU in the family. When desigining an instruction set architecture, there is a tradeoff between software and hardware. If you provide very few instructions, it takes more instructions to perform the same task, but the hardware can be very simple.
    [Show full text]
  • A Characterization of Processor Performance in the VAX-1 L/780
    A Characterization of Processor Performance in the VAX-1 l/780 Joel S. Emer Douglas W. Clark Digital Equipment Corp. Digital Equipment Corp. 77 Reed Road 295 Foster Street Hudson, MA 01749 Littleton, MA 01460 ABSTRACT effect of many architectural and implementation features. This paper reports the results of a study of VAX- llR80 processor performance using a novel hardware Prior related work includes studies of opcode monitoring technique. A micro-PC histogram frequency and other features of instruction- monitor was buiit for these measurements. It kee s a processing [lo. 11,15,161; some studies report timing count of the number of microcode cycles execute z( at Information as well [l, 4,121. each microcode location. Measurement ex eriments were performed on live timesharing wor i loads as After describing our methods and workloads in well as on synthetic workloads of several types. The Section 2, we will re ort the frequencies of various histogram counts allow the calculation of the processor events in 5 ections 3 and 4. Section 5 frequency of various architectural events, such as the resents the complete, detailed timing results, and frequency of different types of opcodes and operand !!Iection 6 concludes the paper. specifiers, as well as the frequency of some im lementation-s ecific events, such as translation bu h er misses. ?phe measurement technique also yields the amount of processing time spent, in various 2. DEFINITIONS AND METHODS activities, such as ordinary microcode computation, memory management, and processor stalls of 2.1 VAX-l l/780 Structure different kinds. This paper reports in detail the amount of time the “average’ VAX instruction The llf780 processor is composed of two major spends in these activities.
    [Show full text]
  • Digital and System Design
    Digital System Design — Use of Microcontroller RIVER PUBLISHERS SERIES IN SIGNAL, IMAGE & SPEECH PROCESSING Volume 2 Consulting Series Editors Prof. Shinsuke Hara Osaka City University Japan The Field of Interest are the theory and application of filtering, coding, trans- mitting, estimating, detecting, analyzing, recognizing, synthesizing, record- ing, and reproducing signals by digital or analog devices or techniques. The term “signal” includes audio, video, speech, image, communication, geophys- ical, sonar, radar, medical, musical, and other signals. • Signal Processing • Image Processing • Speech Processing For a list of other books in this series, see final page. Digital System Design — Use of Microcontroller Dawoud Shenouda Dawoud R. Peplow University of Kwa-Zulu Natal Aalborg Published, sold and distributed by: River Publishers PO box 1657 Algade 42 9000 Aalborg Denmark Tel.: +4536953197 EISBN: 978-87-93102-29-3 ISBN:978-87-92329-40-0 © 2010 River Publishers All rights reserved. No part of this publication may be reproduced, stored in a retrieval system, or transmitted in any form or by any means, mechanical, photocopying, recording or otherwise, without prior written permission of the publishers. Dedication To Nadia, Dalia, Dina and Peter D.S.D To Eleanor and Caitlin R.P. v This page intentionally left blank Preface Electronic circuit design is not a new activity; there have always been good designers who create good electronic circuits. For a long time, designers used discrete components to build first analogue and then digital systems. The main components for many years were: resistors, capacitors, inductors, transistors and so on. The primary concern of the designer was functionality however, once functionality has been met, the designer’s goal is then to enhance per- formance.
    [Show full text]
  • Exploiting Coarse-Grained Parallelism to Accelerate Protein Motif Finding with a Network Processor
    Exploiting Coarse-Grained Parallelism to Accelerate Protein Motif Finding with a Network Processor Ben Wun, Jeremy Buhler, and Patrick Crowley Department of Computer Science and Engineering Washington University in St.Louis {bw6,jbuhler,pcrowley}@cse.wustl.edu Abstract The first generation of general-purpose CMPs is expected to employ a small number of sophisticated, While general-purpose processors have only recently employed superscalar CPU cores; by contrast, NPs contain many, chip multiprocessor (CMP) architectures, network processors much simpler single-issue cores. Desktop and server (NPs) have used heterogeneous multi-core architectures since processors focus on maximizing instruction-level the late 1990s. NPs differ qualitatively from workstation and parallelism (ILP) and minimizing latency to memory, server CMPs in that they replicate many simple, highly efficient while NPs are designed to exploit coarse-grained processor cores on a chip, rather than a small number of parallelism and maximize throughput. NPs are designed sophisticated superscalar CPUs. In this paper, we compare the to maximize performance and efficiency on packet performance of one such NP, the Intel IXP 2850, to that of the processing workloads; however, we believe that many Intel Pentium 4 when executing a scientific computing workload with a high degree of thread-level parallelism. Our target other workloads, in particular tasks drawn from scientific program, HMMer, is a bioinformatics tool that identifies computing, are better suited to NP-style CMPs than to conserved motifs in protein sequences. HMMer represents CMPs based on superscalar cores. motifs as hidden Markov models (HMMs) and spends most of its In this work, we study a representative scientific time executing the well-known Viterbi algorithm to align workload drawn from bioinformatics: the HMMer proteins to these models.
    [Show full text]
  • The Implementation of Prolog Via VAX 8600 Microcode ABSTRACT
    The Implementation of Prolog via VAX 8600 Microcode Jeff Gee,Stephen W. Melvin, Yale N. Patt Computer Science Division University of California Berkeley, CA 94720 ABSTRACT VAX 8600 is a 32 bit computer designed with ECL macrocell arrays. Figure 1 shows a simplified block diagram of the 8600. We have implemented a high performance Prolog engine by The cycle time of the 8600 is 80 nanoseconds. directly executing in microcode the constructs of Warren’s Abstract Machine. The imulemention vehicle is the VAX 8600 computer. The VAX 8600 is a general purpose processor Vimal Address containing 8K words of writable control store. In our system, I each of the Warren Abstract Machine instructions is implemented as a VAX 8600 machine level instruction. Other Prolog built-ins are either implemented directly in microcode or executed by the general VAX instruction set. Initial results indicate that. our system is the fastest implementation of Prolog on a commercrally available general purpose processor. 1. Introduction Various models of execution have been investigated to attain the high performance execution of Prolog programs. Usually, Figure 1. Simplified Block Diagram of the VAX 8600 this involves compiling the Prolog program first into an intermediate form referred to as the Warren Abstract Machine (WAM) instruction set [l]. Execution of WAM instructions often follow one of two methods: they are executed directly by a The 8600 consists of six subprocessors: the EBOX. IBOX, special purpose processor, or they are software emulated via the FBOX. MBOX, Console. and UO adamer. Each of the seuarate machine language of a general purpose computer.
    [Show full text]
  • CHAPTER 4 MARIE: an Introduction to a Simple Computer
    CHAPTER 4 MARIE: An Introduction to a Simple Computer 4.1 Introduction 219 4.2 CPU Basics and Organization 219 4.2.1 The Registers 220 4.2.2 The ALU 221 4.2.3 The Control Unit 221 4.3 The Bus 221 4.4 Clocks 225 4.5 The Input/Output Subsystem 227 4.6 Memory Organization and Addressing 227 4.7 Interrupts 235 4.8 MARIE 236 4.8.1 The Architecture 236 4.8.2 Registers and Buses 236 4.8.3 Instruction Set Architecture 238 4.8.4 Register Transfer Notation 242 4.9 Instruction Processing 244 4.9.1 The Fetch–Decode–Execute Cycle 244 4.9.2 Interrupts and the Instruction Cycle 246 4.9.3 MARIE’s I/O 249 4.10 A Simple Program 249 4.11 A Discussion on Assemblers 252 4.11.1 What Do Assemblers Do? 252 4.11.2 Why Use Assembly Language? 254 4.12 Extending Our Instruction Set 255 4.13 A Discussion on Decoding: Hardwired Versus Microprogrammed Control 262 4.13.1 Machine Control 262 4.13.2 Hardwired Control 265 4.13.3 Microprogrammed Control 270 4.14 Real-World Examples of Computer Architectures 274 4.14.1 Intel Architectures 275 4.14.2 MIPS Architectures 282 Chapter Summary 284 CMPS375 Class Notes (Chap04) Page 1 / 27 Dr. Kuo-pao Yang 4.1 Introduction 219 • In this chapter, we first look at a very simple computer called MARIE: A Machine Architecture that is Really Intuitive and Easy. • We then provide brief overviews of Intel and MIPS machines, two popular architectures reflecting the CISC (Complex Instruction Set Computer) and RISC (Reduced Instruction Set Computer) design philosophies.
    [Show full text]
  • Vhdl Projects to Reinforce Computer Architecture Classroom Instruction
    AC 2007-372: VHDL PROJECTS TO REINFORCE COMPUTER ARCHITECTURE CLASSROOM INSTRUCTION Ronald Hayne, The Citadel Ronald J. Hayne, PhD, is an Assistant Professor in the Department of Electrical and Computer Engineering at The Citadel. His professional areas of interest are digital systems and hardware description languages. He is a retired Army officer with experience in academics and Defense laboratories. Page 12.1588.1 Page © American Society for Engineering Education, 2007 VHDL Projects to Reinforce Computer Architecture Classroom Instruction Abstract Exploration of various computer architecture constructs needs reinforcement beyond pencil and paper homework problems. Unfortunately, laboratory exercises based on microprocessor trainers are limited to a single architecture and a resolution of single assembly language instructions. A hardware description language, such as VHDL, can be used to provide simulation-based application of the classroom instruction regardless of the course text. Models of computer components such as registers, memory, and ALUs can be readily defined to match textbook examples and then combined to demonstrate multiple architectural concepts. Students with basic knowledge of VHDL from their prerequisite digital logic course are able to modify and use these models to simulate computer behavior at the register transfer level with data and control signal visibility at each clock cycle. A program of instruction has been developed that uses VHDL homework exercises and a capstone design project to provide hands-on application of course concepts using modern design tools. Exercises include addressing modes, microprogrammed control, and computer arithmetic. The design project models a multi-bus architecture and hardwired control unit from the text to implement a basic instruction set.
    [Show full text]
  • Brief History of Microprogramming
    Microprogramming History -- Mark Smotherman A Brief History of Microprogramming Mark Smotherman Last updated: October 2012 Summary: Microprogramming is a technique to implement the control logic necessary to execute instructions within a processor. It relies on fetching low-level microinstructions from a control store and deriving the appropriate control signals as well as microprogram sequencing information from each microinstruction. Definitions and Example Although loose usage has sometimes equated the term "microprogramming" with the idea of "programming a microcomputer", this is not the standard definition. Rather, microprogramming is a systematic technique for implementing the control logic of a computer's central processing unit. It is a form of stored-program logic that substitutes for hardwired control circuitry. The central processing unit in a computer system is composed of a data path and a control unit. The data path includes registers, function units such as shifters and ALUs (arithmetic and logic units), internal processor busses and paths, and interface units for main memory and I/O busses. The control unit governs the series of steps taken by the data path during the execution of a user- visible instruction, or macroinstruction (e.g., load, add, store). Each action of the datapath is called a register transfer and involves the transfer of information within the data path, possibly including the transformation of data, address, or instruction bits by the function units. A register transfer is accomplished by gating out (sending) register contents onto internal processor busses, selecting the operation of ALUs, shifters, etc., through which that information might pass, and gating in (receiving) new values for one or more registers.
    [Show full text]
  • The Design of a Reduced Instruction Set Computer Using a Silicon Compiler
    AN ABSTRACT OF THE THESIS OF Licheng Zhang for the degree of Master of Science in Electrical and Computer Engineering presented on June 7, 1989. Title: The Design of A Reduced Instruction Set Computer UsingA Silicon Compiler. Redacted for Privacy Abstract appro ed- John Muff The objective of this thesisisto describe the design and implementation of a VSLI reduced instruction set computer(RISC). The RISC machine constitutes a new style of computerarchitecture. Itdifferssignificantly from the complex instructionset computer architectures(CISC)ofthepast.RISCarchitecturesare characterized by their high performance, simple instructionsets, minimal hardware requirements, and their abilityto support block structured programming languages adequately. In this thesis a 16-bit single chip RISC was designed using the Genesil Silicon Compiler. It has 14 instructions, anoverlapped register window structure,and on chip memory.Itcan execute most instructions in a single clock cycle,including procedure calls and returns. The peak performance of this chip is approximately6 MIPS. The chip was implemented in 2 micron CMOS technology. The chip sizeis 516.54 X 514.27 mils. This chip has not been fabricated. THE DESIGN OF A REDUCED INSTRUCTION SET COMPUTER USING A SILICON COMPLIER By Licheng Zhang A THESIS submittedto Oregon State University in partial fulfillment of the requirement for the degree of Master of Science Completed June 7, 1989 Commencement June,1990. APPROVED: Redacted for Privacy ssor of Electrical and Comp ter gineering in charge of major Redacted for Privacy Head of Department of Electrical and Computer Engineering Redacted for Privacy Dean of Gradua eSchool Date thesis is presented: June 7, 1989. TABLE OF CONTENTS 1.
    [Show full text]