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CHAPTER 4 MARIE: an Introduction to a Simple Computer

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CHAPTER 4 MARIE: an Introduction to a Simple Computer CHAPTER 4 MARIE: An Introduction to a Simple Computer 4.1 Introduction 215 4.2 CPU Basics and Organization 215 4.2.1 The Registers 216 4.2.2 The ALU 217 4.2.3 The Control Unit 217 4.3 The Bus 217 4.4 Clocks 221 4.5 The Input/Output Subsystem 223 4.6 Memory Organization and Addressing 224 4.7 Interrupts 230 4.8 MARIE 231 4.8.1 The Architecture 231 4.8.2 Registers and Buses 232 4.8.3 The Instruction Set Architecture 233 4.8.4 Register Transfer Notation 236 4.9 Instruction Processing 239 4.9.1 The Fetch-Decode-Execute Cycle 239 4.9.2 Interrupts and the Instruction Cycle 241 4.9.3 MARIE’s I/O 242 4.10 A Simple Program 244 4.11 A Discussion on Assemblers 246 4.11.1 What Do Assemblers Do? 246 4.11.2 Why Use Assembly Language? 248 4.12 Extending Our Instruction Set 249 4.13 A Discussion on Decoding: Hardwired vs. Microprogrammed Control 255 4.13.1 Machine Control 256 4.13.2 Hardwired Control 259 4.13.3 Microprogrammed Control 262 4.14 Real-World Examples of Computer Architectures 267 4.14.1 Intel Architectures 269 4.14.2 MIPS Architectures 274 Chapter Summary 277 CMPS375 Class Notes (Chap04) Page 1 / 27 Dr. Kuo-pao Yang 4.1 Introduction 215 In this chapter, we first look at a very simple computer called MARIE: A Machine Architecture that is Really Intuitive and Easy. We then provide brief overviews of Intel and MIPS machines, two popular architectures reflecting the CISC (Complex Instruction Set Computer) and RISC (Reduced Instruction Set Computer) design philosophies. The objective of this chapter is to give you an understanding of how a computer functions. 4.2 CPU Basics and Organization 215 The Central processing unit (CPU) is responsible for fetching program instructions, decoding each instruction that is fetched, and executing the indicated sequence of operations on the correct data. All computers have a CPU that can be divide into two pieces: datapath and the control unit. The datapath consists of an arithmetic-logic unit (ALU) and storage units (registers) that are interconnected by a data bus that is also connected to main memory. Check page 29 Figure 1.4. Various CPU components perform sequenced operations according to signals provided by its control unit. FIGURE 1.4 The von Neumann Architecture CMPS375 Class Notes (Chap04) Page 2 / 27 Dr. Kuo-pao Yang 4.2.1 The Registers 216 Registers hold data that can be readily accessed by the CPU. They can be implemented using D flip-flops. A 32-bit register requires 32 D flip-flops. 4.2.2 The ALU 217 The arithmetic-logic unit (ALU) carries out logical operations (such as comparisons) and arithmetic operations (such as add or multiply) directed by the control unit. 4.2.3 The Control Unit 217 The control unit determines which actions to carry out according to the values in a program counter register and a status register. CMPS375 Class Notes (Chap04) Page 3 / 27 Dr. Kuo-pao Yang 4.3 The Bus 217 The CPU shares data with other system components by way of a data bus. A bus is a set of wires that simultaneously convey a single bit along each line. Two types of buses are commonly found in computer systems: point-to-point, and multipoint buses. FIGURE 4.1 (a) Point-to-Point Buses; (b) Multipoint Buses At any one time, only one device (be it a register, the ALU, memory, or some other component) may use the bus. However, the sharing often results in a communications bottleneck. Master device is one that initiates actions and a slave responds to requests by a master. CMPS375 Class Notes (Chap04) Page 4 / 27 Dr. Kuo-pao Yang Buses consist of data lines, control lines, and address lines. While the data lines convey bits from one device to another, control lines determine the direction of data flow, and when each device can access the bus. Address lines determine the location of the source or destination of the data. FIGURE 4.2 The Components of a Typical Bus In a master-slave configuration, where more than one device can be the bus master, concurrent bus master requests must be arbitrated. Four categories of bus arbitration are: o Daisy chain n arbitration: Permissions are passed from the highest priority device to the lowest. o Centralized parallel arbitration: Each device is directly connected to an arbitration circuit, and a centralized arbiter selects who gets the bus. o Distributed arbitration using self-detection: Devices decide which gets the bus among themselves. o Distributed arbitration using collision-detection: Any device can try to use the bus. If its data collides with the data of another device, the device tries again (Ethernet uses this type arbitration). CMPS375 Class Notes (Chap04) Page 5 / 27 Dr. Kuo-pao Yang 4.4 Clocks 221 Every computer contains at least one clock that synchronizes the activities of its components. A fixed number of clock cycles are required to carry out each data movement or computational operation. The clock frequency, measured in megahertz or gigahertz, determines the speed with which all operations are carried out. Clock cycle time is the reciprocal of clock frequency. o An 800 MHz clock has a cycle time of 1.25 ns. The minimum clock cycle time must be at least as great as the maximum propagation delay of the circuit. The CPU time required to run a program is given by the general performance equation: We see that we can improve CPU throughput when we reduce the number of instructions in a program, reduce the number of cycles per instruction, or reduce the number of nanoseconds per clock cycle. In general, multiplication requires more time than addition, floating point operations require more cycles than integer ones, and accessing memory takes longer than accessing registers. Bus clocks are usually slower than CPU clocks, causing bottleneck problems. CMPS375 Class Notes (Chap04) Page 6 / 27 Dr. Kuo-pao Yang 4.5 The Input/Output Subsystem 223 I/O devices allow us to communicate with the computer system. A computer communicates with the outside world through its input/output (I/O) subsystem. I/O is the transfer of data between primary memory and various I/O peripherals. I/O devices are not connected directly to the CPU. I/O devices connect to the CPU through various interfaces. The CPU communicates to these external devices via input/output registers. This exchange of data is performed in two ways: o In memory-mapped I/O, the registers in the interface appear in the computer’s memory and there is no real difference accessing memory and accessing an I/O device. It uses up memory space in the system. o With instruction-based I/O, the CPU has specialized instructions that input and output. Although this does not use memory space, it requires specific I/O instructions. Interrupts play a very important part in I/O, because they are an efficient way to notify CPU that input or output is available for use. CMPS375 Class Notes (Chap04) Page 7 / 27 Dr. Kuo-pao Yang 4.6 Memory Organization and Addressing 224 You can envision memory as a matrix of bits. Each row, implemented by a register, has a length typically equivalent to the word size of machine. Each register (more commonly referred to as a memory location) has a unique address; memory addresses usually start at zero and progress upward. FIGURE 4.4 (a) N 8-Bit Memory Locations; (b) M 16-Bit Memory Locations Normally, memory is byte-addressable, which means that each individual byte has a unique address. For example, a computer might handle 32-bit word, but still employ a byte- addressable architecture. In this situation, when a word uses multiple bytes, the byte with the lowest address determines the address of the entire word. It is also possible that a computer might be word-addressable, which means each word has its own address, but most current machines are byte-addressable. If architecture is byte-addressable, and the instruction set architecture word is larger than 1 byte, the issue of alignment must be addressed. Memory is built from random access memory (RAM) chips. Memory is often referred to using the notation L X W (length X Length). For example, o 4M X 16 means the memory is 4M long (4M = 22 X 220 = 222 words) and it is 16 bits wide (each word is 16 bits). o To address this memory (assuming word addressing), we need to be able to uniquely identify 222 different items. o The memory locations for this memory are numbered 0 through 222 -1. o The memory bus of this system requires at least 22 address lines. In general, if a computer 2n addressable units of memory, it will require N bits to uniquely address each byte. CMPS375 Class Notes (Chap04) Page 8 / 27 Dr. Kuo-pao Yang Physical memory usually consists of more than one RAM chip. FIGURE 4.5 Memory as a Collection of RAM Chips (32K X 8) o Memory is 32K = 25 X 210 = 215 o 15 bits are needed for each address. o We need 4 bits to select the chip, and 11 bits for the offset into the chip that selects the byte. Access is more efficient when memory is organized into banks of chips with the addresses interleaved across the chips. Suppose we have a byte-addressable memory consisting of 8 modules of 4 byes each, for a total of 32 bytes memory: o Accordingly, in high-order interleaving, the high order address bits specify the memory bank.
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