DOCSLIB.ORG

3.2 the CORDIC Algorithm

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
3.2 the CORDIC Algorithm UC San Diego UC San Diego Electronic Theses and Dissertations Title Improved VLSI architecture for attitude determination computations Permalink https://escholarship.org/uc/item/5jf926fv Author Arrigo, Jeanette Fay Freauf Publication Date 2006 Peer reviewed|Thesis/dissertation eScholarship.org Powered by the California Digital Library University of California 1 UNIVERSITY OF CALIFORNIA, SAN DIEGO Improved VLSI Architecture for Attitude Determination Computations A dissertation submitted in partial satisfaction of the requirements for the degree Doctor of Philosophy in Electrical and Computer Engineering (Electronic Circuits and Systems) by Jeanette Fay Freauf Arrigo Committee in charge: Professor Paul M. Chau, Chair Professor C.K. Cheng Professor Sujit Dey Professor Lawrence Larson Professor Alan Schneider 2006 2 Copyright Jeanette Fay Freauf Arrigo, 2006 All rights reserved. iv DEDICATION This thesis is dedicated to my husband Dale Arrigo for his encouragement, support and model of perseverance, and to my father Eugene Freauf for his patience during my pursuit. In memory of my mother Fay Freauf and grandmother Fay Linton Thoreson, incredible mentors and great advocates of the quest for knowledge. iv v TABLE OF CONTENTS Signature Page...............................................................................................................iii Dedication … ................................................................................................................iv Table of Contents ...........................................................................................................v List of Figures.................................................................................................................x List of Tables...............................................................................................................xiv Acknowledgements ......................................................................................................xv Vita and Publications..................................................................................................xvii Abstract ……............................................................................................................xix 1 INTRODUCTION.......................................................................................1 1.1 Motivation ..........................................................................................................1 1.2 Overview of Chapter 2 .......................................................................................2 1.3 Overview of Chapter 3 .......................................................................................3 1.4 Overview of Chapter 4 .......................................................................................4 1.5 Overview of Chapter 5 .......................................................................................5 1.6 Overview of Chapter 6 .......................................................................................6 1.7 Overview of Chapter 7 .......................................................................................7 2 BACKGROUND..........................................................................................8 2.1 Introduction ........................................................................................................8 2.2 Attitude Parameterization methods ....................................................................9 2.2.1 Direction Cosine Representation......................................................................10 2.2.2 Euler Angle Representation............................................................................122 2.2.3 Euler Axis/Angle Notation...............................................................................13 2.2.4 Quaternion Mathematics ..................................................................................14 2.3 The Kinematic Equation for Rotation ..............................................................18 2.3.1 Methods of Integration .....................................................................................19 2.3.1.1 Direct Integration..............................................................................................19 2.3.1.2 Local Linearization Method .............................................................................20 v vi 2.3.1.3 Exponential Matrix Function............................................................................21 2.3.1.4 Closed Form Approximation (Constant Angular Rate)....................................22 2.3.2. Closed Form Approximation Errors.................................................................25 2.3.2.1 Coning Error....................................................................................................25 2.3.2.2 Orthogonality Error .........................................................................................27 2.4 Conclusion........................................................................................................28 References ........................................................................................................29 3 IMPLEMENTATION ..............................................................................30 3.1 Introduction ......................................................................................................30 3.2 The CORDIC Algorithm ..................................................................................32 3.3 Parallel Design of the Attitude Update System................................................37 3.3.1 Limitations on the Attitude Update Computation ............................................44 3.3.2 ASIC Synthesis.................................................................................................44 3.3.3 Accuracy Analysis............................................................................................45 3.4 Serial Design of the Attitude Update System...................................................47 3.4.1 CORDIC Operations........................................................................................47 3.4.2 Computation of the Magnitude of the Angular Displacement .........................48 3.4.3 Calculation of the Cross Product......................................................................49 3.4.3.1 Scaling ..............................................................................................................50 3.4.4 System Operation and Scheduling....................................................................51 3.4.5 ASIC Synthesis.................................................................................................54 3.4.6 Attitude Update Computation Performance Analysis ......................................55 3.4.6.1 Boundary Analysis ...........................................................................................55 3.4.6.2 Accuracy Analysis...........................................................................................56 3.5 Serial System Design with Parallel Scale Factor Compensation .....................57 3.5.1 Scale Factor Compensation ..............................................................................58 3.5.2 Vectoring Mode Normalization........................................................................59 3.5.3 System Architecture .........................................................................................60 3.5.4 System Operation and Scheduling....................................................................64 3.6 Conclusion........................................................................................................67 vi vii References ........................................................................................................68 4 PARAMETRIC ANALYSES FOR CORDIC BASED ALGORITHM AND COMPARISON TO OTHER APPROXIMATION METHODS ....................................................................70 4.1 Introduction ......................................................................................................70 4.2 Parametric Analysis of the CORDIC Based Algorithm...................................72 4.2.1 Accuracy as a Function of CORDIC Processor Bit Width and Iterations........73 4.2.2 Orthogonality as a Function of Bit Width and the Number of Iterations.........78 4.2.3 Area, Update Rate and Power Consumption as a Function of CORDIC Processor Bit Width and Iterations...............................................................................81 4.2.4 Sensor Errors and Output Accuracy.................................................................85 4.3 Taylor Series Approximation ...........................................................................87 4.3.1 Comparisons of Accuracy ................................................................................89 4.3.2 Comparisons of Orthogonality .........................................................................92 4.4 Wie-Barba Method ...........................................................................................93 4.4.1 Comparisons of Accuracy ................................................................................94 4.4.2 Comparisons of Orthogonality .........................................................................94 4.5 Other Integration Methods ...............................................................................95 4.5.1 Obrechkoff Integration.....................................................................................95
Load more

Recommended publications
  • Fill Your Boots: Enhanced Embedded Bootloader Exploits Via Fault Injection and Binary Analysis
    IACR Transactions on Cryptographic Hardware and Embedded Systems ISSN 2569-2925, Vol. 2021, No. 1, pp. 56–81. DOI:10.46586/tches.v2021.i1.56-81 Fill your Boots: Enhanced Embedded Bootloader Exploits via Fault Injection and Binary Analysis Jan Van den Herrewegen1, David Oswald1, Flavio D. Garcia1 and Qais Temeiza2 1 School of Computer Science, University of Birmingham, UK, {jxv572,d.f.oswald,f.garcia}@cs.bham.ac.uk 2 Independent Researcher, [email protected] Abstract. The bootloader of an embedded microcontroller is responsible for guarding the device’s internal (flash) memory, enforcing read/write protection mechanisms. Fault injection techniques such as voltage or clock glitching have been proven successful in bypassing such protection for specific microcontrollers, but this often requires expensive equipment and/or exhaustive search of the fault parameters. When multiple glitches are required (e.g., when countermeasures are in place) this search becomes of exponential complexity and thus infeasible. Another challenge which makes embedded bootloaders notoriously hard to analyse is their lack of debugging capabilities. This paper proposes a grey-box approach that leverages binary analysis and advanced software exploitation techniques combined with voltage glitching to develop a powerful attack methodology against embedded bootloaders. We showcase our techniques with three real-world microcontrollers as case studies: 1) we combine static and on-chip dynamic analysis to enable a Return-Oriented Programming exploit on the bootloader of the NXP LPC microcontrollers; 2) we leverage on-chip dynamic analysis on the bootloader of the popular STM8 microcontrollers to constrain the glitch parameter search, achieving the first fully-documented multi-glitch attack on a real-world target; 3) we apply symbolic execution to precisely aim voltage glitches at target instructions based on the execution path in the bootloader of the Renesas 78K0 automotive microcontroller.
    [Show full text]
  • Computer Organization and Architecture Designing for Performance Ninth Edition
    COMPUTER ORGANIZATION AND ARCHITECTURE DESIGNING FOR PERFORMANCE NINTH EDITION William Stallings Boston Columbus Indianapolis New York San Francisco Upper Saddle River Amsterdam Cape Town Dubai London Madrid Milan Munich Paris Montréal Toronto Delhi Mexico City São Paulo Sydney Hong Kong Seoul Singapore Taipei Tokyo Editorial Director: Marcia Horton Designer: Bruce Kenselaar Executive Editor: Tracy Dunkelberger Manager, Visual Research: Karen Sanatar Associate Editor: Carole Snyder Manager, Rights and Permissions: Mike Joyce Director of Marketing: Patrice Jones Text Permission Coordinator: Jen Roach Marketing Manager: Yez Alayan Cover Art: Charles Bowman/Robert Harding Marketing Coordinator: Kathryn Ferranti Lead Media Project Manager: Daniel Sandin Marketing Assistant: Emma Snider Full-Service Project Management: Shiny Rajesh/ Director of Production: Vince O’Brien Integra Software Services Pvt. Ltd. Managing Editor: Jeff Holcomb Composition: Integra Software Services Pvt. Ltd. Production Project Manager: Kayla Smith-Tarbox Printer/Binder: Edward Brothers Production Editor: Pat Brown Cover Printer: Lehigh-Phoenix Color/Hagerstown Manufacturing Buyer: Pat Brown Text Font: Times Ten-Roman Creative Director: Jayne Conte Credits: Figure 2.14: reprinted with permission from The Computer Language Company, Inc. Figure 17.10: Buyya, Rajkumar, High-Performance Cluster Computing: Architectures and Systems, Vol I, 1st edition, ©1999. Reprinted and Electronically reproduced by permission of Pearson Education, Inc. Upper Saddle River, New Jersey, Figure 17.11: Reprinted with permission from Ethernet Alliance. Credits and acknowledgments borrowed from other sources and reproduced, with permission, in this textbook appear on the appropriate page within text. Copyright © 2013, 2010, 2006 by Pearson Education, Inc., publishing as Prentice Hall. All rights reserved. Manufactured in the United States of America.
    [Show full text]
  • ARM Instruction Set
    4 ARM Instruction Set This chapter describes the ARM instruction set. 4.1 Instruction Set Summary 4-2 4.2 The Condition Field 4-5 4.3 Branch and Exchange (BX) 4-6 4.4 Branch and Branch with Link (B, BL) 4-8 4.5 Data Processing 4-10 4.6 PSR Transfer (MRS, MSR) 4-17 4.7 Multiply and Multiply-Accumulate (MUL, MLA) 4-22 4.8 Multiply Long and Multiply-Accumulate Long (MULL,MLAL) 4-24 4.9 Single Data Transfer (LDR, STR) 4-26 4.10 Halfword and Signed Data Transfer 4-32 4.11 Block Data Transfer (LDM, STM) 4-37 4.12 Single Data Swap (SWP) 4-43 4.13 Software Interrupt (SWI) 4-45 4.14 Coprocessor Data Operations (CDP) 4-47 4.15 Coprocessor Data Transfers (LDC, STC) 4-49 4.16 Coprocessor Register Transfers (MRC, MCR) 4-53 4.17 Undefined Instruction 4-55 4.18 Instruction Set Examples 4-56 ARM7TDMI-S Data Sheet 4-1 ARM DDI 0084D Final - Open Access ARM Instruction Set 4.1 Instruction Set Summary 4.1.1 Format summary The ARM instruction set formats are shown below. 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 9876543210 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 Cond 0 0 I Opcode S Rn Rd Operand 2 Data Processing / PSR Transfer Cond 0 0 0 0 0 0 A S Rd Rn Rs 1 0 0 1 Rm Multiply Cond 0 0 0 0 1 U A S RdHi RdLo Rn 1 0 0 1 Rm Multiply Long Cond 0 0 0 1 0 B 0 0 Rn Rd 0 0 0 0 1 0 0 1 Rm Single Data Swap Cond 0 0 0 1 0 0 1 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 Rn Branch and Exchange Cond 0 0 0 P U 0 W L Rn Rd 0 0 0 0 1 S H 1 Rm Halfword Data Transfer: register offset Cond 0 0 0 P U 1 W L Rn Rd Offset 1 S H 1 Offset Halfword Data Transfer: immediate offset Cond 0
    [Show full text]
  • CORDIC-Like Method for Solving Kepler's Equation
    A&A 619, A128 (2018) Astronomy https://doi.org/10.1051/0004-6361/201833162 & c ESO 2018 Astrophysics CORDIC-like method for solving Kepler’s equation M. Zechmeister Institut für Astrophysik, Georg-August-Universität, Friedrich-Hund-Platz 1, 37077 Göttingen, Germany e-mail: [email protected] Received 4 April 2018 / Accepted 14 August 2018 ABSTRACT Context. Many algorithms to solve Kepler’s equations require the evaluation of trigonometric or root functions. Aims. We present an algorithm to compute the eccentric anomaly and even its cosine and sine terms without usage of other transcen- dental functions at run-time. With slight modifications it is also applicable for the hyperbolic case. Methods. Based on the idea of CORDIC, our method requires only additions and multiplications and a short table. The table is inde- pendent of eccentricity and can be hardcoded. Its length depends on the desired precision. Results. The code is short. The convergence is linear for all mean anomalies and eccentricities e (including e = 1). As a stand-alone algorithm, single and double precision is obtained with 29 and 55 iterations, respectively. Half or two-thirds of the iterations can be saved in combination with Newton’s or Halley’s method at the cost of one division. Key words. celestial mechanics – methods: numerical 1. Introduction expansion of the sine term and yielded with root finding methods a maximum error of 10−10 after inversion of a fifteen-degree Kepler’s equation relates the mean anomaly M and the eccentric polynomial. Another possibility to reduce the iteration is to use anomaly E in orbits with eccentricity e.
    [Show full text]
  • Consider an Instruction Cycle Consisting of Fetch, Operators Fetch (Immediate/Direct/Indirect), Execute and Interrupt Cycles
    Module-2, Unit-3 Instruction Execution Question 1: Consider an instruction cycle consisting of fetch, operators fetch (immediate/direct/indirect), execute and interrupt cycles. Explain the purpose of these four cycles. Solution 1: The life of an instruction passes through four phases—(i) Fetch, (ii) Decode and operators fetch, (iii) execute and (iv) interrupt. The purposes of these phases are as follows 1. Fetch We know that in the stored program concept, all instructions are also present in the memory along with data. So the first phase is the “fetch”, which begins with retrieving the address stored in the Program Counter (PC). The address stored in the PC refers to the memory location holding the instruction to be executed next. Following that, the address present in the PC is given to the address bus and the memory is set to read mode. The contents of the corresponding memory location (i.e., the instruction) are transferred to a special register called the Instruction Register (IR) via the data bus. IR holds the instruction to be executed. The PC is incremented to point to the next address from which the next instruction is to be fetched So basically the fetch phase consists of four steps: a) MAR <= PC (Address of next instruction from Program counter is placed into the MAR) b) MBR<=(MEMORY) (the contents of Data bus is copied into the MBR) c) PC<=PC+1 (PC gets incremented by instruction length) d) IR<=MBR (Data i.e., instruction is transferred from MBR to IR and MBR then gets freed for future data fetches) 2.
    [Show full text]
  • CORDIC V6.0 Logicore IP Product Guide
    CORDIC v6.0 LogiCORE IP Product Guide Vivado Design Suite PG105 August 6, 2021 Table of Contents IP Facts Chapter 1: Overview Navigating Content by Design Process . 5 Core Overview . 5 Feature Summary. 6 Applications . 6 Licensing and Ordering . 7 Chapter 2: Product Specification Performance. 8 Resource Utilization. 9 Port Descriptions . 9 Chapter 3: Designing with the Core Clocking. 12 Resets . 12 Protocol Description – AXI4-Stream . 12 Functional Description. 17 Input/Output Data Representation . 30 Chapter 4: Design Flow Steps Customizing and Generating the Core . 38 System Generator for DSP. 44 Constraining the Core . 44 Simulation . 45 Synthesis and Implementation . 46 Chapter 5: C Model Features . 47 Overview . 47 Installation . 48 C Model Interface. 49 CORDIC v6.0 Send Feedback 2 PG105 August 6, 2021 www.xilinx.com Compiling . 53 Linking. 53 Dependent Libraries . 54 Example . 55 Chapter 6: Test Bench Demonstration Test Bench . 56 Appendix A: Upgrading Migrating to the Vivado Design Suite. 58 Upgrading in the Vivado Design Suite . 58 Appendix B: Debugging Finding Help on Xilinx.com . 62 Debug Tools . 63 Simulation Debug. 64 AXI4-Stream Interface Debug . 65 Appendix C: Additional Resources and Legal Notices Xilinx Resources . 66 Documentation Navigator and Design Hubs . 66 References . 67 Revision History . 67 Please Read: Important Legal Notices . 68 CORDIC v6.0 Send Feedback 3 PG105 August 6, 2021 www.xilinx.com IP Facts Introduction LogiCORE IP Facts Table Core Specifics This Xilinx® LogiCORE™ IP core implements a Versal™ ACAP
    [Show full text]
  • A Review on Hardware Accelerator Design and Implementation of CORDIC Algorithm for a Gaming Application
    International Journal of Innovative Technology and Exploring Engineering (IJITEE) ISSN: 2278-3075, Volume-9 Issue-9, July 2020 A Review on Hardware Accelerator Design and Implementation of CORDIC Algorithm for a Gaming Application Trupthi B, Jalendra H E, Srilaxmi C P, Varun M S, Geethashree A Abstract - Co-ordinate Digital rotation computer is the full The conversion of rectangular to polar and polar to form of CORDIC.CORDIC is a process for finding functions rectangular function are the two major operations in using less hardware like shifts, subs/adds and then compares. It's CORDIC. Basically, they are the two different co-ordinates the algorithm used for some elementary functions which are calculated in real-time and many conversions like from to represent the 2D plane. The Rectangular form is rectangular to polar co-ordinate and vice versa. Rectangular to represented by a real part (horizontal axis) and an imaginary polar and polar to rectangular is an important operation in (Vertical axis) part of the vector. The Rectangular form is CORDIC which are generally used in ALUs, wireless shown by a real part (horizontal axis) and an imaginary communications, DSP processors etc. This paper proposes the (Vertical axis) part of the vector [8].The rectangular co- implementation of physical design for CORDIC algorithm for ordinates are in the form of (x, y) where „x‟ stands for a polar to rectangular and rectangular to polar conversions, by the use of RTL code in written in Verilog and fed to pre-processor, horizontal plane and „y‟ stands for the vertical plane from cordic core and post processor.
    [Show full text]
  • Akukwe Michael Lotachukwu 18/Sci01/014 Computer Science
    AKUKWE MICHAEL LOTACHUKWU 18/SCI01/014 COMPUTER SCIENCE The purpose of every computer is some form of data processing. The CPU supports data processing by performing the functions of fetch, decode and execute on programmed instructions. Taken together, these functions are frequently referred to as the instruction cycle. In addition to the instruction cycle functions, the CPU performs fetch and writes functions on data. When a program runs on a computer, instructions are stored in computer memory until they're executed. The CPU uses a program counter to fetch the next instruction from memory, where it's stored in a format known as assembly code. The CPU decodes the instruction into binary code that can be executed. Once this is done, the CPU does what the instruction tells it to, performing an operation, fetching or storing data or adjusting the program counter to jump to a different instruction. The types of operations that typically can be performed by the CPU include simple math functions like addition, subtraction, multiplication and division. The CPU can also perform comparisons between data objects to determine if they're equal. All the amazing things that computers can do are performed with these and a few other basic operations. After an instruction is executed, the next instruction is fetched and the cycle continues. While performing the execute function of the instruction cycle, the CPU may be asked to execute an instruction that requires data. For example, executing an arithmetic function requires the numbers that will be used for the calculation. To deliver the necessary data, there are instructions to fetch data from memory and write data that has been processed back to memory.
    [Show full text]
  • Parallel Computing
    Lecture 1: Computer Organization 1 Outline • Overview of parallel computing • Overview of computer organization – Intel 8086 architecture • Implicit parallelism • von Neumann bottleneck • Cache memory – Writing cache-friendly code 2 Why parallel computing • Solving an × linear system Ax=b by using Gaussian elimination takes ≈ flops. 1 • On Core i7 975 @ 4.0 GHz,3 which is capable of about 3 60-70 Gigaflops flops time 1000 3.3×108 0.006 seconds 1000000 3.3×1017 57.9 days 3 What is parallel computing? • Serial computing • Parallel computing https://computing.llnl.gov/tutorials/parallel_comp 4 Milestones in Computer Architecture • Analytic engine (mechanical device), 1833 – Forerunner of modern digital computer, Charles Babbage (1792-1871) at University of Cambridge • Electronic Numerical Integrator and Computer (ENIAC), 1946 – Presper Eckert and John Mauchly at the University of Pennsylvania – The first, completely electronic, operational, general-purpose analytical calculator. 30 tons, 72 square meters, 200KW. – Read in 120 cards per minute, Addition took 200µs, Division took 6 ms. • IAS machine, 1952 – John von Neumann at Princeton’s Institute of Advanced Studies (IAS) – Program could be represented in digit form in the computer memory, along with data. Arithmetic could be implemented using binary numbers – Most current machines use this design • Transistors was invented at Bell Labs in 1948 by J. Bardeen, W. Brattain and W. Shockley. • PDP-1, 1960, DEC – First minicomputer (transistorized computer) • PDP-8, 1965, DEC – A single bus
    [Show full text]
  • A.1 CORDIC Algorithm
    Research on Hardware Intellectual Property Cores Based on Look-Up Table Architecture for DSP Applications HOANG VAN PHUC Doctoral Program in Electronic Engineering Graduate School of Electro-Communications The University of Electro-Communications A thesis submitted for the degree of DOCTOR OF ENGINEERING September 2012 I would like to dedicate this dissertation to my parents, my wife and my daughter. Research on Hardware Intellectual Property Cores Based on Look-Up Table Architecture for DSP Applications APPROVED Asso. Prof. Cong-Kha PHAM, Chairman Prof. Kazushi NAKANO Prof. Yoshinao MIZUGAKI Prof. Koichiro ISHIBASHI Asso. Prof. Takayuki NAGAI Date Approved by Chairman c Copyright 2012 by HOANG Van Phuc All Rights Reserved. 和文要旨 DSPアプリケーションのためのルックアップテーブルアーキテ クチャに基づくハードウェアIPコアに関する研究 ホアン ヴァンフック 電気通信学研究科電子工学専攻博士後期課程 電気通信大学大学院 本論文は，ルックアップテーブル（LUT）アーキテクチャに基づく省面積 かつ高性能なハードウェア IP コアを提案し，DSP アプリケーションに適用 することを目的としている．LUT ベースの IP コアおよびこれらに基づいた 新しい計算システムを提案した．ここで，提案する計算システムには，従来 の演算と提案する IP コアを含む．提案する IP コアには，乗算や二乗計算等 の基本演算と，正弦関数や対数・真数計算等の初等関数が含まれる. まず初めに，高効率な LUT 乗算器および二乗回路の設計を目的として， ２つの方法を提案した．１つは，全幅結果が不要な場合に DSP に応用可能 な打切り定数乗算器である．このアーキテクチャには，LUT ベースの計算と DSP 用の打切り定数乗算器という２つのアプローチを組み合わせた．最適な パラメータと LUT の内容を探索するために，LUT 最適化アルゴリズムの検 討を行った．さらに，固定幅二乗回路向けに LUT ハイブリッドアーキテク チャを改良した．この技術は，二乗回路における性能，誤計算率，複雑さの 間の妥協点を見いだすために，LUT 論理回路と従来の論理回路の両方を採用 したものである． 初等関数の計算については，LUT ベースの計算と線形差分法を組み合わせ て，２つのアーキテクチャを提案した．１つは，ディジタル周波数合成器， 適応信号処理技術および正弦関数生成器に利用可能な正弦関数計算のために， 線形差分法を改良したものである．他の方法と比較して誤計算率が変わらな い一方で，LUT の規模と複雑さを抑える最適パラメータを探索するために数 値解析と最適化を行った．その他に，対数計算および真数計算向けに，疑似
    [Show full text]
  • An Optimization of CORDIC Algorithm and FPGA Implementation
    International Journal of Hybrid Information Technology Vol.8, No.6 (2015), pp.217-228 http://dx.doi.org/10.14257/ijhit.2015.8.6.21 An Optimization of CORDIC Algorithm and FPGA Implementation Rui Xua, Zhanpeng Jiangb, Hai Huangc, Changchun Dongd Department of Integrated circuits design and integrated systems,Harbin University of Science and Technology ,Harbin, Heilongjiang, China [email protected], b [email protected], [email protected] [email protected] Abstract ASIC and FPGA ASIC and FPGA are considered to be the ideal platform for special fast calculations because of the hardware structure, and how to achieve computational algorithm by is the hotpot of research. The CORDIC (Coordinate Rotational Digital Computer) can break the basis functions down to operations of shift and addition or subtraction, which can be used to lay the foundation for the realization of complex logic. But the functions selected by traditional CODIC for angle encoding are too complex, which will lead to some problems, such as too much of area consumption and large delay. In this paper, an optimization of CORDIC algorithm are proposed, which reduce the consumption of Adders and comparators, decrease the complexity and delay of the algorithm implement in hardware. The proposed algorithms are modeled in Verilog Hardware Description Language and implemented with FPGA. The simulation results show that the functions of sine and cosine are realized successfully, and the proposed algorithm not only improves the computation speed but also reduces
    [Show full text]
  • FPGA Technology in Beam Instrumentation and Related Tools
    FPGA technology in beam instrumentation and related tools Javier Serrano CERN, Geneva, Switzerland DIPAC 2005. Lyon, France. 7 June 2005. Plan of the presentation z FPGA architecture basics z FPGA design flow z Performance boosting techniques z Doing arithmetic with FPGAs z Example: RF cavity control in CERN’s Linac 3. DIPAC 2005. Lyon, France. 7 June 2005. A preamble: basic digital design Clk [31:0] DataInB[31:0] [31:0] D[31:0] Q[31:0] [31:0] D[0] Q[0] [31:0] 0 dataBC[31:0] dataSelectC [31:0] [31:0] [31:0] D[31:0] Q[31:0] [31:0] DataOut[31:0] DataSelect [31:0] 1 DataOut[31:0] DataOut_3[31:0] [31:0] High clock rate: [31:0] + [31:0] sum[31:0] DataInA[31:0] [31:0] D[31:0] Q[31:0] 144.9 MHz on a [31:0] [31:0] 6.90 ns dataAC[31:0] Xilinx Spartan IIE. DataSelect D[0] Q[0] D[0] Q[0] dataSelectC dataSelectCD1 Clk [31:0] D[31:0] Q[31:0] [31:0] 0 [31:0] [31:0] [31:0] [31:0] DataInB[31:0] [31:0] D[31:0] Q[31:0] [31:0] [31:0] D[31:0] Q[31:0] [31:0] DataOut[31:0] dataACd1[31:0] [31:0] 1 dataBC[31:0] DataOut[31:0] DataOut_3[31:0] Higher clock rate: [31:0] [31:0] + [31:0] D[31:0] Q[31:0] [31:0] DataInA[31:0] [31:0] D[31:0] Q[31:0] [31:0] 151.5 MHz on the [31:0] [31:0] sum_1[31:0] sum[31:0] dataAC[31:0] 6.60 ns same chip.
    [Show full text]