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A Review on Hardware Accelerator Design and Implementation of CORDIC Algorithm for a Gaming Application International Journal of Innovative Technology and Exploring Engineering (IJITEE) ISSN: 2278-3075, Volume-9 Issue-9, July 2020 A Review on Hardware Accelerator Design and Implementation of CORDIC Algorithm for a Gaming Application Trupthi B, Jalendra H E, Srilaxmi C P, Varun M S, Geethashree A Abstract - Co-ordinate Digital rotation computer is the full The conversion of rectangular to polar and polar to form of CORDIC.CORDIC is a process for finding functions rectangular function are the two major operations in using less hardware like shifts, subs/adds and then compares. It's CORDIC. Basically, they are the two different co-ordinates the algorithm used for some elementary functions which are calculated in real-time and many conversions like from to represent the 2D plane. The Rectangular form is rectangular to polar co-ordinate and vice versa. Rectangular to represented by a real part (horizontal axis) and an imaginary polar and polar to rectangular is an important operation in (Vertical axis) part of the vector. The Rectangular form is CORDIC which are generally used in ALUs, wireless shown by a real part (horizontal axis) and an imaginary communications, DSP processors etc. This paper proposes the (Vertical axis) part of the vector [8].The rectangular co- implementation of physical design for CORDIC algorithm for ordinates are in the form of (x, y) where „x‟ stands for a polar to rectangular and rectangular to polar conversions, by the use of RTL code in written in Verilog and fed to pre-processor, horizontal plane and „y‟ stands for the vertical plane from cordic core and post processor. This type of implementation the origin likewise, the Polar Form is represented by vector results with greater efficiency, throughput by reducing power magnitude and angle which is calculated respect to the real consumption and implanting it with high frequency. Hence due to axis. The vector value will be the complex number's great efficiency with low power it can be used for gaming modulus, polar co-ordinates are in the form of (푟, Ө) where applications. „r‟ stands for distance from the starting point to the Keywords: CORDIC, rectangular, polar, Co-ordinates, Digital estimated point and „Ө‟ is an angle measured from positive Signal Processing, FPGA, ASIC, efficiency, Power optimization . „x‟ axis [15]. These conversions are used in different processors like ALU, DSP and various communication I. INTRODUCTION purposes like wireless and satellite communication. Co-ordinate rotation Digital Computer or (CORDIC) is an II. THE CORDIC ALGORITHM algorithm given by Volder [8]. It is an algorithm that provides an easy way of rotating vector in same single plane The abbreviation for CORDIC is Co-ordinate Rotation by simple addition and shift operation. This works when we Digital Computer. The CORDIC algorithm is used to rotate the system co-ordinates through fixed angles until determine the real-time part of calculation for the functions which the resultant angle should reduce until zero. The using the iterative rotation of the vector which is fed as input offsets of angles are zero such that the operations performed [2]. The CORDIC algorithm performs a planar rotation. A on X and Y are added and shifted [19]. It is an easy and vector (Xi, Yi) gets transformed means the planar rotation efficient way to implement this algorithm used to calculate into completely a new vector 푋푗 , 푌푗 that is obtained as functions like trigonometric, hyperbolic and other functions shown in Fig 1 [1]. others like multiplication, division and also some other The planar rotation of any vector of (Xi, Yi) in matrix form operations like logarithmic functions, square roots and exponential functions [24].These are implemented in areas can be as shown in Equation (1). of the design algorithm and developed the architectures to provide high performance. X j cos sin X i (1) Y sin cos Y j i Revised Manuscript Received on June 30, 2020. The angle rotation of takes various steps. All these steps * Correspondence Author will comprise one planar rotation. A single step is given by Trupthi B, Department of Electronics and Communication, the equation (2) Vidyavardhaka College of Engineering, Mysore, Karnataka, India, E-mail: [email protected] X n1 cosn sinn X n Jalendra H E, Department of Electronics and Communication, (2) Vidyavardhaka College of Engineering, Mysore, Karnataka, India, E-mail: Yn1 sinn cosn Yn [email protected] Srilaxmi C P, Department of Electronics and Communication, Vidyavardhaka College of Engineering, Mysore, Karnataka, India, E-mail: Equation 2 can be hence modified by cancelling the [email protected] cosn Varun M S, Department of Electronics and Communication, Vidyavardhaka College of Engineering, Mysore, Karnataka, India, E-mail: factor. [email protected] Dr. Geethashree A, Department of Electronics and Communication, Vidyavardhaka College of Engineering, Mysore, Karnataka, India, E-mail: [email protected] Published By: Retrieval Number: I7271079920/2020©BEIESP Blue Eyes Intelligence Engineering DOI: 10.35940/ijitee.I7271.079920 605 and Sciences Publication A Review on Hardware Accelerator Design and Implementation of CORDIC Algorithm for a Gaming Application 2n X n1 1 tan n X n X n1 X n S n 2 Yn (3) (13) cos n 2n Yn1 tan n 1 Yn Yn1 Yn S n 2 X n The multipliers which added are hence eliminated by Here the Z represents the part of the angle which is not choosing the angle steps. Where tangent of step is given by rotated. power of 2. Hence the step angle can be given as n (14) Z n1 i 1 i0 n arctan (4) 2n For each step of rotation, value of Sn is determined as a sign of Zn. (5) Sn n n0 1 if Z n 0 S n (15) where 1 if Z n 0 Sn 1;1 (6) Combining Equation (5) and Equation (15) gives a system which reduces the un-rotated part of angle to zero. This gives III. CORDIC ALGORITHM ARCHITECTURE tan S 2n n n (7) Three fundamental blocks are used to construct any CORDIC Processor cores those are namely pre-processor, Combining Equation (3) and Equation (7) we get the post-processor and the actual CORDIC core. The core part of CORDIC is basically made up of different types of n X n1 1 Sn 2 X n architecture. Then below are the main architectures in the cosn n Y S 2 1 Y CORDIC algorithm. n1 n n (8) Fig 1 Planar rotation of (푿풊, 풀풊). Y (Xj, Yj) The coefficient can be eradicated fully by pre-determination of the final result. The coefficient can be given as, (Xi, Yi) 1 (9) cosn cosarctan n 2 X Equation (9) can be found for all values of „푛‟, where 퐾 is A) Iterative Architecture: one such constant. Work of shift-add/sub-operations is serial, and architecture 1 1 K cosarctan 0.607253 (10) of CORDIC core is implemented in sequential n P n0 2 configuration, using a single shift-add/sub-stage and feeding back the output. A minimum latency CORDIC core and The derivative P (approximate 1.64676) is defined. takes minimum of N cycles to determine the new output. The relationship is that the implementation size of this is related to the precision internally. X j KX i cos Yi sin (11) Y j KYi cos X i sin The coefficient K is pre-determined as n X n1 1 S n 2 X n n (12) Yn1 S n 2 1 Yn Or as Published By: Retrieval Number: I7271079920/2020©BEIESP Blue Eyes Intelligence Engineering DOI: 10.35940/ijitee.I7271.079920 606 and Sciences Publication International Journal of Innovative Technology and Exploring Engineering (IJITEE) ISSN: 2278-3075, Volume-9 Issue-9, July 2020 There is a similarity in the structure used compared to that of a Parallel CORDIC. In between each iteration phase pipeline registers are used. The advantages in pipelined CORDIC is for continuous input values. IV. SOFTWARE IMPLEMENTATION For application-specific CORDIC processors, the very common application is in Digital signal processing for vector rotation. In the paper [2], the design of pipeline architecture is defined on the basis of application-specific processor of CORDIC used for the determination of values of sine and cosine. Due to its pipeline architecture, CORDIC's design in rotation mode in a circular way gives overall high system throughput by reducing the latency in every level of pipeline. The synchronizer function is autocorrelation. In the OFDM amplifier, CORDIC is then efficiently used to measure the offset of frequency and to determine the division equation for calculating channels. In the paper [3], by using 130 nm technology, a rapid pipeline CORDIC architecture and auto-correlator are first designed, implemented and then tested. A MATLAB simulation is performed to verify at functional level before the coding in Verilog HDL. Digital signal processing (DSP) has been always driven front in case of DSP applications and also in very-large-scale (VLSI) technology. This raised many issues Fig 2: Iterative Architecture [26] with DSP applications deployment. These implementations will meet the DSP systems defined real-time sampling rate B) Parallel or Cascaded Architecture: constraints which covers less space and power consumption. This architecture uses various formulation of Iterative Flexibility, high throughput, low power and low cost are CORDIC. Here it is basically shift-add/sub-stages in reasons for the development of today's VLSI (FPGA / CORDIC core with parallel architecture being with it. The ASIC) based communication of mobile and wireless throughput or the latency of one such clock cycle is obtained medium. The WLAN which is based on OFDM is the next- for output of N-bit parallel CORDIC core.
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