MARIE: An Introduction to a Outline Simple Computer Learn the components common to every modern computer system. Be able to explain how each component contributes to program execution. Understand a simple architecture invented Machine Architecture that is Really to illuminate these basic concepts, and how Intuitive and Easy it relates to some real architectures. Know how the program assembly process works. CS 2401 Comp. Org. Marie -- Chapter 4 1 CS 2401 Comp. Org. & Marie -- Chapter 4 2 & Assembly Assembly 44..11 Introduction 44..22 CPU Basic and Organization Chapter 1 presented a general overview of The computer’s CPU fetches, decodes, and computer systems. executes program iiinstructions. In Chapter 2, we discussed how data is stored and manipulated by various The two principal parts of the CPU are the computer system components. datapath and the control unit. Chapter 3 described the fundamental The datapath consists of an arithmetic-logic unit components of digital circuits. and storage units (registers) that are Having this background, we can now interconnected by a data bus that is also unddhderstand how computer components connected to main memory. work, and how they fit together to create Various CPU components perform sequenced useful computer systems. operations according to signals provided by its control unit. CS 2401 Comp. Org. & Marie -- Chapter 4 3 CS 2401 Comp. Org. & Marie -- Chapter 4 4 Assembly Assembly 1 44..22 CPU Basic and Organization 44..33 The BUS Registers hold data -- addresses, program counters, The CPU shares data with other system data -- that can be readily accessed by the CPU. comppyyonents by way of a data bus. Size of a register varies according to the design. A bus is a set of wires that simultaneously convey a single bit along each line. The number of registers varies from architecture to Two types of buses are commonly found in architecture. computer systems: point-to-point, and multipoint They can be implemented using D flip-flops. buses. A 32-bit register requires 32 D flip-flops. The arithmetic-logic unit (ALU) carries out logical and arithmetic operations as directed by the control unit. The control unit determines which actions to carry out according to the values in a program counter register and a status register. point-to-point bus configuration multipoint configuration CS 2401 Comp. Org. & Marie -- Chapter 4 5 CS 2401 Comp. Org. & Marie -- Chapter 4 6 Assembly Assembly 44..33 The BUS 44..33 The BUS Buses consist of data lines, control lines, and address lines. A multipoint bus is shown below. Data lines convey bits from one device to another Because a multipoint bus is a shared Control lines determine the direction of data flow resource, access to it is controlled through when each device can access the bus protocols, which are built into the Acknowledge bus request, interrupts, and clock synchronization signals hardware. Address lines determine the location of the source or destination of the data. CS 2401 Comp. Org. & Marie -- Chapter 4 7 CS 2401 Comp. Org. & Marie -- Chapter 4 8 Assembly Assembly 2 44..33 The BUS 44..33 The BUS Bus transactions: In a master-slave configuration, where more than one Sending an address for a read or write device can be the bus master, concurrent bus master Transferring data from memory to a register for memory read requests must be arbitrated. Transferring data from a register to memory for memory write Four categories of bus arbitration are: I/O reads and writes from peripheral devices Daisy chain: Permissions are passed from the Each transfer occurs within a bus cycle highest-priority device to the lowest. Centralized parallel: Each device is directly connected to an arbitration circuit. Distributed using self-detection: Devices decide which gets the bus among themselves. Distributed using collision-detection: Any device can try to use the bus. If its data collides with the data of another device, it tries again. CS 2401 Comp. Org. & Marie -- Chapter 4 9 CS 2401 Comp. Org. & Marie -- Chapter 4 10 Assembly Assembly 44..44 Clocks 44..44 Clocks Every computer contains at least one clock that Clock speed should not be confused with CPU synchronizes the activities of its components. performance. A fixed number of clock cycles are required to carry The CPU time required to run a program is given by out each data movement or computational operation. the general performance equation: The clock frequency, measured in megahertz or gigahertz, determines the speed with which all operations are carried out. We see that we can improve CPU throughput when Clock cycle time is the reciprocal of clock frequency. we reduce the number of instructions in a program, An 800 MHz clock has a cycle time of 1.25 ns. reduce the number of cyypcles per instruction, or reduce the number of nanoseconds per clock cycle. Multiplication operation Intel 286 required 20 clock cycles Pentium required 1 clock cycle CS 2401 Comp. Org. & Marie -- Chapter 4 11 CS 2401 Comp. Org. & Marie -- Chapter 4 12 Assembly Assembly 3 44..66 Memory Organization and 44..55 Input/Output Subsystem Addressing Computer memory consists of a linear array of addressable A computer communicates with the outside storage cells that are similar to registers. world through its input/output (I/O) Memory can be btbyte-addressa ble, or word-addressa ble, where a subsystem. word typically consists of two or more bytes. Memory is constructed of RAM chips, often referred to in terms of I/O devices connect to the CPU through length width. various interfaces. If the memory word size of the machine is 16 bits, then a 4M 16 RAM chip gives us 4 megabytes of 16-bit memory locations. I/O can be memory-mapped-- where the I/O device behaves like main memory from the CPU’s point of view. O/OOr I/O can be instruction-bdhbased, where t he CPU has a specialized I/O instruction set. We study I/O in detail in chapter 7. CS 2401 Comp. Org. & Marie -- Chapter 4 13 CS 2401 Comp. Org. & Marie -- Chapter 4 14 Assembly Assembly 44..66 Memory Organization and 44..66 Memory Organization and Addressing Addressing How does the computer access a memory Physical memory usually consists of more location corresponds to a particular than one RAM chip. address? Access is more efficient when memory is We observe that 4M can be expressed as organized into banks of chips with the 22 220 = 222 words. addresses interleaved across the chips The memory locations for this memory are With low-order interleaving, the low order numbered 0 through 222 1. bits of the address specify which memory Thus, the memory bus of this system bank contains the address of interest. requires at least 22 address lines. Accordldingly, in hhhigh-ordlder interleaving, the The address lines “count” from 0 to 222 -1 in high order address bits specify the memory binary. Each line is either “on” or “off” indicating bank. the location of the desired memory element. CS 2401 Comp. Org. & Marie -- Chapter 4 15 CS 2401 Comp. Org. & Marie -- Chapter 4 16 Assembly Assembly 4 44..66 Memory Organization and Addressing Problem 4 Page 260 How many bits would you need to address a 2M 32 memory if a. The memory is byte-addressable? Low-Order Interleaving b. The memory is word-addressable? a. There are 2M × 4 byyqtes which equals 2 × 220 × 22 = 223 total bytes, so 23 bits are needed for an address b. There are 2M words which equals 2 × 220 = 221, so 21 bits are required for an address High-Order Interleaving CS 2401 Comp. Org. & Marie -- Chapter 4 17 CS 2401 Comp. Org. & Marie -- Chapter 4 18 Assembly Assembly Problem 5 Page 260 Problem 9 Page 260 Suppose that a 2M 16 main memory is built using How many bits would you need to 256K 8 RAM chips and memory is word-addressable. address a 4M 16 memory if a. How many RAM chips are necessary? a. The memory is byte-addressable? b. How many RAM chips are there per memory word? c. How many address bits are needed for each RAM b. The memory is word-addressable? chip? d. How many banks will this memory have? e. How many address bits are needed for all of 20 2 23 a. There are 2M × 4 byyqtes which equals 2 × 2 × 2 = 2 total memory? bytes, so 23 bits are needed for an address b. There are 2M words which equals 2 × 220 = 221, so 21 bits f. If high-order interleaving is used, where would are required for an address address 14 (which is E in hex) be located? g. Repeat Exercise 6f for low-order interleaving. CS 2401 Comp. Org. & Marie -- Chapter 4 19 CS 2401 Comp. Org. & Marie -- Chapter 4 20 Assembly Assembly 5 Problem 9 Page 260 Problem 11 Page 261 A digital computer has a memory unit with 24 bits per 000 218 23 218 23 00000 – 3FFFF word. The instruction set consists of 150 different operations. All instructions have an operation code 001 218 23 218 23 00000 – 3FFFF part (opcode) and address part (allowing for only one address). Each instruction is stored in one word of 010 218 23 218 23 00000 – 3FFFF memory. 011 218 23 218 23 00000 – 3FFFF a. How many bits are needed for the opcode? 100 218 23 218 23 00000 – 3FFFF b. How many bits are left for the address part of the instruction? 18 3 18 3 101 2 2 2 2 00000 – 3FFFF c. What is the maximum allowable size for memory? 110 218 23 218 23 00000 – 3FFFF d.