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Mark Bohr 2014 IDF Session Presentation

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Mark Bohr 2014 IDF Session Presentation 14 nm Process Technology: Opening New Horizons Mark Bohr Intel Senior Fellow Logic Technology Development SPCS010 Agenda • Introduction • 2nd Generation Tri-gate Transistor • Logic Area Scaling • Cost per Transistor • Product Benefits • SoC Feature Menu 2 Agenda • Introduction • 2nd Generation Tri-gate Transistor • Logic Area Scaling • Cost per Transistor • Product Benefits • SoC Feature Menu 3 Intel Technology Roadmap 22 nm 14 nm 10 nm 7 nm Manufacturing Development Research 4 Intel Technology Roadmap 22 nm 14 nm 10 nm 7 nm Manufacturing Development Research >500 million chips using 22 nm Tri-gate (FinFET) transistors shipped to date 5 Intel Technology Roadmap 22 nm 14 nm 10 nm 7 nm Manufacturing Development Research Industry’s first 14 nm technology is now in volume manufacturing 6 Intel Scaling Trend 10 10000 1 1000 Scaled transistors provide: • Higher performance Micron 0.1 ~0.7x per 100 nm generation • Lower power 32 nm 22 nm 14 nm 0.01 10 • Lower cost per transistor 0.001 1 1970 1980 1990 2000 2010 2020 Moore’s Law continues! 7 How Small is 14 nm? 10 1 100 10 1 100 10 1 100 10 1 0.1 meter millimeter micrometer nanometer 8 How Small is 14 nm? Mark Fly Mite Blood Cell Virus Silicon Atom 1.66 m 7 mm 300 um 7 um 100 nm 0.24 nm 10 1 100 10 1 100 10 1 100 10 1 0.1 meter millimeter micrometer nanometer 9 How Small is 14 nm? 14 nm Process Mark Fly Mite Blood Cell Virus Silicon Atom 1.66 m 7 mm 300 um 7 um 100 nm 0.24 nm 10 1 100 10 1 100 10 1 100 10 1 0.1 meter millimeter micrometer nanometer Very small 10 14 nm Tri-gate Transistor Fins Gate 8 nm Fin Width 42 nm Fin Pitch Si Substrate 11 14 nm Intel® Core™ M Processor 1.3 billion transistors 82 mm2 die size Industry’s first 14 nm processor now in volume production 12 Agenda • Introduction • 2nd Generation Tri-gate Transistor • Logic Area Scaling • Cost per Transistor • Product Benefits • SoC Feature Menu 13 Minimum Feature Size 22 nm 14 nm Scale Transistor Fin Pitch 60 42 .70x Transistor Gate Pitch 90 70 .78x Interconnect Pitch 80 52 .65x nm nm Intel has developed a true 14 nm technology with good dimensional scaling 14 Transistor Fin Optimization 60 nm pitch 34 nm height Si Substrate Si Substrate 22 nm Process 14 nm Process 15 Transistor Fin Optimization 60 nm 42 nm pitch pitch 34 nm height Si Substrate Si Substrate 22 nm Process 14 nm Process Tighter fin pitch for improved density 16 Transistor Fin Optimization 42 nm 60 nm pitch pitch 42 nm 34 nm height height Si Substrate Si Substrate 22 nm Process 14 nm Process Taller and thinner fins for improved performance 17 Transistor Fin Optimization 42 nm 60 nm pitch pitch 42 nm 34 nm height height Si Substrate Si Substrate 22 nm Process 14 nm Process Reduced number of fins for improved density and lower capacitance 18 Transistor Fin Optimization Metal Gate Metal Gate Si Substrate Si Substrate 22 nm Process 14 nm Process 1st generation Tri-gate 2nd generation Tri-gate 19 Transistor Fin Optimization 22 nm Process 14 nm Process 1st generation Tri-gate 2nd generation Tri-gate 20 Interconnects 22 nm Process 14 nm Process 80 nm minimum pitch 52 nm (0.65x) minimum pitch 52 nm interconnect pitch provides better than normal interconnect scaling 21 SRAM Memory Cells 22 nm Process 14 nm Process .108 um2 .0588 um2 (Used on CPU products) (0.54x) 14 nm design rules + 2nd generation Tri-gate provides industry-leading SRAM density 22 Agenda • Introduction • 2nd Generation Tri-gate Transistor • Logic Area Scaling • Cost per Transistor • Product Benefits • SoC Feature Menu 23 Transistor Gate Pitch Scaling ~0.8x per generation 100 Gate Pitch (nm) 10 45 nm 32 nm 22 nm 14 nm 10 nm Technology Node Gate pitch scaling ~0.8x for good balance of performance, density and low leakage 24 Metal Interconnect Pitch Scaling ~0.7x per generation 100 Metal Pitch (nm) 10 45 nm 32 nm 22 nm 14 nm 10 nm Technology Node 14 nm interconnects scaling faster than normal for improved density 25 Logic Area Scaling Metric Gate Pitch Logic Metal Cell Pitch Height Logic Cell Width Logic area scaling ~ gate pitch x metal pitch 26 Logic Area Scaling 10000 Gate Pitch x Metal Pitch Intel 2 (nm ) ~0.53x per generation 1000 45/40 nm 32/28 nm 22/20 nm 16/14 nm 10 nm Technology Node Logic area continues to scale ~0.53x per generation 27 Logic Area Scaling 10000 Gate Pitch x Others Metal Pitch Intel (nm2) 1000 45/40 nm 32/28 nm 22/20 nm 16/14 nm 10 nm Technology Node In the past, others tended to have better density, but came later than Intel 45nm: K-L Cheng (TSMC), 2007 IEDM, p. 243 28nm: F. Arnaud (IBM alliance), 2009 IEDM, p. 651 28 20nm: H. Shang (IBM alliance), 2012 VLSI, p.129 Logic Area Scaling 10000 Gate Pitch x Others Metal Pitch Intel (nm2) 1000 45/40 nm 32/28 nm 22/20 nm 16/14 nm 10 nm Technology Node Intel continues scaling at 14 nm while other pause to develop FinFETs 45nm: K-L Cheng (TSMC), 2007 IEDM, p. 243 16nm: S. Wu (TSMC), 2013 IEDM, p. 224 28nm: F. Arnaud (IBM alliance), 2009 IEDM, p. 651 10nm: K-I Seo (IBM alliance), 2014 VLSI, p. 14 29 20nm: H. Shang (IBM alliance), 2012 VLSI, p.129 Logic Area Scaling 1st 10000 FinFET 1st Gate Pitch FinFET x Others Planar Metal Pitch Intel (nm2) 2nd FinFET 1000 45/40 nm 32/28 nm 22/20 nm 16/14 nm 10 nm Technology Node Intel is shipping its 2nd generation FINFETs before others ship their 1st generation 45nm: K-L Cheng (TSMC), 2007 IEDM, p. 243 16nm: S. Wu (TSMC), 2013 IEDM, p. 224 28nm: F. Arnaud (IBM alliance), 2009 IEDM, p. 651 10nm: K-I Seo (IBM alliance), 2014 VLSI, p. 14 30 20nm: H. Shang (IBM alliance), 2012 VLSI, p.129 Logic Area Scaling 10000 Q4 ’11 Gate Pitch 2015? x Others Metal Pitch 1H ’14 Intel 2 (nm ) Q2 ’14 1000 45/40 nm 32/28 nm 22/20 nm 16/14 nm 10 nm Technology Node Intel 14 nm is both denser and earlier than what others call “16nm” or “14nm” 45nm: K-L Cheng (TSMC), 2007 IEDM, p. 243 16nm: S. Wu (TSMC), 2013 IEDM, p. 224 28nm: F. Arnaud (IBM alliance), 2009 IEDM, p. 651 10nm: K-I Seo (IBM alliance), 2014 VLSI, p. 14 31 20nm: H. Shang (IBM alliance), 2012 VLSI, p.129 Agenda • Introduction • 2nd Generation Tri-gate Transistor • Logic Area Scaling • Cost per Transistor • Product Benefits • SoC Feature Menu 32 Cost per Transistor $ / mm2 (normalized) 100 10 1 90 nm 90 nm 65 nm 45 nm 32 nm 22 nm 14 nm 10 130 nm Wafer cost is increasing due to added masking steps 33 Cost per Transistor $ / mm2 mm2 / Transistor (normalized) (normalized) 100 1 10 0.1 1 0.01 90 nm 90 nm 65 nm 45 nm 32 nm 22 nm 14 nm 10 90 nm 90 nm 65 nm 45 nm 32 nm 22 nm 14 nm 10 130 nm 130 nm 14 nm achieves better than normal area scaling 34 Cost per Transistor $ / mm2 mm2 / Transistor $ / Transistor (normalized) (normalized) (normalized) 100 1 1 10 0.1 0.1 1 0.01 0.01 90 nm 90 nm 65 nm 45 nm 32 nm 22 nm 14 nm 10 90 nm 90 nm 65 nm 45 nm 32 nm 22 nm 14 nm 10 90 nm 90 nm 65 nm 45 nm 32 nm 22 nm 14 nm 10 130 nm 130 nm 130 nm Intel 14 nm continues to deliver lower cost per transistor 35 Agenda • Introduction • 2nd Generation Tri-gate Transistor • Logic Area Scaling • Cost per Transistor • Product Benefits • SoC Feature Menu 36 Transistor Performance vs. Leakage 65 nm 45 nm 32 nm 22 nm 14 nm 1x 0.1x 0.01x LowerLeakage Power 0.001x Higher Transistor Performance (switching speed) 14 nm transistors provide improved performance and leakage … 37 Transistor Performance vs. Leakage 65 nm 45 nm 32 nm 22 nm 14 nm Server 1x Computing Client 0.1x Computing 0.01x Mobile LowerLeakage Power Computing 0.001x Mobile Always-On Circuits Higher Transistor Performance (switching speed) … to support a wide range of products 38 Product Benefits Performance Active Power Performance per Watt (Includes performance increase) 2x 1x 10x Server Server Server Laptop Laptop Laptop Mobile Mobile Mobile ~1.6x 1x .25x 1x per gen. 45 nm 32 nm 22 nm 14 nm 45 nm 32 nm 22 nm 14 nm 45 nm 32 nm 22 nm 14 nm New technology generations provide improved performance and/or reduced power, but the key benefit is improved performance per watt 39 Product Benefits Performance per Watt 14 nm Intel® Core™ M processor delivers >2x improvement in performance per watt 10x Intel Core M processor • 2nd generation Tri-gate transistors with improved low voltage performance and >2x lower leakage Server Laptop • Better than normal area scaling Mobile • Extensive design-process co-optimization ~1.6x 1x per gen. • Microarchitecture optimizations for active 45 nm 32 nm 22 nm 14 nm power reduction Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark* and MobileMark*, are measured using specific computer systems, components, software, operations and functions.
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