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Technology Trends: DRAM Technology Trends: Storage

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Technology Trends: DRAM Technology Trends: Storage Recap of Last Lecture ECE 486/586 • “Old” view of computer architecture: – Instruction Set Architecture (ISA) design • “Real” computer architecture: Computer Architecture – Design to maximize performance within constraints: cost, power, and availability – Includes ISA, microarchitecture, hardware Lecture # 2 • Tasks of a computer architect: – Determine features needed by a market and incorporate those Spring 2015 features in the computer – Identify important technology scaling trends and adapt computer design accordingly Portland State University Lecture Topics Technology Trends: Transistor Counts • Trends in Semiconductor Technology • Transistor density increases by ~ 35% per year – Logic, DRAM and Storage Technology • Die size increase less predictable, ranging from 10% to 20% per year – Bandwidth and Latency scaling • Combined effect: – Transistors and Wires – On-chip transistor count increases by 40% to 55% per year (2x increase every 18 to 24 months) • Trends in power and Energy – Popularly known as Moore’s Law • Trends in Cost – Impact of time, volume and commoditization • What can we do with all these extra transistors: – Cost of an Integrated Circuit – More complex processors (e.g., deeper pipelines, SIMD units) – More general-purpose cores on a chip • Reference: Chapter 1: Sections 1.4, 1.5 and 1.6 (Pages 17 – 32) – More special-purpose cores (e.g., graphics) on a chip – Larger on-chip caches Technology Trends: DRAM Technology Trends: Storage • In 1990s, DRAM capacity was increasing by 60% per year Flash Memory: (quadrupling every 3 years) • Capacity increasing by 50 to 60% per year (doubling in < 2 years) • More recently, DRAM capacity increase has slowed down to • 15-20X cheaper/bit than DRAM 25% -- 40% (doubling every 2 to 3 years) • Increasing use as SSD in Laptops and as the only storage device in • Capacity increases will continue to slow down due to charge tablets and smartphones storage limits of the DRAM capacitors – DRAM may stop scaling before the end of this decade Magnetic Disk Technology: • Impact on Architecture: • Capacity increasing by 40% per year (doubling every 2 to 3 years) – Need to explore other memory technologies to replace DRAM as • 15-25X cheaper/bit then Flash the main memory • 300-500X cheaper/bit than DRAM • Most widely used in server and warehouse-scale storage Why care about Technology Trends? Bandwidth vs. Latency • Architect needs to be aware of technology trends to make • Bandwidth or throughput the correct design choices and trade-offs – Total work done in a given time – 10,000-25,000X improvement for processors • Product design begins 3 – 5 years before the product is – 300-1200X improvement for memory and disks expected to hit the market – Consistent technology trends help in knowing how a design would • Latency or response time behave in the future – Time between start and completion of an event – 30-80X improvement for processors – 6-8X improvement for memory and disks Bandwidth vs. Latency Technology Trends: Transistors • Scaling refers to reduction in integrated circuit feature size (in x or y dimension) – 1971: 10 micrometer – 2011: 32 nanometers • Transistor density (count per unit area) increases quadratically with feature size reductions (e.g. 2x density increase from 32 nm to 22 nm process technology) • Transistor speed typically increases linearly with decreasing feature size – Complex for multiple reasons including decrease in supply voltage Bandwidth improvements significantly outpace latency improvements Technology Trends: Wires Power & Energy: A Systems Perspective • Wire delays do not scale well with technology • System Needs: – Power needs to brought in and distributed around the chip – Delay proportional to Resistance * Capacitance – Power dissipated as heat needs to be removed – Wire lengths decrease with feature size reductions – But, resistance and capacitance per unit length increase • Considerations: – Peak Power • Power supply system needs to provision for peak power needs • Poor wire delay scaling compared to transistor scaling creates • If a processor attempts to draw more current than the supply can design challenges provide, there is a “voltage droop”, which leads to malfunction – Larger fractions of processor clock cycle consumed by signal – Thermal Design power (TDP) propagation delay on wires • Characterizes sustained power consumption • Determined by the capabilities of the cooling system • Lower than peak power, higher than average power consumption – Energy Efficiency • Considers power and execution time (Energy = Power * Time) Power vs. Energy Dynamic Energy and Power • Power poses operating constraints: • Dynamic energy – can only execute fast enough to max out the power delivery or – Transistor switches from 0 -> 1 or 1 -> 0 the cooling solution – ½ x Capacitive load x Voltage 2 • Energy is the ultimate metric – measures the “true” cost of performing a task – has a direct impact on battery lives (portable devices) and • Dynamic power electricity bills (servers) – ½ x Capacitive load x Voltage 2 x Frequency switched • Example: If processor A consumes 20% more power than processor B but finishes the task in 30% less time, its relative • Reducing clock rate reduces power, not energy energy is 1.2 * 0.7 = 0.84. Processor A is better, provided its • Reducing voltage reduces both power and energy higher power can be supported by the power delivery and cooling systems – Voltages have dropped from 5V to < 1V in 20 years Example Power Wall Question: • Until 2003, increases in Consider a processor which can operate in two different modes: (i) transistor count and Mode-1: a high voltage mode (1V, 3GHz), and (ii) Mode-2: a low frequency dominated voltage mode (0.75V, 2 GHz). How much savings in dynamic energy reductions in voltage => and dynamic power will the processor achieve by operating in net increase in power Mode-2 as compared to Mode-1? • Intel 80386 consumed ~ 2 W Answer: • 3.3 GHz Intel Core i7 2 2 consumes 130 W (Energy) mode2 /(ENERGY) mode1 = (0.75) /(1) = 0.56 44% energy savings • Heat must be dissipated from 1.5 x 1.5 cm chip 2 2 • This is the limit of what (Power) mode2 /(Power) mode1 = (0.75) (2) / (1) (3)= 0.375 can be cooled by air 62.5% power savings • Result: Clock speeds became stagnant from 2003 onwards Techniques to Reduce Power Static Power • Do nothing well: • Power consumed when the system is idle – Turn off the clock of inactive modules, e.g., idle FP units or cores – Current static x Voltage • Dynamic Voltage-Frequency Scaling: – Proportional to the number of transistors – Multiple operating modes with different voltages and frequencies – Increasing rapidly with larger on-chip SRAM caches – In periods of low activity, switch to lower voltage (frequency) • Low power memory states – DRAMs have a series of increasingly lower power modes • To cut down static power: – Switching from a low power mode to active mode consumes – Need to turn off the power supply to inactive modules extra latency (power gating ) • Overclocking – Turbo mode in Intel processors Cost and Price Trends Intel Pentium 4 and Pentium M Pricing • Impacted by time , volume , and commodification – Cost decreases with time due to: • Learning curve resulting in improved yields • Recognized opportunities for cost reductions – Cost decreases with volume due to: • Learning curve reached much faster • Purchasing and manufacturing efficiency • Reduction in amortized per unit cost of R&D – Cost decreases with commodification due to: • Multiple vendors producing large volumes of mostly identical products, leading to competition and price reduction • Intense competition results in lower profit margins and reduced prices Price reduces with time, as the manufacturing process matures and volume increases IC Manufacturing Example: Intel Sandy Bridge • Integrated circuit manufacturing starts from the production of silicon wafers • Silicon ingot is sliced into silicon wafers • Wafers go through multiple processing steps • Patterned wafers are tested and bad wafers are removed from the population • Good wafers are chopped into dies which go through another testing process • Good dies are packaged, re-tested and then sent to customers 280 dies/300 mm wafer, 32nm process technology Cost of an Integrated Circuit Cost of an Integrated Circuit Bose-Einstein formula: • Wafer yield: • accounts for wafers that are completely bad • Defects per unit area: • Measure of random manufacturing defects • 0.016-0.057 defects per square cm (2010) • N (Process complexity factor) • Measure of manufacturing difficulty • 11.5-15.5 (40 nm, 2010) Yield Example Yield Example Problem: Problem: Assume Wafer yield = 100% Assume Wafer yield = 100% Assume Defect Density = 0.031 per cm 2 Assume Defect Density = 0.031 per cm 2 Assume N= 13.5 Assume N= 13.5 Compare die yields for a die that is 1.5 cm on a side with a die that is 1 cm on a side? Compare die yields for a die that is 1.5 cm on a side with a die that is 1 cm on a side? Solution: Die A: 1.5 cm on a side Area = 1.5 2 = 2.25cm 2 Die Yield = 100% * 1/(1 + 0.031 * 2.25) 13.5 = 0.4 Yield Example Yield Example (cont.) Problem: Assume Wafer yield = 100% Problem: Assume Defect Density = 0.031 per cm 2 For the problem on previous page, compare the number of good dies for a 30 cm Assume N= 13.5 wafer in each case. Compare die yields for a die that is 1.5 cm on a side with a die that is 1 cm on a side? Solution: Die A: 1.5 cm on a side Area = 1.5 2 = 2.25cm 2 Die Yield = 100% * 1/(1 + 0.031 * 2.25) 13.5 = 0.4 Die B: 1 cm on a side Area = 1 2 = 1cm 2 Die Yield = 100% * 1/(1 + 0.031 * 1) 13.5 = 0.66 Yield Example (cont.) Yield Example (cont.) Problem: Problem: For the problem on previous page, compare the number of good dies for a 30 cm For the problem on previous page, compare the number of good dies for a 30 cm wafer in each case.
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