DOCSLIB.ORG

Electrical Characterization and Modeling of Low Dimensional Nanostructure FET Jae Woo Lee

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Electrical Characterization and Modeling of Low Dimensional Nanostructure FET Jae Woo Lee Electrical characterization and modeling of low dimensional nanostructure FET Jae Woo Lee To cite this version: Jae Woo Lee. Electrical characterization and modeling of low dimensional nanostructure FET. Autre. Université de Grenoble; 239 - Korea University, 2011. Français. NNT : 2011GRENT070. tel- 00767413 HAL Id: tel-00767413 https://tel.archives-ouvertes.fr/tel-00767413 Submitted on 19 Dec 2012 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. THÈSE Pour obtenir le grade de DOCTEUR DE LUNIVERSITÉ DE GRENOBLE Spécialité : Micro et Nano Électronique Arrêté ministériel : 7 août 2006 Présentée par Jae Woo LEE Thèse dirigée par Mireille MOUIS et Gérard GHIBAUDO préparée au sein du Laboratoire IMEP-LAHC dans l'École Doctorale EEATS Caractérisation électrique et modélisation des transistors à effet de champ de faible dimensionnalité Thèse soutenue publiquement le 5 décembre 2011 devant le jury composé de : M. Gérard GHIBAUDO DR CNRS Alpes-IMEP/INPG, Président M. Jong-Tae PARK Dr Incheon University, Rapporteur M. Jongwan JUNG Dr Sejong University, Rapporteur M. Gyu Tae KIM Dr Korea Univeristy, Co-directeur de thèse M. Laurent MONTÈS DR CNRS Alpes-IMEP/INPG, Membre Mme. Mireille MOUIS MCF INP Grenoble-IMEP, Directeur de thèse Thesis for the Degree of Doctor Electrical Characterization and Modeling of Low Dimensional Nanostructure FET by Jae Woo LEE School of Electrical Engineering Graduate School Korea University February 2012 " フB うB 繯B ̤⭆刱⎱B 獐B 吤B 轕B 艿B ⓸B 毗B B Electrical Characterization and Modeling of Low Dimensional Nanostructure FET f f f マB ⓸毗まB ˙轕獐吤B 轕艿⓸毗ぬ鹵B 髒瓤疴B 2012 ヽ 2 檷 Ŕǘ〖轕̰ 〖轕檌 銱䟽銱ガ˙轕ɬ 蠼 釃 羭f " " Electrical Characterization and Modeling of Low Dimensional Nanostructure FET Ph.D. Thesis Jae Woo, LEE Thesis Advisor Prof. Gyu Tae KIM School of Electrical Engineering, Korea University, Seoul 136-701, Republic of Korea " Prof. Mireille MOUIS (Dr. CNRS) and Prof. Gérard GHIBAUDO (Dr. CNRS) IMEP-LAHC, Grenoble INP-MINATEC, 3 Parvis Louis Néel, 38016 Grenoble, France " " This Ph.D thesis prepared at Korea University, Korea and at IMEP-LAHC laboratory, INP- Grenoble, France under co-supervising program. The journey is the reward. - Steve Jobs English Abstract At the beginning of this thesis, basic and advanced device fabrication process which I have experienced during study such as top-down and bottom-up approach for the nanoscale device fabrication technique have been described. Especially, lithography technology has been focused because it is base of the modern device fabrication. For the advanced device structure, etching technique has been investigated in detail. The characterization of FET has been introduced. For the practical consideration in the advanced FET, several parameter extraction techniques have been introduced such as Y- function, split C-V etc. FinFET is one of promising alternatives against conventional planar devices. Problem of FinFET is surface roughness. During the fabrication, the etching process induces surface roughness on the sidewall surfaces. Surface roughness of channel decreases the effective mobility by surface roughness scattering. With the low temperature measurement and mobility analysis, drain current through sidewall and top surface was separated. From the separated currents, effective mobilities were extracted in each temperature conditions. As temperature lowering, mobility behaviors from the transport on each surface have different temperature dependence. Especially, in n-type FinFET, the sidewall mobility has stronger degradation in high gate electric field compare to top surface. Quantification of surface roughness was also compared between sidewall and top surface. Low temperature measurement is nondestructive characterization method. Therefore this study can be a proper surface roughness measurement technique for the performance optimization of FinFET. As another quasi-1 D nanowire structure device, 3D stacked SiGe nanowire has been introduced. Important of strain engineering has been known for the effective mobility booster. The limitation of dopant diffusion by strain has been shown. Without strain, SiGe nanowire FET showed huge short channel effect. Subthreshold current was bigger than strained SiGe channel. Temperature dependent mobility behavior in short channel unstrained device was completely different from the other cases. Impurity scattering was dominant in short channel unstrained SiGe nanowire FET. Thus, it could be concluded that the strain engineering is not necessary only for the mobility booster but also short channel effect immunity. Junctionless FET is very recently developed device compare to the others. Like as JFET, junctionless FET has volume conduction. Thus, it is less affected by interface states. Junctionless FET also has good short channel effect immunity because off-state of junctionless FET is dominated pinch-off of channel depletion. For this, junctionless FET should have thin body thickness. Therefore, multi gate nanowire structure is proper to make junctionless FET. Because of the surface area to volume ratio, quasi-1D nanowire structure is good for the sensor application. Nanowire structure has been investigated as a sensor. Using numerical simulation, generation-recombination noise property was considered in nanowire sensor. Even though the surface area to volume ration is enhanced in the nanowire channel, device has sensing limitation by noise. The generation-recombination noise depended on the channel geometry. As a design tool of nanowire sensor, noise simulation should be carried out to escape from the noise limitation in advance. The basic principles of device simulation have been discussed. Finite difference method and Monte Carlo simulation technique have been introduced for the comprehension of device simulation. Practical device simulation data have been shown for examples such as FinFET, strongly disordered 1D channel, OLED and E-paper. Eqpvgpvu" k" " Dpoufout" " 1. Overview of Semiconductor Device Trends ................................................. 1" 1.1 Economical Consideration: Market Trend Overview ...................................................... 3" 1.2 Device Scaling.................................................................................................................. 5" 1.3 Short Channel Effects....................................................................................................... 7" 1.3.1 Threshold Voltage Shift, Punchthrough and Drain-induced Barrier Lowering .................. 8" 1.3.2 Velocity Saturation .............................................................................................................. 10" 1.3.3 Hot Carrier Effects ............................................................................................................... 12" 1.4 Challenges to Overcome Short Channel Effects ............................................................ 12" 1.4.1 High-k and Metal Gate ......................................................................................................... 12" 1.4.2 Silicon on Insulator .............................................................................................................. 14" 1.4.3 Multi Gate and Pseudo 1D Structure ................................................................................... 16" 1.5 Conclusion ...................................................................................................................... 18" References ............................................................................................................................ 19" 2. Nano-device Fabrication Technology .......................................................... 21" 2.1 Introduction .................................................................................................................... 23" 2.2 Top-down and Bottom-up .............................................................................................. 24" 2.2.1 Bottom-up approach ............................................................................................................. 24" 2.2.2 Top-down approach ............................................................................................................. 26" 2.2.3 Conclusion: Convergence of Top-down and Bottom-up ..................................................... 37" 2.3 Conclusion ...................................................................................................................... 38" References ............................................................................................................................ 39" 3. Characterization and Parameter Extraction of FET ................................ 43" 3.1 Introduction .................................................................................................................... 45" 3.2 Basic MOSFET Operation ............................................................................................. 46" 3.2.1 Linear Regime (at Small VD) ..............................................................................................
Load more

Recommended publications
  • Mack DFM Keynote
    The future of lithography and its impact on design Chris Mack www.lithoguru.com 1 Outline • History Lessons – Moore’s Law – Dennard Scaling – Cost Trends • Is Moore’s Law Over? – Litho scaling? • The Design Gap • The Future is Here 2 1965: Moore’s Observation 100000 65,000 transistors 10000 Doubling each year 1000 100 Components per chip per Components 10 64 transistors! 1 1959 1961 1963 1965 1967 1969 1971 1973 1975 Year G. E. Moore, “Cramming More Components onto Integrated Circuits,” Electronics Vol. 38, No. 8 (Apr. 19, 1965) pp. 114-117. 3 Moore’s Law “Doubling every 1 – 2 years” 25 nm 100000000000 10000000000 feature size + die size 1000000000 100000000 10000000 1000000 Today only lithography 100000 25 µm contributes 10000 1000 Componentsper chip 100 feature size + die size + device cleverness 10 1 1959 1969 1979 1989 1999 2009 2019 Year 4 Dennard’s MOSFET Scaling Rules Device/Circuit Parameter Scaling Factor Device dimension/thickness 1/ λ Doping Concentration λ Voltage 1/ λ Current 1/ λ Robert Dennard Capacitance 1/ λ Delay time 1/ λ Transistorpower 1/ λ2 Power density 1 There are no trade-offs. Everything gets better when you shrink a transistor! 5 The Golden Age 1975 - 2000 • Dennard Scaling - as transistor shrinks it gets: – Faster – Lower power (constant power density) – Smaller/lighter • Moore’s Law – More transistors/chip & cost of transistor = ‒15%/year • More powerful chip for same price • Same chip for lower price – Many new applications – large increase in volume 6 Problems with Dennard Scaling • Voltage stopped shrinking
    [Show full text]
  • Risk Factors
    Risk Factors •Today’s presentations contain forward-looking statements. All statements made that are not historical facts are subject to a number of risks and uncertainties, and actual results may differ materially. Please refer to our most recent Earnings Release and our most recent Form 10-Q or 10-K filing for more information on the risk factors that could cause actual results to differ. •If we use any non-GAAP financial measures during the presentations, you will find on our website, intc.com, the required reconciliation to the most directly comparable GAAP financial measure. Rev. 4/19/11 Today’s News The world’s first 3-D Tri-Gate transistors on a production technology New 22nm transistors have an unprecedented combination of power savings and performance gains. These benefits will enable new innovations across a broad range of devices from the smallest handheld devices to powerful cloud-based servers. The transition to 3-D transistors continues the pace of technology advancement, fueling Moore’s Law for years to come. The world’s first demonstration of a 22nm microprocessor -- code-named Ivy Bridge -- that will be the first high-volume chip to use 3-D Tri-Gate transistors. Energy-Efficient Performance Built on Moore’s Law 1 65nm 45nm 32nm 22nm 1x 0.1x > 50% 0.01x reduction Lower Active Power Active Lower Lower Transistor Leakage Transistor Lower Active Power per Transistor (normalized) Transistor per Power Active 0.001x Constant Performance 0.1 65nm 45nm 32nm 22nm Higher Transistor Performance (Switching Speed) Planar Planar Planar Tri-Gate Source: Intel 22 nm Tri-Gate transistors increase the benefit from a new technology generation Source: Intel Transistor Innovations Enable Technology Cadence 2003 2005 2007 2009 2011 90 nm 65 nm 45 nm 32 nm 22 nm Invented 2nd Gen.
    [Show full text]
  • 3D-AFM Measurements for Semiconductor Structures and Devices
    3D-AFM Measurements for Semiconductor Structures and Devices Ndubuisi G. Orji and Ronald G. Dixson Engineering Physics Division Physical Measurement Laboratory National Institute of Standards and Technology Gaithersburg, MD, 20899, USA Abstract This book chapter reviews different types of three-dimensional atomic force microscope (3D-AFM) measurements for semiconductor metrology. It covers different implementations of 3D-AFM, calibrations methods, measurement uncertainty considerations and applications. The goal is to outline key aspects of 3D-AFM for dimensional semiconductor measurements in a way that is accessible to both new and experienced users and gives readers a strong foundation for further study. Preprint version For published version see: N. G. Orji & R. G. Dixson “3D-AFM Measurements for Semiconductor Structures and Devices” In Metrology and Diagnostic Techniques for Nanoelectronics (eds. Z. Ma, & D. G. Seiler) (Pan Stanford, 2017). Official contributions of the U.S. Government, not subject to copyright. Certain commercial equipment, instruments, materials or companies are identified in this paper in order to specify the experimental procedure adequately, or to give full credit to sources of some material. Such identification is not intended to imply recommendation or endorsement by the National Institute of Standards and Technology, nor is it intended to imply that the materials or equipment identified are necessarily the best available for the purpose. 3D-AFM Measurements for Semiconductor Structures and Devices Table of
    [Show full text]
  • United States Securities and Exchange Commission Form
    UNITED STATES SECURITIES AND EXCHANGE COMMISSION Washington, D.C. 20549 FORM 8-K CURRENT REPORT Pursuant to Section 13 OR 15(d) of The Securities Exchange Act of 1934 Date of Report: November 20, 2014 (Date of earliest event reported) INTEL CORPORATION (Exact name of registrant as specified in its charter) Delaware 000-06217 94-1672743 (State or other jurisdiction (Commission (IRS Employer of incorporation) File Number) Identification No.) 2200 Mission College Blvd., Santa Clara, California 95054-1549 (Address of principal executive offices) (Zip Code) (408) 765-8080 (Registrant's telephone number, including area code) (Former name or former address, if changed since last report) Check the appropriate box below if the Form 8-K filing is intended to simultaneously satisfy the filing obligation of the registrant under any of the following provisions (see General Instruction A.2. below): [ ] Written communications pursuant to Rule 425 under the Securities Act (17 CFR 230.425) [ ] Soliciting material pursuant to Rule 14a-12 under the Exchange Act (17 CFR 240.14a-12) [ ] Pre-commencement communications pursuant to Rule 14d-2(b) under the Exchange Act (17 CFR 240.14d-2(b)) [ ] Pre-commencement communications pursuant to Rule 13e-4(c) under the Exchange Act (17 CFR 240.13e-4c)) Item 7.01 Regulation FD Disclosure The information in this report shall not be treated as filed for purposes of the Securities Exchange Act of 1934, as amended. On November 20, 2014, Intel Corporation presented business and financial information to institutional investors, analysts, members of the press and the general public at a publicly available webcast meeting (the "Investor Meeting").
    [Show full text]
  • ZERO DEFECTS November 2015 Entegris Newsletter
    ZERO DEFECTS November 2015 Entegris Newsletter CONTENTS Entegris Expands CMP Filtration Technology 1. Entegris News Solutions and Research, Analytical and Entegris Expands CMP Filtration Technology Solutions and Research, Manufacturing Capabilities in Taiwan Analytical and Manufacturing Capabilities in Taiwan Microcontamination Control business SmartStack® 300 mm Contactless unit, Clint Haris. “Entegris continues to HWS Launch @ SEMICON® Europa invest in people, technology and facilities 2. Yield Improvement in Asia to introduce new solutions for the Tackling Materials Contamination semiconductor market. As our customers Control Complexities Below 22 nm produce integrated circuits with smaller Entegris Announces New feature sizes, our nanofiber technology reduces the number of defect-causing VaporSorb™ TRK Filter for Entegris announced at the SEMICON® contaminants from reaching the wafer.” Advanced Yield Protection in Taiwan tradeshow the development of Semiconductor Lithography a platform of CMP filtration solutions The Entegris filter platform using NMB Processing using nano-melt-blown (NMB) filtration media now includes the Planargard® bulk, 5. Innovation technology, as well as the expansion of Solaris® point-of-tool and Planarcap® Diffusion, a Key Parameter to its CMP research, analytical services and point-of-dispense families to provide Understand Contamination manufacturing capabilities in Taiwan. contamination control solutions through- Phenomena in FOUPs: These investments enable the company out the CMP process area. Developed and - Part 1 – Polymer Transport to further serve the growing demand for manufactured in Taiwan, the NMB media Coefficients Obtention advanced CMP filtration solutions. utilizes the increased porosity of the nanofibers to reduce shear stress placed - Part 2 – Coefficients Application “CMP processes continue to grow in upon the slurry during transport and in Numerical Simulation complexity in both the materials used filtration operations.
    [Show full text]
  • Carbon Nanotube Based VLSI Interconnects Analysis and Design
    SPRINGER BRIEFS IN APPLIED SCIENCES AND TECHNOLOGY Brajesh Kumar Kaushik Manoj Kumar Majumder Carbon Nanotube Based VLSI Interconnects Analysis and Design SpringerBriefs in Applied Sciences and Technology More information about this series at http://www.springer.com/series/8884 Brajesh Kumar Kaushik Manoj Kumar Majumder Carbon Nanotube Based VLSI Interconnects Analysis and Design 1 3 Brajesh Kumar Kaushik Manoj Kumar Majumder Department of Electronics and Communication Engineering Indian Institute of Technology Roorkee Roorkee Uttarakhand India ISSN 2191-530X ISSN 2191-5318 (electronic) ISBN 978-81-322-2046-6 ISBN 978-81-322-2047-3 (eBook) DOI 10.1007/978-81-322-2047-3 Library of Congress Control Number: 2014946403 Springer New Delhi Heidelberg New York Dordrecht London © The Author(s) 2015 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. Exempted from this legal reservation are brief excerpts in connection with reviews or scholarly analysis or material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. Duplication of this publication or parts thereof is permitted only under the provisions of the Copyright Law of the Publisher’s location, in its current version, and permission for use must always be obtained from Springer.
    [Show full text]
  • Is Dark Silicon Useful? Harnessing the Four Horsemen of the Coming Dark Silicon Apocalypse
    Is Dark Silicon Useful? Harnessing the Four Horsemen of the Coming Dark Silicon Apocalypse Michael B. Taylor Computer Science & Engineering Department University of California, San Diego ABSTRACT continues but CMOS scaling ceases to provide the fruits that Due to the breakdown of Dennardian scaling, the percentage it once did. As in prior years, the computational capabilities of a silicon chip that can switch at full frequency is dropping of chips are still increasing by 2.8× per process generation; exponentially with each process generation. This utilization but a utilization wall [26] limits us to only 1.4× of this ben- wall forces designers to ensure that, at any point in time, efit { resulting in large swaths of our silicon area remaining large fractions of their chips are effectively dark or dim sili- underclocked, or dark { hence the term dark silicon [19, 8]. con, i.e., either idle or significantly underclocked. These numbers are easy to derive from simple scaling the- As exponentially larger fractions of a chip's transistors ory, which is a good thing, because it allows us to think in- become dark, silicon area becomes an exponentially cheaper tuitively about the problem. Transistor density continues to resource relative to power and energy consumption. This improve by 2× every two years, and native transistor speeds shift is driving a new class of architectural techniques that improve by 1.4×. But energy efficiency of transistors is im- \spend" area to \buy" energy efficiency. All of these tech- proving only by 1.4×, which, under constant power-budgets, niques seek to introduce new forms of heterogeneity into the results in a 2× shortfall in energy budget to power a chip at computational stack.
    [Show full text]
  • Intel Fellow, Technology and Manufacturing Group Director, Interconnect Technology and Integration
    Leading at the edge TECHNOLOGY AND MANUFACTURING DAY 14 nm technology leadership Dr. Ruth Brain Intel Fellow, Technology and Manufacturing Group Director, Interconnect Technology and Integration TECHNOLOGY AND MANUFACTURING DAY Disclosures Intel Technology and Manufacturing Day 2017 occurs during Intel’s “Quiet Period,” before Intel announces its 2017 first quarter financial and operating results. Therefore, presenters will not be addressing first quarter information during this year’s program. Statements in this presentation that refer to forecasts, future plans and expectations are forward-looking statements that involve a number of risks and uncertainties. Words such as “anticipates,” “expects,” “intends,” “goals,” “plans,” “believes,” “seeks,” “estimates,” “continues,” “may,” “will,” “would,” “should,” “could,” and variations of such words and similar expressions are intended to identify such forward-looking statements. Statements that refer to or are based on projections, uncertain events or assumptions also identify forward-looking statements. Such statements are based on management’s expectations as of March 28, 2017, and involve many risks and uncertainties that could cause actual results to differ materially from those expressed or implied in these forward-looking statements. Important factors that could cause actual results to differ materially from the company’s expectations are set forth in Intel’s earnings release dated January 26, 2017, which is included as an exhibit to Intel’s Form 8-K furnished to the SEC on such date. Additional information regarding these and other factors that could affect Intel’s results is included in Intel’s SEC filings, including the company’s most recent reports on Forms 10-K, 10-Q and 8-K reports may be obtained by visiting our Investor Relations website at www.intc.com or the SEC’s website at www.sec.gov.
    [Show full text]
  • [email protected] Hot Chips, August 22, 2017
    Norman P. Jouppi, Cliff Young, Nishant Patil, David Patterson, Gaurav Agrawal, Raminder Bajwa, Sarah Bates, Suresh Bhatia, Nan Boden, Al Borchers, Rick Boyle, Pierre-luc Cantin, Clifford Chao, Chris Clark, Jeremy Coriell, Mike Daley, Matt Dau, Jeffrey Dean, Ben Gelb, Tara Vazir Ghaemmaghami, Rajendra Gottipati, William Gulland, Robert Hagmann, C. Richard Ho, Doug Hogberg, John Hu, Robert Hundt, Dan Hurt, Julian Ibarz, Aaron Jaffey, Alek Jaworski, Alexander Kaplan, Harshit Khaitan, Andy Koch, Naveen Kumar, Steve Lacy, James Laudon, James Law, Diemthu Le, Chris Leary, Zhuyuan Liu, Kyle Lucke, Alan Lundin, Gordon MacKean, Adriana Maggiore, Maire Mahony, Kieran Miller, Rahul Nagarajan, Ravi Narayanaswami, Ray Ni, Kathy Nix, Thomas Norrie, Mark Omernick, Narayana Penukonda, Andy Phelps, Jonathan Ross, Matt Ross, Amir Salek, Emad Samadiani, Chris Severn, Gregory Sizikov, Matthew Snelham, Jed Souter, Dan Steinberg,Andy Swing, Mercedes Tan, Gregory Thorson, Bo Tian, Horia Toma, Erick Tuttle, Vijay Vasudevan, Richard Walter, Walter Wang, Eric Wilcox, and Doe Hyun Yoon [email protected] Hot Chips, August 22, 2017 A Golden Age in Microprocessor Design Proprietary + Confidential • Stunning progress in microprocessor design 40 years ≈ 106x faster! • Three architectural innovations (~1000x) • Width: 8->16->32 ->64 bit (~8x) • Instruction level parallelism: • 4-10 clock cycles per instruction to 4+ instructions per clock cycle (~10-20x) • Multicore: 1 processor to 16 cores (~16x) • Clock rate: 3 to 4000 MHz (~1000x thru technology & architecture) • Made possible by IC technology: • Moore’s Law: growth in transistor count (2X every 1.5 years) • Dennard Scaling: power/transistor shrinks at same rate as transistors are added (constant per mm2 of silicon) Source: John Hennessy, “The Future of Microprocessors,”Source: Lorem ipsum dolor Stanford sit amet, consectetur University, adipiscing March elit.
    [Show full text]
  • Introducing 5-Nm Finfet Technology in Microwind Etienne Sicard, Lionel Trojman
    Introducing 5-nm FinFET technology in Microwind Etienne Sicard, Lionel Trojman To cite this version: Etienne Sicard, Lionel Trojman. Introducing 5-nm FinFET technology in Microwind. 2021. hal- 03254444 HAL Id: hal-03254444 https://hal.archives-ouvertes.fr/hal-03254444 Submitted on 8 Jun 2021 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Introducing 5-nm FinFET technology in Microwind Etienne SICARD Lionel TROJMAN Professor Professor, INSA-Dgei, 135 Av de Rangueil ISEP -Institut Supérieur 31077 Toulouse – France d’Électronique de Paris, 10 rue de www.microwind.org Vanves, Issy les Moulineaux, email: Etienne.sicard@insa- 92130-France. toulouse.fr Email : [email protected] Abstract: This paper describes the implementation of a high performance FinFET-based 5-nm CMOS technology in Microwind. After a general presentation of the electronic market and the roadmap to 1- nm technology, design rules and basic metrics for the 5-nm node are presented. Concepts related to the design of FinFET and design for manufacturing are also described. The performances of a ring oscillator, basic cells and a 6-transistor RAM memory are also analyzed. Keywords: FinFET, CMOS design, 5-nm, Ring oscillator, interconnects, SRAM, logic gates Introduction Manufacturing smaller circuits begets the integration of more complex components to comply with a demand for an increased operating frequency and reduced power consumption.
    [Show full text]
  • The Future of Semiconductor Intellectual Property Architectural Blocks in Europe
    The Future of Semiconductor Intellectual Property Architectural Blocks in Europe Author: Ilkka Tuomi Editor: Marc Bogdanowicz EUR 23962 EN - 2009 The Future of Semiconductor Intellectual Property Architectural Blocks in Europe Author: Ilkka Tuomi Editor: Marc Bogdanowicz 2009 EUR 23962 EN The mission of the JRC-IPTS is to provide customer-driven support to the EU policy-making process by developing science-based responses to policy challenges that have both a socio-economic as well as a scientific/technological dimension. European Commission Joint Research Centre Institute for Prospective Technological Studies Contact information Address: Edificio Expo. c/ Inca Garcilaso, 3. E-41092 Seville (Spain) E-mail: [email protected] Tel.: +34 954488318 Fax: +34 954488300 http://ipts.jrc.ec.europa.eu http://www.jrc.ec.europa.eu Legal Notice Neither the European Commission nor any person acting on behalf of the Commission is responsible for the use which might be made of this publication. Europe Direct is a service to help you find answers to your questions about the European Union Freephone number (*): 00 800 6 7 8 9 10 11 (*) Certain mobile telephone operators do not allow access to 00 800 numbers or these calls may be billed. A great deal of additional information on the European Union is available on the Internet. It can be accessed through the Europa server http://europa.eu/ JRC52422 EUR 23962 EN Catalogue number: LF-NA-23962-EN-C ISSN: 1018-5593 ISBN: 978-92-79-13058-8 DOI: 10.2791/13315 Luxembourg: Office for Official Publications of the European Communities © European Communities, 2009 Reproduction is authorised provided the source is acknowledged Printed in Spain Preface Over the last decades, developed economies have been undergoing a structural transformation towards knowledge economies.
    [Show full text]
  • Analysis of Local Interconnect Resistance at Scaled Process Nodes R
    Analysis of Local Interconnect Resistance at Scaled Process Nodes R. Pandey1, N. Agrawal1, R. Arghavani2 and S. Datta1 1The Pennsylvania State University, University Park PA 16802, USA; 2Lam Research, CA, USA. Email: [email protected] Introduction: M0/M1 local interconnects exhibit steadily increasing resistance with Line-width (LW) and Critical Dimension (CD) scaling. Enhanced electron scattering from metal surface and grain boundaries as well as increased volume of highly resistive liners/diffusion barriers in the interconnect bulk are key contributors for this trend [1]. Via0 resistance was identified as dominant component of local interconnect resistance at 22 nm process node [1]. Consequently at 14 nm process node back end of line (BEOL) process relaxes Via0 CD [2]. We show that with the latest trend of M0/M1 LW scaling along with Via0 and Contact CD scaling, M0 and Contact emerge as prominent contributors to local interconnect resistance at 5 nm process node. We present comprehensive analysis of local interconnect resistance for interconnects fabricated from both dual damascene and single damascene processes. Additionally, we investigate impact of replacing Tungsten in Contact and M0 line by a lower resistivity Tungsten, at 5 nm process, and quantify subsequent improvement in transistor on-state performance. Local Interconnect Simulation: Numerical simulator Sentaurus TCAD [3] is used to model transport in 3- Dimensional (3D) M0/M1 local interconnect structure (Fig.1 (a)), with technology scaling from 22 nm to 5 nm node. In dual damascene (DD) interconnect (Fig. 1(b)), both metal line and via are fabricated simultaneously. On the contrary, in single damascene (SD) process metal line and via are formed in separate steps which results in an additional Metal-Nitride liner in between metal line and via (Fig.
    [Show full text]