Introduction to Semiconductor Processing Brendan O'neill
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Fabrication of Nanoelectronic Devices and their Applications (Introduction to UE4008) Dr. Ray Duffy, Tyndall-U.C.C. 1 Silicon enables technology all around us I’ll be back Silicon transistor technology Scaling : Increasing performance and functionality This Silicon is in your phone now.... Easy to process, Well-known, Strong, Reliable Silicon we are working on at Tyndall-UCC SEM of fabricated test Substrate structure Metal Metal Silicon 3 20 nm lines 20 nm spaces 50 µm Silicon nanowires are in there Silicon isn’t going away soon.... Overview • Impact and Markets • Evolution of the MOS transistor • Future Directions • New device architectures • Replacing Si 7 Impact & Grand Challenges • 21st century society faces serious challenges : •Need to reduce CO2 emissions to combat climate change • An ageing population needs better healthcare and earlier diagnosis to prevent poor health • As the information highway expands, infrastructure must handle more data while consuming less energy • Ensuring safety and security in modern-day society and has become a substantial challenge 8 Markets 9 Markets 10 Markets 10.5 cm 10.5 cm × 6.8×109 = 7.14×105 km 11 Placed end-to-end : You are here Smartphones could reach to the moon and back 3.85 ×105 km 10.5 cm × 6.8×109 = 7.14×105 km 12 Evolution and revolution Price Performance Battery life time 13 Increasing functionality & performance Skynet’s roadmap : T-800 T-1000 T-X (Standard model) (Advanced) (Even more advanced) I’m back Increasing functionality & performance 14 Markets http://www.electroiq.com/articles/sst/print/volume-56/issue- 2/departments/news/10-ic-product-segments-to-exceed-total.html 15 16 Sales leaders : tool vendors 17 Overview • Impact and Markets • Evolution of the MOS transistor • Future Directions • New device architectures • Replacing Si 18 Background "Method and Apparatus for The first operational Ge transistor ; Controlling Electric Currents“ Julius Bardeen, Brattain, and Shockley, E. Lilienfeld, 1926 1947 19 Background “Cramming More Components Onto Integrated Circuits” G. E. Moore, Electronics, Volume 38, Number 8, April 19, 1965 Transistors × 2 every 2 years Moore’s Law I. Ferain et al. Nature, 2011 # transistors = 2300 # transistors > 2.5 billion Coming soon 10 µm process 22 nm process 14 nm 1971 2010 process 2016? 20 21 Power consumption Static power stars to be dominant in advanced technology nodes 22 Application : the field effect transistor MOSFET: Metal-Oxide-Semiconductor Field Effect Transistor Invented: Lilienfeld 1926. First made: Kahng, Attala 1960 Properties of a MOSFET: Small area Low power Simple technology Lower switching speed than bipolar device CMOS: Complementary MOS: NMOS + PMOS CMOS combines high packing density with low power 23 MOS operation : it’s a switch Log(IDS) VVGSGS >< = V 0T I VDS = VDD ON Oxide Metal Gate (Gate) Source Drain Source Drain IOFF VT VDD • We want VGS • ION high (speed) • IOFF low (power dissipation) 24 NMOS and PMOS transistors Free electron Free hole NMOS PMOS + + + - - - Conducts at +VG Conducts at -VG Vdd Vin PMOS Vout CMOS : B = nwell Vss Vdd NMOS + PMOS e.g. inverter Vin Vout n-well B = pwell p-substrate NMOS 25 Everything Scales Down • Minimum Feature Size • Film Thicknesses • Junction Depths • Power Supply Voltages 26 Scaling : Industrial motivation… $ Money $ More chips per Silicon area more profit $ Money $ Industry can put more functions on one chip cheaper products $ Money $ Scaled technologies are faster Digital revolution $ Scaled technologies dissipate less energy new (mobile) markets 27 Drive current means Circuit Speed Discharged capacitor Charged capacitor “0” “1” +++ “off-state” “on-state” Speed: • Time to switch from off-state to on-state vice versa • Time needed to (dis)charge the equivalent gate capacitor • Intrinsic gate delay t = charge/current = CV/I 28 Non-ideal MOSFET operation (tends to get worse as you scale down!!!) • Leakage currents • junction leakage, gate-induced drain leakage, gate current • Short channel effects • drain-induced barrier lowering, VT rolloff, reverse short channel effect, change of swing and body factor, punchthrough • MOSFET degradation • Hot carrier degradation, stress-induced leakage current, oxide breakdown, negative bias temperature instabilities 29 Short-channel effects (SCE) : The gate loses control V Ioff Ion GS 103 Gate VDS 102 ) S D 101 W = m m) FIN / 8 nm 0 42 nm A A/ 10 22 nm ( 32 nm ( 32 nm -1 22 nm DS V DS 10 I 42 nm Depletion regions GS I 8 nm Lgate ↑ -2 10 Gate VDS L V =DS 40=V nmDD G -3 10 S D 0.0 0.2 0.4 0.6 0.8 1.0 V (V) G 30 Two gates are better than one Gate Gate S D S D I Ion on Ioff Ioff 31 The FinFET/MugFET concept source box buried oxide drain scalable automatically self-aligned process simplicity, close to standard CMOS processing double-gate, triple-gate 32 Cross-sections through a FinFET Through gate Tilted top view B’ NiSi NiSi poly-Si NiSi Gate Source Drain High-k + MG B 20 nm Si Fin Buried oxide 33 Cross-sections through a FinFET Through fin A-A’ Tilted top view NiSi A’ A Poly-Si Gate Fin 34 (September 2012) “TSMC integrates Ge on Si in p-type FinFETs” “GlobalFoundries tips 14 nm FinFETs ….” 35 Overview • Impact and Markets • Evolution of the MOS transistor • Future Directions • New device architectures • Replacing Si 36 Evolution of MOS Transistors “Gate-all-Around” “3 Gates” “2 Gates” Gate Source Drain “1 Gate” ID Buried oxide Polysilicon Gate Gate Silicon Source Drain Fin BOX 20 nm Gate Gate Buried Oxide Gate Tri-Gate with 800C 600Torr 5min H2Anneal Source Drain Fins are 45x78nm, Nice corner rounding by H2 anneal Buried oxide Source Drain Back gate (substrate) Gate 38 39 40 Holy grail : Ge & III-Vs with Si Material Si Ge GaAs In0.53Ga0.47As InAs InSb Electron Mobility 1400 3900 8500 14000 40000 78000 (cm2/Vs) Hole mobility 450 1900 400 300 500 850 (cm2/Vs) III-V n-FETs combined with Improved performance/power Ge p-FETs consumption ratio 41 Beyond 2020 Exploration of ideas capable of replacing CMOS technology in the 2020 timeframe and beyond Heterogeneous integration of new technologies with the CMOS platform Fundamental new approaches to information processing The state variable is something other than electronic charge Spin Molecular state Photons Phonons Mechanical state Quantum state 42 Top Down vs Bottom Up Even though “traditional” scaling ended at the 90nm node (according to Intel) The devices are still recognisable as MOS devices Bottom up research is looking at alternatives Graphene Carbon nanotubes Molecular Devices Single Electron Transistors Spin Devices Ferromagnetic Logic Devices 43 Graphite and graphene Carbon: Two allotropes – diamond & graphite Graphite: Semi-metal. Layered material where carbon atoms in each layer (graphene sheets) are arranged in honeycomb structure. Metal Semiconductor Graphite Energy band structure Dark: filled states Graphene: one carbon atom at each vertex Light: empty states 44 Graphene: 2D Carbon Electronics Recent work - : • Sheets one atom thick! • Max Current Densities J > 108 A/cm2 • μ ≈5,000 cm2V–1s–1 up to 300 K. Graphene Potential: S D • Room Temperature ballistic nano-interconnects SiO2 (90 nm or 300 nm) • Sensors (Micron-scale and nanoscale) Si (gate) • Field-effect Devices (bilayers) 45 Other 2D materials . TMDs (transition-metal dichalcogenides) show promise WITH a bandgap!!! . e.g. MoS2 . Only very early work done in this area . Flakes of material 46 TMD 2D materials Transition Chalcogens Metals 47 TMDs: from crystal to device Starting point… … Final Structure! • Cleaning of the surface; S Electrical Characterization: Mo • Metal deposition through IV Curves Extraction Lift-Off process; 6.15 Ang. 48 Overview • Impact and Markets • Evolution of the MOS transistor • Future Directions • Conclusions 49 Where will it end? • Research is currently handing over the 10 nm process which is scheduled for 2015 • 5 nm will be the 2019 process 50 Summary . Moore’s law just keeps going . Increasingly novel solutions are found . Lots of questions below 10 nm… . ….structures, materials, processes, metrology . Exciting times! 51 .