DOCSLIB.ORG

International Roadmap for Devices and Systems

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
International Roadmap for Devices and Systems INTERNATIONAL ROADMAP FOR DEVICES AND SYSTEMS 2020 EDITION BEYOND CMOS THE IRDS IS DEVISED AND INTENDED FOR TECHNOLOGY ASSESSMENT ONLY AND IS WITHOUT REGARD TO ANY COMMERCIAL CONSIDERATIONS PERTAINING TO INDIVIDUAL PRODUCTS OR EQUIPMENT. ii © 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. THE INTERNATIONAL ROADMAP FOR DEVICES AND SYSTEMS: 2020 COPYRIGHT © 2020 IEEE. ALL RIGHTS RESERVED. iii Table of Contents Acknowledgments .............................................................................................................................. vi 1. Introduction .................................................................................................................................. 1 1.1. Scope of Beyond-CMOS Focus Team .............................................................................................. 1 1.2. Difficult Challenges ............................................................................................................................ 2 1.3. Nano-information Processing Taxonomy........................................................................................... 4 2. Emerging Memory Devices ........................................................................................................... 4 2.1. Memory Taxonomy ............................................................................................................................ 5 2.2. Emerging Memory Devices ................................................................................................................ 6 2.3. Memory Selector Device .................................................................................................................. 17 2.4. Storage Class Memory .................................................................................................................... 20 3. Emerging Logic and Alternative Information Processing Devices ............................................... 27 3.1. Taxonomy ........................................................................................................................................ 27 3.2. Devices for CMOS Extension .......................................................................................................... 28 3.3. Beyond-CMOS Devices: Charge-Based .......................................................................................... 32 3.4. Beyond-CMOS Devices: Alternative Information Processing .......................................................... 36 4. Emerging Device-Architecture Interaction ................................................................................... 41 4.1. Introduction ...................................................................................................................................... 41 4.2. Analog Computing ........................................................................................................................... 43 4.3. Probabilistic Circuits ......................................................................................................................... 57 4.4. Reversible Computing...................................................................................................................... 59 4.5. Device-Architecture Interaction: Conclusions/Recommendations ................................................... 64 5. Beyond CMOS Devices for More-Than-Moore Applications ....................................................... 64 5.1. Emerging Devices for Security Applications .................................................................................... 64 6. Emerging Materials Integration ................................................................................................... 68 6.1. Introduction and Scope .................................................................................................................... 68 6.2. Challenges ....................................................................................................................................... 69 6.3. Technology Requirements and Potential Solutions ......................................................................... 70 6.4. Emerging/Disruptive Concepts and Technologies ........................................................................... 73 6.5. Conclusions and Recommendations ............................................................................................... 74 7. Assessment ................................................................................................................................ 74 7.1. Introduction ...................................................................................................................................... 74 7.2. NRI Beyond-CMOS Benchmarking ................................................................................................. 75 7.3. Archive of ITRS ERD Survey-Based Assessment ........................................................................... 77 8. Summary ................................................................................................................................ 80 9. Endnotes/References .................................................................................................................. 81 THE INTERNATIONAL ROADMAP FOR DEVICES AND SYSTEMS: 2020 COPYRIGHT © 2020 IEEE. ALL RIGHTS RESERVED. iv List of Figures Figure BC1.1 Relationship of More Moore, Beyond CMOS, and Novel Computing Paradigms and Applications (Courtesy of Japan beyond-CMOS group) .................................... 1 Figure BC2.1 Taxonomy of Emerging Memory Devices ................................................................. 6 Figure BC2.2. Taxonomy of Memory Select Devices .................................................................... 17 Figure BC2.3 Comparison of Performance of Different Memory Technologies ............................ 23 Figure BC3.1 Taxonomy of Options for Emerging Logic Devices ................................................ 27 Figure BC4.1. Conventional vs. Alternative Computing Paradigms .............................................. 42 Figure BC4.2 A Resistive Memory Crossbar = Solver is Illustrated ..................................... 45 Figure BC4.3 A Spiking CNN for Gesture Recognition with Local Learning ................................. 47 Figure BC4.4 One Generalized Instantiation of a Photonic MVM unit, with Wavelength Multiplexed Inputs and Outputs and a Coupler-based Tunable Array. Reproduced from931. ............................................................................................... 54 Figure BC4.5 Energy Dissipation per Stage vs. Frequency in an Adiabatic CMOS Shift Register .................................................................................................................. 61 Figure BC4.6 Energy dissipation of RQFP and irreversible AQFP 1-b full adders ....................... 62 Figure EMI1 Emerging Material Integration Promotes the Advancement of Existing Technologies .......................................................................................................... 69 Figure EMI2 An Example of the Role of Machine Learning in the Multiscale Simulation ............ 74 Figure BC7.1 (a) Energy versus Delay of a 32-bit ALU for a Variety of Charge- and Spin- based Devices; (b) Energy versus Delay per Memory Association Operation Using Cellular Neural Network (CNN) for a Variety of Charge- and Spin-based Devices1156 .............................................................................................................. 76 Figure BC7.2 (a) Survey of Emerging Memory Devices and (b) Survey of Emerging Logic Devices in 2014 ERD Emerging Logic Workshop (Albuquerque, NM) ................... 78 Figure BC7.3 Comparison of Emerging Memory Devices Based on 2013 Critical Review .......... 78 Figure BC7.4 Comparison of Emerging Logic Devices Based on 2013 ITRS ERD Critical Review: (a) CMOS Extension Devices; (b) Charge-based Beyond-CMOS Devices; (c) Non-charge-based Beyond-CMOS Devices ....................................... 79 THE INTERNATIONAL ROADMAP FOR DEVICES AND SYSTEMS: 2020 COPYRIGHT © 2020 IEEE. ALL RIGHTS RESERVED. v List of Tables Table BC1.1 Beyond CMOS Difficult Challenges .......................................................................... 3 Table BC2.1 Emerging Research Memory Devices—Demonstrated and Projected Parameters ............................................................................................................... 5 Table BC2.2 Experimental Demonstrations of Vertical Transistors in Memory Arrays ............... 18 Table BC2.3 Benchmark Select Device Parameters ................................................................... 18 Table BC2.4a Experimentally Demonstrated Two-terminal Memory Select Devices .................... 20 Table BC2.4b Experimentally Demonstrated Self-selecting Memory Devices (self-rectifying) ..... 20 Table BC2.5 Target Device and System Specifications for SCM ................................................ 22 Table BC2.6 Potential of Current Prototypical and Emerging Research Memory Candidates for SCM Applications .............................................................................................
Load more

Recommended publications
  • Monolithic Integration of a Novel Microfluidic Device with Silicon Light Emitting Diode-Antifuse and Photodetector
    ESSDERC 2002 Monolithic Integration of a Novel Microfluidic Device with Silicon Light Emitting Diode-Antifuse and Photodetector P. LeMinh, J. Holleman, J.W.Berenschot,N.R.Tas,A.vandenBerg MESA+ Research Institute, University of Twente, the Netherlands E-mail [email protected] Abstract developing an CMOS compatible etching recipe using Tetra Methyl Ammonium Hydroxide (TMAH). Light emitting diode antifuse has been integrated into In the next sections of the paper, fabrication process, a microfluidic device that is realized with extended some critical technological design parameters, electrical standard CMOS technological steps. The device and optical properties, few results on first applications comprises of a microchannel sandwiched between a will be described respectively. photodiode detector and a nanometer-scale diode antifuse light emitter. Within this contribution, the 2. Device realization device fabrication process, working principle and properties will be discussed. Change in the interference The realization of the device (figure 1) is a 10-mask fringe of the antifuse spectra has been measured due to process. The starting material is a 3-in silicon n-type the filling of the channel. Preliminary applications are wafer with standard doping. First of all, junction electroosmotic flow speed measurement, detection of photodiode areas were fabricated by implantation of absorptivity of liquids in the channel… boron. So as not to make any step height difference at the junction between n-type and p-type region, thick resist 1. Introduction was used as masking layer for the implantation. This is important to the evenness of the channel. The shape of Silicon is well-known as an electronic and mechanical the channel was then produced by shaping a layer of material but hardly ever used as an active optoelectronic 500nm thick LPCVD polysilicon deposited on top of the element, due to its inefficient radiative recombination first silicon rich nitride (SiRN) layer.
    [Show full text]
  • Memristor-The Future of Artificial Intelligence L.Kavinmathi, C.Gayathri, K.Kumutha Priya
    International Journal of Scientific & Engineering Research, Volume 5, Issue 4, April-2014 358 ISSN 2229-5518 Memristor-The Future of Artificial Intelligence L.kavinmathi, C.Gayathri, K.Kumutha priya Abstract- Due to increasing demand on miniaturization and low power consumption, Memristor came into existence. Our design exploration is Reconfigurable Threshold Logic Gates based Programmable Analog Circuits using Memristor. Thus a variety of linearly separable and non- linearly separable logic functions such as AND, OR, NAND, NOR, XOR, XNOR have been realized using Threshold logic gate using Memristor. The functionality can be changed between these operations just by varying the resistance of the Memristor. Based on this Reconfigurable TLG, various Programmable Analog circuits can be built using Memristor. As an example of our approach, we have built Programmable analog Gain amplifier demonstrating Memristor-based programming of Threshold, Gain and Frequency. As our idea consisting of Programmable circuit design, in which low voltages are applied to Memristor during their operation as analog circuit element and high voltages are used to program the Memristor’s states. In these circuits the role of memristor is played by Memristor Emulator developed by us using FPGA. Reconfigurable is the option we are providing with the present system, so that the resistance ranges are varied by preprogram too. Index Terms— Memristor, TLG-threshold logic gates, Programmable Analog Circuits, FPGA-field programmable gate array, MTL- memristor threshold logic, CTL-capacitor Threshold logic, LUT- look up table. —————————— ( —————————— 1 INTRODUCTION CCORDING to Chua’s [founder of Memristor] definition, 9444163588. E-mail: [email protected] the internal state of an ideal Memristor depends on the • L.kavinmathi is currently pursuing bachelors degree program in electronics A and communication engineering in tagore engineering college under Anna integral of the voltage or current over time.
    [Show full text]
  • Effects of Metal Contacts and Doping for High
    TW-P061 Effects of metal contacts and doping for high-performance field-effect transistor based on tungsten diselenide (WSe2) Seo-Hyeon Jo and Jin-Hong Park School of Electronics and Electrical Engineering, Sungkyunkwan University, Suwon 440-746, Korea Transition metal dichalcogenides (TMDs) with two-dimensional layered structure, such as molybdenum disulfide (MoS2) and tungsten diselenide (WSe2), are considered attractive materials for future semiconductor devices due to its relatively superior electrical, optical, and mechanical properties. Their excellent scalability down to a monolayer based on the van der Waals layered structure without surface dangling bonds makes semiconductor devices based on TMD free from short channel effect. In comparison to the widely studied transistor based on MoS2, researchs focusing on WSe2 transistor are still limited. WSe2 is more resistant to oxidation in humid ambient condition and relatively air-stable than sulphides such as MoS2. These properties of WSe2 provide potential to fabricate high-performance filed-effect transistor if outstanding electronic characteristics can be achieved by suitable metal contacts and doping phenomenon. Here, we demonstrate the effect of two different metal contacts (titanium and platinum) in field-effect transistor based on WSe2, which regulate electronic characteristics of device by controlling the effective barreier height of the metal-semiconductor junction. Electronic properties of WSe2 transistor were systematically investigated through monitoring of threshold voltage shift, carrier concentration difference, on-current ratio, and field-effect mobility ratio with two different metal contacts. Additionally, performance of transistor based on WSe2 is further enhanced through reliable and controllable n-type doping method of WSe2 by triphenylphosphine (PPh3), which activates the doping phenomenon by thermal annealing process and adjust the doping level by controlling the doping concentration of PPh3.
    [Show full text]
  • Hybrid Memristor–CMOS Implementation of Combinational Logic Based on X-MRL †
    electronics Article Hybrid Memristor–CMOS Implementation of Combinational Logic Based on X-MRL † Khaled Alhaj Ali 1,* , Mostafa Rizk 1,2,3 , Amer Baghdadi 1 , Jean-Philippe Diguet 4 and Jalal Jomaah 3 1 IMT Atlantique, Lab-STICC CNRS, UMR, 29238 Brest, France; [email protected] (M.R.); [email protected] (A.B.) 2 Lebanese International University, School of Engineering, Block F 146404 Mazraa, Beirut 146404, Lebanon 3 Faculty of Sciences, Lebanese University, Beirut 6573, Lebanon; [email protected] 4 IRL CROSSING CNRS, Adelaide 5005, Australia; [email protected] * Correspondence: [email protected] † This paper is an extended version of our paper published in IEEE International Conference on Electronics, Circuits and Systems (ICECS) , 27–29 November 2019, as Ali, K.A.; Rizk, M.; Baghdadi, A.; Diguet, J.P.; Jomaah, J. “MRL Crossbar-Based Full Adder Design”. Abstract: A great deal of effort has recently been devoted to extending the usage of memristor technology from memory to computing. Memristor-based logic design is an emerging concept that targets efficient computing systems. Several logic families have evolved, each with different attributes. Memristor Ratioed Logic (MRL) has been recently introduced as a hybrid memristor–CMOS logic family. MRL requires an efficient design strategy that takes into consideration the implementation phase. This paper presents a novel MRL-based crossbar design: X-MRL. The proposed structure combines the density and scalability attributes of memristive crossbar arrays and the opportunity of their implementation at the top of CMOS layer. The evaluation of the proposed approach is performed through the design of an X-MRL-based full adder.
    [Show full text]
  • The Memristor: Anew Bond Graph Element D
    Paper No. n-Aut·N J The Society shall not be responsible for statements or opinions :<;111 pnp~,r~ or, in'Ldisao~slofl at me~,~in~s~f t~~ <~~,~iety, o,~, ot ,.its (I',~l)o'isjons:"or S,ecti ons;) lor- prlrU9d;:)ln tts j:~obllcaJLors. G. F.OSTER The Memristor: ANew Bond Graph Element D. M. AUSLANDER Mechanical Engineering Department. The "mcmris[.or," first deft ned by L. Clma for electrical drwits, 1·$ proposed as a new University of California, Berkeley, bond gra,ph clemel/t, on (1.11- equul footiug with R, L, & C, and having some unique Calif. modelling capubilities for nontinear systems. The Missing Constitutive Relation circuit thcory; howevcr, if wc look beyond the electrical doma.in it is not hard 1.0 find systems whose characteristics are con­ Ix HIS original lecture notes int.roducing the bond veniently represented by a memristor modcl. graph technique, Paynter drew a 1I1ctrahedron of state," (Fig. I) which sumnHlrir.cd j.he relationship between the sl.ate vl~riables Properties (c, I, p, q) [I, 2].1 There are G binary relationships possible be­ tween these 4 state variableii, Two of these are definitions: the The constitutive relation for a I-port memristor is a curve in the q-p ph~ne, Fig. 2. [n this context, we do not necessarily in_ displacement., q(t) = q(O) + f(t)clJ, and the qU:l.utit,y pet) = J:' terpret the quant.it,y p(l) = p(O) + ]:' e(t)dt as momentum, magneti(~ p(O) + }:' c(l)dt, which is interpreted ns momentum, flux, or pressure-momentum (2), buti merely as t.he integrated etTol't ("impulse!».
    [Show full text]
  • Nano Computing Revolution and Future Prospects
    Recent Research in Science and Technology 2012, 4(3): 16-17 ISSN: 2076-5061 Available Online: http://recent-science.com/ Nano computing revolution and future prospects Deepti Hirwani and Anuradha Sharma Maharaja Agrasen International College, Raipur C.G, India Abstract There are several ways nanocomputers might be built, using mechanical, electronic, biochemical, or quantum technology. It is unlikely that nanocomputers will be made out of semiconductor transistors (Microelectronic components that are at the core of all modern electronic devices), as they seem to perform significantly less well when shrunk to sizes under 100 nanometers.The research results summarized here also suggest that many useful, yet strikingly different solutions may exist for tolerating defects and faults within nanocomputing systems. Also included in the survey are a number of software tools useful for quantifying the reliability of nanocomputing systems in the presence of defects and faults. Keywords: Nano computing, electronic devices, technology INTRODUCTION classical computer would have to repeat 2 x input numbers, Nanocomputer is the logical name for the computer smaller performing the same task that a classical computer would have to then the microcomputer, which is smaller than the minicomputer. repeat 2 x times or use 2 xprocessors working in parallel. In other (The minicomputer is called “mini” because it was a lot smaller than words a quantum computer offers an enormous gain in the use of the original (mainframe) computers.) More technically, it is a computational resources such as time and memory. This becomes computer whose fundamental part is no bigger than a few mind boggling when you think of what 32 qubits can accomplish.
    [Show full text]
  • PPBI for OTP Fpgas Final Report
    ESA UNCLASSIFIED – For Official Use estec European Space Research and Technology Centre Keplerlaan 1 2201 AZ Noordwijk The Netherlands Tel. (31) 71 5656565 Fax (31) 71 5656040 www.esa.int PPBI for OTP FPGAs Final Report Prepared by: Ken Hernan Reference: ESCC WG 01/13 Issue: 1 Revision: 9 Date of Issue: 23rd May 2014 Status: Final Document Type: WG Report ESA UNCLASSIFIED – For Official Use ESA UNCLASSIFIED – For Official Use Table of contents: 1 INTRODUCTION ...................................................................................................................................................... 5 1.1 SCOPE OF THE DOCUMENT ..................................................................................................................................... 5 1.2 APPLICABLE AND REFERENCE DOCUMENTS ........................................................................................................... 5 1.2.1 Reference Documents (RDs) .......................................................................................................................... 5 1.3 ACRONYMS AND ABBREVIATIONS .......................................................................................................................... 6 2 EXECUTIVE SUMMARY ........................................................................................................................................ 9 3 WOKRING GROUP ACTIVITIES ........................................................................................................................ 15 4 BACKGROUND
    [Show full text]
  • Semiconductor Devices
    H01L CPC COOPERATIVE PATENT CLASSIFICATION H ELECTRICITY (NOTE omitted) H01 BASIC ELECTRIC ELEMENTS (NOTES omitted) H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR (use of semiconductor devices for measuring G01; resistors in general H01C; magnets, inductors, transformers H01F; capacitors in general H01G; electrolytic devices H01G 9/00; batteries, accumulators H01M; waveguides, resonators, or lines of the waveguide type H01P; line connectors, current collectors H01R; stimulated-emission devices H01S; electromechanical resonators H03H; loudspeakers, microphones, gramophone pick-ups or like acoustic electromechanical transducers H04R; electric light sources in general H05B; printed circuits, hybrid circuits, casings or constructional details of electrical apparatus, manufacture of assemblages of electrical components H05K; use of semiconductor devices in circuits having a particular application, see the subclass for the application) NOTES 1. This subclass covers: • electric solid state devices which are not covered by any other subclass and details thereof, and includes: semiconductor devices adapted for rectifying, amplifying, oscillating or switching; semiconductor devices sensitive to radiation; electric solid state devices using thermoelectric, superconductive, piezo-electric, electrostrictive, magnetostrictive, galvano- magnetic or bulk negative resistance effects and integrated circuit devices; • photoresistors, magnetic field dependent resistors, field effect resistors, capacitors with potential-jump
    [Show full text]
  • Recent Advancement in the Memristor Memory Development Ravikumar K
    International Journal of Innovative Technology and Exploring Engineering (IJITEE) ISSN: 2278-3075, Volume-9 Issue-7, May 2020 Recent Advancement in the Memristor Memory Development Ravikumar K. I, Sukumar R voltages as referred to in [19]) and d) manufacturing methods Abstract: Meritor is a newly-created tool and because of its compliant with CMOS relative to other NVM systems. nanometer scale and different electrical properties it has received Relative to other MRM (Resistive random access memory) much interest from advanced electronics designers since it was there are specific advantages. The RRAM is combined with discovered. The memory capacity of a memrist is one of the most significant features. In this paper, about 50 papers on designing the SRAM cell in past works such as [20–23], but each of memristor, optimization rules for reducing power, area for configuration either contributes to substantial deterioration of storing the data into memristor and implemented the full adders the fundamental SRAM reading process or absorbs a huge using memristor using the Pspice simulator. The paper ultimately amount of energy for the storage / restoration of data to / from addresses the complex study lapses and obstacles in constructing RRAM as described further in depth in section 4. In our paper the memorial that will enable scholars and thinkers lead to more analysis. we give a new NV-SRAM 8T1R that is similar to a standard Keywords: memristor, optimization. SRAM 6 T device with reading power, delay and noise tolerance. In turn, since only one RRAM cell is required for I. INTRODUCTION the off-time storage of SRAM data, energy used for processing RRAM data is reduced by more than 60% relative The resistive memory of the Crossbar has recently gained to the lowest energy density of previous RRAM NV-SRAM tremendous publicity owing to its amazing high density and designs.
    [Show full text]
  • Reliability Evaluation of Finfet-Based Srams in the Presence of Resistive Defects
    UNIVERSIDADE FEDERAL DO RIO GRANDE DO SUL INSTITUTO DE INFORMÁTICA PROGRAMA DE PÓS-GRADUAÇÃO EM MICROELETRÔNICA THIAGO SANTOS COPETTI Reliability Evaluation of FinFET-based SRAMs in the Presence of Resistive Defects Thesis presented in partial fulfillment of the requirements for the degree of PhD in Microelectronics Advisor: Prof. Dr. Tiago Roberto Balen Coadvisor: Profa. Dra. Letícia Maria Bolzani Poehls Porto Alegre February 2021 CIP — CATALOGING-IN-PUBLICATION Copetti, Thiago Santos Reliability Evaluation of FinFET-based SRAMs in the Pres- ence of Resistive Defects / Thiago Santos Copetti. – Porto Alegre: PGMICRO da UFRGS, 2021. 121 f.: il. Thesis (Ph.D.) – Universidade Federal do Rio Grande do Sul. Programa de Pós-Graduação em Microeletrônica, Porto Alegre, BR–RS, 2021. Advisor: Tiago Roberto Balen; Coadvisor: Letícia Maria Bolzani Poehls. 1. FinFET. 2. SRAM. 3. Resistive Defects. 4. SPICE. 5. TCAD. 6. Reliability. 7. Single Event Transient Modeling. I. Balen, Tiago Roberto. II. Poehls, Letícia Maria Bolzani. III. Tí- tulo. UNIVERSIDADE FEDERAL DO RIO GRANDE DO SUL Reitor: Prof. Carlos André Bulhões Vice-Reitora: Profa. Patricia Helena Lucas Pranke Pró-Reitor de Pós-Graduação: Prof. Júlio Otávio Jardim Barcellos Diretora do Instituto de Informática: Profa. Carla Maria Dal Sasso Freitas Coordenador do PGMICRO: Prof. Tiago Roberto Balen Bibliotecária-chefe do Instituto de Informática: Beatriz Regina Bastos Haro THIAGO SANTOS COPETTI Reliability Evaluation of FinFET-based SRAMs in the Presence of Resistive Defects Orientador: Dr. Tiago Roberto Balen Coorientador: Dra. Letícia Maria Bolzani Poehls Porto Alegre February 2021 DEDICATION I dedicate this work to my wife, my parents, and my siblings. “Nobody told me it was impossible, so I did” —JEAN COCTEAU ACKNOWLEDGMENT Firstly, I would like to thank my advisors and friends, Prof.
    [Show full text]
  • Memristor Nanodevice for Unconventional Computing:Review and Applications Mahyar Shahsavari, Pierre Boulet
    Memristor nanodevice for unconventional computing:review and applications Mahyar Shahsavari, Pierre Boulet To cite this version: Mahyar Shahsavari, Pierre Boulet. Memristor nanodevice for unconventional computing:review and applications . [Research Report] Université de Lille 1, Sciences et Technologies; CRIStAL UMR 9189. 2016. hal-01480614 HAL Id: hal-01480614 https://hal.archives-ouvertes.fr/hal-01480614 Submitted on 1 Mar 2017 HAL is a multi-disciplinary open access L’archive ouverte pluridisciplinaire HAL, est archive for the deposit and dissemination of sci- destinée au dépôt et à la diffusion de documents entific research documents, whether they are pub- scientifiques de niveau recherche, publiés ou non, lished or not. The documents may come from émanant des établissements d’enseignement et de teaching and research institutions in France or recherche français ou étrangers, des laboratoires abroad, or from public or private research centers. publics ou privés. Memristor nanodevice for unconventional computing: review and applications Mahyar Shahsavari, Pierre Boulet Univ. Lille, CNRS, Centrale Lille, UMR 9189 - CRIStAL Centre de Recherche en Informatique Signal et Automatique de Lille, F-59000 Lille, France. Abstract A memristor is a two-terminal nanodevice that its properties attract a wide community of re- searchers from various domains such as physics, chemistry, electronics, computer and neuroscience. The simple structure for manufacturing, small scalability, nonvolatility and potential of using in low power platforms are outstanding characteristics of this emerging nanodevice. In this report, we review a brief literature of memristor from mathematic model to the physical realization. We discuss different classes of memristors based on the material used for its manufacturing. The potential applications of memristor are presented and a wide domain of applications are explained and classified.
    [Show full text]
  • Exploring Optoelectronics Potential of Monolayer Tungsten Diselenide
    60 Technical focus: Optoelectronics Exploring optoelectronics potential of monolayer tungsten diselenide Three groups have recently reported on preliminary experiments with photovoltaic and light-emission effects from pn junctions created using split-gate electrostatic doping. Mike Cooke reports. esearchers are beginning to explore the semi- both convert light into current and current into light. conductor potential of monolayer materials The creation of n- and p-type conductivity in these Rbeyond graphene with hopes of developing devices was achieved electrostatically with a split gate robust devices that are flexible and transparent for beneath the WSe2 monolayer. deployment in wearable formats, interactive displays, Vienna University of Technology [Andreas Pospischil and efficient solar cells. et al, Nature Nanotechnology, vol 9 (2014), p257] An interesting class of materials that has recently come began its fabrication by forming a split gate of titanium/ to the fore is that of few-layer group-VIB transition-metal gold with a 460nm gap on a silicon/silicon dioxide dichalcogenides (TMDs) such as molybdenum disulfide wafer (Figure 1). Gate bonding pads were also formed (MoS2), molybdenum diselenide (MoSe2), tungsten with titanium/gold. The split gate was covered with disulfide (WS2), and tungsten diselenide (WSe2). silicon nitride, except for the bonding pads. The crystal structure consists of the metal atoms WSe2 flakes were exfoliated from bulk material sup- encapsulated between two layers of sulfur/selenium plied by Nanosurf onto a stack of polymer layers on a chalcogenide atoms. The bonding within a monolayer sacrificial silicon substrate. Suitable flakes were identi- is strong while the bonding between monolayers is fied under an optical microscope.
    [Show full text]