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PPBI for OTP Fpgas Final Report ESA UNCLASSIFIED – For Official Use estec European Space Research and Technology Centre Keplerlaan 1 2201 AZ Noordwijk The Netherlands Tel. (31) 71 5656565 Fax (31) 71 5656040 www.esa.int PPBI for OTP FPGAs Final Report Prepared by: Ken Hernan Reference: ESCC WG 01/13 Issue: 1 Revision: 9 Date of Issue: 23rd May 2014 Status: Final Document Type: WG Report ESA UNCLASSIFIED – For Official Use ESA UNCLASSIFIED – For Official Use Table of contents: 1 INTRODUCTION ...................................................................................................................................................... 5 1.1 SCOPE OF THE DOCUMENT ..................................................................................................................................... 5 1.2 APPLICABLE AND REFERENCE DOCUMENTS ........................................................................................................... 5 1.2.1 Reference Documents (RDs) .......................................................................................................................... 5 1.3 ACRONYMS AND ABBREVIATIONS .......................................................................................................................... 6 2 EXECUTIVE SUMMARY ........................................................................................................................................ 9 3 WOKRING GROUP ACTIVITIES ........................................................................................................................ 15 4 BACKGROUND ....................................................................................................................................................... 16 4.1 USE OF FPGAS IN SPACE APPLICATIONS ............................................................................................................. 16 4.2 THE ANTIFUSE: A TECHNICAL BACKGROUNDER .................................................................................................. 17 4.3 ANTIFUSE VS MEMORY-BASED PROGRAMMABLE LOGIC ..................................................................................... 19 4.4 ANTIFUSE TECHNOLOGY ...................................................................................................................................... 21 4.5 EVOLUTION OF ANTIFUSE ALTERNATIVES ........................................................................................................... 23 4.6 GSFC NASA ADVISORY ..................................................................................................................................... 25 4.7 ESA ALERT .......................................................................................................................................................... 26 4.8 ESA FPGA POLICY .............................................................................................................................................. 27 5 WORK LOGIC ......................................................................................................................................................... 29 5.1 MICROSEMI QUALITY MANAGEMENT SYSTEM (QMS) ........................................................................................ 29 5.1.1 Microsemi Quality Certificates .................................................................................................................... 29 5.1.2 Quality System .............................................................................................................................................. 29 5.1.3 Qualification Program ................................................................................................................................. 30 5.1.4 Quality & Reliability Testing ....................................................................................................................... 38 5.1.4.1 High Temperature Operating Life (HTOL)................................................................................................................ 38 5.1.4.2 Blank Level Burn-in .................................................................................................................................................. 40 5.1.4.2.1 Burn-In Types ..................................................................................................................................................... 40 5.1.4.2.2 Burn-In Procedure ............................................................................................................................................... 41 5.1.4.3 Other FPGA Test Modes ........................................................................................................................................... 41 5.1.4.4 RTSX-SU Voltage Acceleration ................................................................................................................................ 44 5.1.4.5 Microsemi Accelerated Reliability Testing ................................................................................................................ 45 5.1.4.6 Enhanced Antifuse Qualification (EAQ) ................................................................................................................... 47 5.1.4.6.1 High Stress Test Designs .................................................................................................................................... 47 5.1.4.6.2 EAQ Test Method ............................................................................................................................................... 50 5.1.4.7 Enhanced Lot Acceptance (ELA) .............................................................................................................................. 51 5.1.4.7.1 ELA Cross Section Analysis ............................................................................................................................... 52 5.1.4.7.2 ELA HTOL Test ................................................................................................................................................. 52 5.1.4.7.3 Thermal Runaway Characterisation Test ............................................................................................................ 52 5.1.4.7.4 ELA HTOL Test Design ..................................................................................................................................... 52 5.1.4.7.5 ELA HTOL Test Method .................................................................................................................................... 53 5.1.4.7.6 ELA HTOL Results ............................................................................................................................................ 53 5.2 MEC ANTIFUSE TECHNOLOGY ............................................................................................................................ 54 5.2.1 MEC Antifuse : Construction ....................................................................................................................... 54 5.2.2 MEC Antifuse : Failure Mechanism ............................................................................................................. 54 Page 2/114 Title: PPBI for OTP FPGAs Date: 23rd May 2014, Issue-1, Rev-9 ESA UNCLASSIFIED – For Official Use ESA UNCLASSIFIED – For Official Use 5.2.3 MEC Antifuse : Reliability Data .................................................................................................................. 58 5.2.3.1 Independent Review on NASA Space Flight Missions .............................................................................................. 58 5.2.3.2 PPBI for RT54SX-S and A54SX-A Devices ............................................................................................................. 60 5.2.3.3 Thales CS & CNES RTSX-S Experience .................................................................................................................. 60 5.3 UMC ANTIFUSE TECHNOLOGY ............................................................................................................................ 60 5.3.1 UMC Antifuse : Construction ....................................................................................................................... 60 5.3.2 UMC Antifuse : Failure Mechanism ............................................................................................................ 62 5.3.3 MEC Antifuse versus UMC Antifuse Comparison ........................................................................................ 62 5.3.4 UMC Antifuse : Reliability Data .................................................................................................................. 63 5.3.5 Risk Minimisation of Antifuse Failures ........................................................................................................ 64 5.4 MICROSEMI OTP FPGA PROGRAMMING EQUIPMENT .......................................................................................... 66 5.4.1 Overview of OTP FPGA Programming Hardware ...................................................................................... 66 5.4.2 Overview of OTP FPGA Programming Software ........................................................................................ 67 5.4.3 Frequently Asked Questions on Silicon Sculptor Test, Calibration and Diagnostics .................................. 68 5.4.4 Reliability of OTP FPGA Programming Equipment ...................................................................................
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