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Zener Zap Anti-Fuse Trim in VLSI Circuits

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Zener Zap Anti-Fuse Trim in VLSI Circuits VLSI DESIGN (C) 1996 OPA (Overseas Publishers Association) Amsterdam B.V. 1996, Vol. 5, No. I, pp. 89-100 Published in The Netherlands under license by Reprints available directly from the publisher Gordon and Breach Science Publishers SA Photocopying permitted by license only Printed in Malaysia Zener Zap Anti-Fuse Trim in VLSI Circuits DONALD T. COMER* Brigham Young University, Provo, UT 84602 (Received 23 October 1994; In final form 10 April 1995) This paper presents an overview of Zener zap anti-fuse trim as used to achieve improved accuracy in precision integrated circuits. Because this technology spans design and manu- facturing, elements of design, layout, processing, and testing are included. The mechanism is defined and typical applications are discussed. Layout considerations of anti-fuse devices are summarized and complex trim networks and multiplexed control methods are presented. Both bipolar and CMOS process implementations are considered. The paper also contains a bibliography which includes U.S. patents, which make up a large part of the technical documentation of this technology. Keywords: Zener zap, anti-fuse, trim, precision integrated circuits, mixed signal circuits, VLSI circuits 1. INTRODUCTION cally targeted to achieve improvement in key param- eters such as the offset voltage of an op-amp, the absolute value of a reference voltage, or a specific The accuracy of analog integrated circuits is typically limited by poor control of the absolute value and delay time in a cascade of logic gates. matching tolerances of the integrated devices created The advent of mixed-signal VLSI has created a in the fabrication process. Although ratiometric de- renewed interest in inexpensive methods of trimming sign principles are used where possible, mismatching at the wafer level to improve yield. This is because in ratios can cause a loss of accuracy and poor yield the yields of digital circuits typically exceed those of to high accuracy specifications. analog circuits constructed on the same process [13]. Over the years, "trim" techniques have been devel- Since most mixed-signal integrated circuits are size- oped to improve the accuracy and yield of integrated dominated by digital circuits, the failure of a small circuits. In this context trimming refers to making analog section of a chip to meet accuracy require- adjustments to the integrated circuit after its fabrica- ments can have drastic implications on the yield eco- tion has been completed. Trimming is typically done nomics of a mixed-signal design. at the wafer level on individual die but may even be A widely used method of trimming integrated cir- performed on die after packaging. Trimming is typi- cuits is laser trimming of thin film resistors [1]. By *Fax: (801) 378-6586 E-mail: [email protected]. 89 90 D.T. COMER selectively evaporating a small portion of the film low to moderate junction breakdown voltage. Histor- resistor with a laser beam, its effective value can be ically the Zener zap method has been used primarily increased. This method is used, for example, in on bipolar processes, where its use requires no addi- achieving high linearity in D/A converters, where tional or special processing steps. The primary focus several resistors must be trimmed to prescribed ratios of this paper is on the Zener zap method, although the [2]. basic resistor link trim methods discussed could be An alternative to laser trimming to achieve preci- used with other anti-fuse technologies. sion in integrated circuits is the anti-fuse approach which is the subject of this paper. This method is applicable to both bipolar and CMO$ designs and is 2. DESCRIPTION OF THE ZENER ZAP especially suited to mixed-signal A$IC products MECHANISM which do not lend themselves to laser trimming. The term is used to describe an element anti-fuse Fig. 1 shows a top view and a cross-section of a which initially appears as an open circuit but can be device used in a typical bipolar process to implement made to approach a short circuit by forcing conduc- the Zener zap anti-fuse. In this case the cathode of the tion of a high current for a short duration. Anti-fuse diode is created as a circular diffusion with a circular devices may be created in integrated circuits by three contact. The cathode is heavily doped N-material distinct methods. The first method utilizes a dielectric (typically 1-3 microns deep and 5-10 ohms per material to insulate two conductors, which can be ef- square) and is installed at the same process step as the fectively shorted together by electrically breaking emitter of a complete NPN device. The anode of the down the dielectric [14-15]. A second method is Zener device is created by a moderately doped based upon the use of amorphous silicon material, P-diffusion (typically 3-5 microns deep and 100-200 which in its normal state is an adequate insulator but ohms per square) and is installed at the same process can be rendered conductive by the application of suf- step as the base of a bipolar NPN device. ficiently strong fields and current flow [17-18]. The The equation governing the breakdown voltage of third method creates anti-fuse devices by forcing a the P-N junction is given by temporary avalanche breakdown in a P-N junction sufficient to cause localized heating and subsequent Cathode interconnect metal migration of metal across the junction. This method (emitter) of creating an anti-fuse came to be known in industry (base) jargon as "Zener zap" and in fact the Zener zap ter- minology is now used in technical literature as well anode interconnect metal [9-11]. (pocket) Although it is beyond the scope of this paper to make a quantitative comparison of the three anti-fuse approaches, it can be noted that the dielectric anti- (a) Top view fuse is dependent upon thinner oxides than utilizing cathode metal interconnect are available in most standard bipolar integrated cir- / anode metal interconnect / cuit processes and therefore tends to be used prima- oxide rily in CMOS and BiCMOS fabrication processes. n+ ) The amorphous silicon approach utilizes a material that is not commonly used in either bipolar or MOS integrated circuit processes and its use requires a spe- Epi-layer cial processing step in the fabrication cycle. The Ze- (b) Cross-section ner zap method requires a P-N junction device with a FIGURE Typical Bipolar Zener Device ANTI FUSE TRIM 91 .(N ND)Sc2rit The mechanism by which the transport of metal BV A (1) 2qNANo atoms takes place by momentum exchange with con- ducting electrons is investigated in the literature as - "electromigration" and is a very important factor in where e is the of and are permittivity silicon, NA No the reliability analysis of integrated circuit metaliza- the and donor densities of the P- and acceptor doping tion [9]. It occurs in metal lines at high current den- N- materials is the of an elec- respectively, q charge sities and elevated temperatures and consists of the tron, and is the maximum field that can be im- 'crit movement of metal atoms toward the positive termi- across the of the P-N pressed depletion region junc- nal of the conductor. Electromigration of aluminum tion without to avalanche breakdown leading [8]. generally occurs at current densities in excess of 105 For the case of a diode as doped suggested, No A;shcm2 and at temperatures in excess of 100C. be to >> NA, (1) may simplified Fig. 2 shows a top view and a cross section of a Zener zap device which has been fused by metal mi- gration. It is worth noting that the fused metal stripe occurs on and slightly below the surface of the silicon 2qNa. (2) but is below the layer of passivation normally used to seal out contaminants. No damage is caused to the Equation (2) indicates that the P- material doping passivation and the result is a structure with no di- will determine the junction breakdown and that a minished reliability as a result of the fusing mecha- higher doping will result in a lower breakdown volt- nism. age. The doping levels used in most bipolar and Bi- The amount of current required to cause fusing MOS processes create a breakdown voltage in the will vary with the process and device size. Small de- range of 6 to 7 volts. Furthermore, because most fab- vices constructed with no special optimizations for rication processes create a doping profile that results this application on a typical bipolar process will re- in maximum density at the surface of the doped ma- quire zap currents in the neighborhood of 100-200 terial, it follows that the voltage breakdown will oc- mA for a duration of a few milliseconds. It is possible cur at the surface of the vertical P-N junction. to design structures for a given process that will fuse The power dissipated by the junction at breakdown is given by (emitter) (base) P=BV.L (3) iiI iiiiiiiiiiiii./] anode interconnect metal where I is the current conducted across the junction l/ (pocket) during breakdown. If no limit is placed upon L the junction will heat very rapidly and can be destroyed by a number of mechanisms. On the other hand, if I is (a) Top view limited, the power P will cause localized heating cathode metal interconnect around the area where the current is concentrated. If I anode metal interconnect is applied for a fixed time, sufficient heating can oc- / cur to cause migration of atoms of the metal intercon- nect from the cathode terminal to the anode terminal of the diode along the path of breakdown current.
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