Europaisches Patentamt European Patent Office 0 Publication number: 0 528 417 A2 Office europeen des brevets

EUROPEAN PATENT APPLICATION

0 Application number: 92114148.7 int.Ci.5:G11C 17/16, H01L27/112

0 Date of filing: 19.08.92

0 Priority: 19.08.91 US 746824 0 Applicant: MICRON TECHNOLOGY, INC. 2805 East Columbia Road © Date of publication of application: Boise, ID 83706(US) 24.02.93 Bulletin 93/08 0 Inventor: Lowrey, Tyler A. 0 Designated Contracting States: 2599 E. Plateau DE Boise, Idaho 8371 2(US) Inventor: Lee, Ruojia 3351 Raindrop Dr. Boise, Idaho 83706(US)

0 Representative: Klunker . Schmitt-Nilson . Hirsch Winzererstrasse 106 W-8000 Munchen 40 (DE)

One-time, voltage-programmable, read-only memory array having igfets, each of which is coupled to a reference voltage line via an anti- element.

0 A one-time, voltage-programmable, read-only when subjected to a programming voltage. A series memory array in which individual memory cells com- of minimum pitch bitlines (48 + 49), which run prise an insulated-gate, field-effect , the parallel to the wordlines (33), completes the memory channel of which provides, through a voltage-prog- array. Each bitline (48 + 49) makes direct contact rammable anti-fuse element, a current path between with each pair of cell junctions along its length. The a reference voltage line (34) and a bitline (48 + 49). array is characterized by a non-folded bitline ar- In a preferred embodiment, the array comprises a chitecture. semiconductor substrate having a series of parallel, alternating, minimum-pitch field isolation regions (31) and active area strips (32), a series of parallel, minimum-pitch wordlines (33A-33F) overlying and CM perpendicular to the field isolation region (31) and < active area strips, the wordlines being insulated from the active areas by a gate dielectric layer (42) and being dielectrically insulated on their edges and up- per surfaces, source/drain junction regions (50) be- tween each wordline and field isolation 00 pair strip CM pair, a reference voltage line (34) between and co- 50B m extensive with every other wordline pair that makes anti-fusible contact to each subjacent pair of cell junctions along its length, anti-fusible contact for each cell being made within a trench that extends below junction depth, and is lined with conformal FIG. 4 silicon nitride dielectric layer (46) that breaks down

Rank Xerox (UK) Business Services (3. 10/3.5x/3.0. 1) 1 EP 0 528 417 A2 2

Field of the Invention suffer from several disadvantages. Reverse bias leakage will result in high background current val- This invention relates to tech- ues. In addition, the programming operation tends nology, one-time-programmable memory arrays, to stress the dielectric on cells which are to remain memory cells having an insulated-gate, field-effect 5 unshorted. Finally, it is difficult to balance the need transistor as the selective element, and a shortable to utilize a read voltage which will be sufficient to , or anti-fuse, as the programmable ele- trigger the column sense amps without exerting ment. undue stress on the dielectric of the unshorted cells during the useful life of the device. BACKGROUND OF THE INVENTION w The PROM cells described in U.S. Pat. Nos. 4,322,822 and 4,507,757 utilize a programmable Read Only Memory (ROM) are commonly used antifuse capacitor in combination with a MOS tran- to store programs in computer systems. Although sistor, which functions as the selection element. mask-programmed ROMs are the least expensive The first referenced patent discloses an when manufactured in high volume, they have the 75 electrically-programmable memory array having ca- disadvantages of high initial design cost and long pacitor devices formed in anisotropically etched V- lead time to manufacturing. Programmable ROMs grooves, which provide enhanced dielectric break- (PROMs), of which there are many types, have the down at the apex of the groove. After breakdown advantage of being field programmable. (i.e., programming), a cell exhibits a low resistance Bipolar PROMs, which incorporate bipolar fus- 20 to a grounded substrate. This cell structure is ible links or vertical shorting junction elements, somewhat difficult to manufacture, in that it re- have typically been used for high-speed applica- quires a highly-conductive, grounded substrate. Ad- tions, despite their relatively high manufacturing ditionally, the design does not lend itself to high cost, high power consumption, and low circuit den- density circuit layout. The second referenced pat- sity. Fusible links are particularly problematic. Not 25 ent ('757) discloses an electrically-programmable only are high current values required to blow the memory array having a thin-oxide avalanche fuse fusible links during programming, but the element which is programmed at voltage below the photolithographic and etch steps required for their oxide breakdown level. Such a design is extremely formation must be precisely controlled so as to susceptible to manufacturing process variability, minimize process variability. Unless link size and 30 since the avalanche phenomenon is difficult to con- shape is controlled within a narrow range, it will not trol. function effectively both as a conductor if not blown and as a completely open circuit if blown. Summary of the Invention Where speed is not of paramount importance, electrically-programmable ROMs (EPROMs) em- 35 The invention is an improved one-time, ploying floating gate technology have been typi- voltage-programmable, read-only memory array in cally employed. Such EPROMs feature greater cir- which individual memory cells comprise an cuit density than bipolar EPROMs, due to a more insulated-gate, field-effect transistor, the channel of compact cell design. However, the manufacture of which provides, through a voltage-programmable floating gate EPROMs requires complicated pro- 40 anti-fuse element, a current path between a refer- cessing. Additionally, data is retained in the floating ence voltage line and a bitline. The function of the gate, which is vulnerable to leakage and ultraviolet cell may be compared with that of a conventional radiation, either of which may result in the perma- dynamic random access memory (DRAM) cell. nent loss of data. In a DRAM cell, charge stored within a cell Various other PROM cells have been proposed 45 capacitor is accessed through an insulated-gate that utilize antifuse elements for the programmable field effect transistor (the access transistor), which link. Generally, the antifuse elements are essen- is turned on by activating a single word line. The tially , consisting of two conductive or cell capacitor has a node called the cell plate, semiconductive materials separated by a dielectric which is electrically common to all other cells with- layer. During programming, the dielectric layer is 50 in the array. The voltage of the cell plate is held to broken down by the application of a programming approximately Vcc/2 (Vcc being the voltage sup- voltage that is significantly greater than the normal plied to the chip). A "1 " is stored in the capacitor read voltage, thereby electrically connecting the of a memory cell by charging the cell capacitor's conducting materials. uncommon node, or storage-node plate, to Vcc For the PROM cells described in U.S. Pat. Nos. 55 through the access transistor. Likewise, a "0" is 3,634,929 and 4,499,557, an isolated is used stored by discharging the uncommon node to Vss - as the selection element and a capacitor is used as (generally ground potential) through the access the programmable antifuse element. Such designs transistor. The charge on the capacitor is read by

2 3 EP 0 528 417 A2 4 first equilibrating the cell plate and all digit lines to Brief Description of the Drawings Vcc/2. After the equilibration voltage is disconnect- ed from the digit lines and cell plate, the access Figure 1A is a proposed schematic symbol for a transistor is turned on, dumping the charge stored non-shorted antifuse element; in the cell's capacitor to an interconnected digit 5 Figure 1 B is a proposed schematic symbol for a line. If the uncommon node of the cell capacitor shorted antifuse element; had been charged to Vcc,the voltage on that digit Figure 2 is an abbreviated circuit schematic for line will be increased slightly, whereas if the un- the improved PROM array; common node had been grounded to Vss, the Figure 3 is a top plan view of a portion of the voltage on that digit line will be decreased slightly. io improved PROM array; and An adjacent digit line, to which no charge has been Figure 4 is a cross-sectional view through dumped during this read cycle, is used as a refer- broken line 4-4 of Figure 3, which fully depicts a ence. The voltage differential between the two digit single memory cell within the array. lines will be within a range of approximately 200 to 400mV. This differential voltage is then amplified is Preferred Embodiment of the Invention by cross-coupled N-channel and P-channel transis- tors (differential sense ), which pull the Since the charge storage characteristics of a digit line having the slightly lower voltage to Vss capacitor are typically immaterial to antifuse ele- and the digit line having the slightly higher voltage ment performance, the schematic representation of to Vcc.Once this has occurred, the voltages on the 20 such elements using capacitor symbols is some- digit lines is passed out of the array to a column what misleading. Given this realization, antifuse ele- decoder and read by an output buffer. ments have been variously represented with gate- Within the subject PROM array, cells have like and fuse-like symbols. Because of the need access , but no cell capacitor. A refer- within this disclosure to distinguish between short- ence voltage line common to all cells within the 25 ed and non-shorted antifuse elements, a new sym- array, provides a current source which is acces- bol is proposed. Figure 1A depicts a non-shorted sible through a particular cell access transistor only antifuse element, which consists of two curved if the programmable antifuse link within that cell is lines separated by a gap. Figure 1B, on the other shorted. Since a current source is accessed hand, depicts a shorted antifuse element, the dif- through the cell transistor, differential sense amps 30 ference being a dot which bridges the gap between are not required to sense a charge differential the two curved lines. between two bitlines. Instead, a far simpler current Referring now to the abbreviated circuit sche- sense amp may be used to determine cell logic matic of Figure 2, the improved PROM array is states. shown as comprising a series of non-intersecting For the preferred embodiment of the invention, 35 wordlines (WL1 , WL2, WL3, and WL4), a series of the array comprises a semiconductor substrate reference voltage lines (RL1 and RL2), each of having a series of parallel, alternating, minimum- which is located between every wordline pair, and pitch field isolation region and active area strips, a a series of non-intersecting bitlines (BL1 , BL2, BL3, series of parallel, minimum-pitch wordlines over- and BL4), which intersects the series of wordlines. lying and perpendicular to the field isolation region 40 One memory cell is associated with each wordline- and active area strips, the wordlines being insu- bitline intersection. For example, cell C1 is asso- lated from the active areas by a gate dielectric ciated with the intersection of wordline WL1 and layer and being dielectrically insulated on their bitline BL1 , cell C7 with the intersection of wordline edges and upper surfaces, source/drain junction WL3 and BL2, and cell 14 with the intersection of regions between each wordline pair and field isola- 45 wordline WL2 and BL4. Within each cell, a refer- tion strip pair, a reference voltage line between and ence voltage line is coupled to a bitline via an coextensive with every other wordline pair that antifuse link and a cell access transistor which is makes anti-fusible contact to each subjacent pair of gated by the wordline associated with that cell. For cell junctions along its length, anti-fusible contact example, in cell C1, reference voltage line RL1 is for each cell being made within a trench that ex- 50 coupled to bitline BL1 through antifuse link A1 and tends below junction depth, and is lined with con- access transistor Q1, which is gated by wordline formal silicon nitride dielectric layer that breaks WL1. If the antifuse link within a cell is shorted (i.e., down when subjected to a programming voltage. A conductive), then current from the reference volt- series of minimum pitch bitlines, which run parallel age line will flow to the bitline. However, if the to the wordlines, completes the memory array. 55 antifuse link is unshorted (i.e., an open circuit), no Each bitline makes direct contact with each pair of current will flow to the bitline. A "1 " is permanently cell junctions along its length. The array is char- written to a cell within the array by applying a acterized by a non-folded bitline architecture. voltage that is greater than the breakdown voltage

3 5 EP 0 528 417 A2 6 of the antifuse link to the bitline associated with self-aligned bitline contact etch is then performed that cell, and activating the wordline associated at the array locations 35, which are identified in with the cell. In this schematic, cells C1, C4, C8, Figure 3 with a circle having an "X" therein. A C9, C11, C12, C14, C15, and C16 are depicted as series of parallel bitlines which intersect wordlines having shorted antifuse links, while the remainder 5 33 and reference voltage lines 34 are then pat- of the cells are depicted as having unshorted links. terned from a refractory-metal-silicided second The preferred embodiment of the improved poly layer. Bitlines are thus formed which have a PROM array will now be described with reference second poly layer component 48 and a refractory to both Figure 3, which is a top plan view thereof metal silicide layer component 49. and Figure 4, which is a cross-sectional view io Referring now to figure 4, exclusively, it will be through broken line 4-4 of Figure 3. Although the noted that the trench in which reference voltage process utilized to fabricate the preferred embodi- line 34 rests serves a dual function. First, it elec- ment of the array is not within the scope of this trically isolates the cells associated with wordline disclosure, an abbreviated description of the pro- 33C from those associated with wordline 33D. Ad- cess will be provided that should be sufficient to 15 ditionally, it provides a relatively large surface area enable a semiconductor process engineer having for breakdown of the silicon nitride dielectric layer ordinary skill in his art to fabricate the array. Fea- 46 to occur during high voltage programming. The tures within the Figures will be given an item programmable antifuse link consists of the silicon number either between 31 and 39 if they are more nitride dielectric layer 46 between the reference readily discernable in Figure 3 or between 41 and 20 voltage line 34 and the adjacent transistor junction 50 if they are more readily discernable in Figure 4. 50B. An array fabrication process is employed, In order to program a particular cell, a selected which, at least through transistor formation, is very digitline and a selected wordline are both held at a similar—if not identical~to processes employed to programming potential of approximately 10-12 fabricate stacked-capacitor DRAM arrays. The ar- 25 volts, while unselected bitlines, unselected word- ray depicted will be fabricated utilizing N-channel lines, and reference voltage lines are held at devices. However, a functional array may also be ground potential. When this programming voltage fabricated on an N-type substrate by reversing is applied to a bitline and wordline pair, the access implant conductivity types. transistor of the cell so selected is completely Following the creation of a series of parallel, 30 turned on, and the dielectric in the antifuse link linear field oxide regions 31 in a lightly-doped P- ruptures (i.e., breaks down), forming a permanent type silicon substrate 41, a gate oxide layer 42 is conductive path from the reference voltage line to thermally grown on the surface of the active areas the adjacent transistor junction. 32 (the substrate regions between field oxide re- There are two basic methods for reading the gions 31). A series of wordlines 33A, 33B, 33C, 35 logic state stored within a particular cell. For the 33D, 33E, 33F....33n (where n is the total number first method, a selected bitline is held at ground of wordlines in the array) is patterned from a silicon potential. The voltage applied to the remaining bit- dioxide covered, refractory-metal-silicided first lines, although theoretically irrelevant from a logic polycrystalline silicon (poly) layer. Thus each con- standpoint, are also held at ground potential to ductive portion of a wordline comprises a poly 40 eliminate potential inter-circuit current leakage. A layer 43 and a silicide layer 44. Silicide layer 44 is selected wordline is held within a range of approxi- covered by a silicon dioxide layer 45. Source and mately 4-6 volts, while unselected wordlines are drain regions 50A, 50B are then created by im- held at ground potential. Voltage reference lines planting an N-type impurity such as phosphorus, are held within a range of approximately 2-3 volts. arsenic, or both. Wordline sidewall spacers are 45 If the antifuse link in a selected cell is shorted, utilized to appropriately offset the implants from the detectable current will flow from the reference volt- channel edges. From this point, the array fabrica- age line to the selected bitline. If, on the other tion process departs from DRAM process flows. hand, the antifuse link in the selected is not short- Active area regions between every other word- ed, no current will flow to the selected bitline. For line are then subjected to an anisotropic etch which 50 the second method of reading the cell logic state, a trenches the substrate below transistor junction selected bitline is held at a voltage level of 2-3 depth. These trenches are then lined with a con- volts, while unselected bitlines are once again held formal silicon nitride dielectric layer 46 that is ap- at ground potential to eliminate the possibility of proximately 50 to 100A in thickness. A series of inter-circuit current leakage. A selected wordline is parallel reference voltage lines 34 is then created 55 held within a range of approximately 4-6 volts, in the interwordline gaps where the silicon nitride while unselected wordlines are held at ground po- lined trenches have been created. The array is tential. Reference voltage lines are grounded. If the then covered with a dielectric isolation layer 47. A antifuse link in a selected cell is shorted, detect-

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able current will flow from the selected bitline to 6. The PROM array of Claim 5, wherein a particu- the reference voltage line. If, on the other hand, the lar cell within the array is programmable, such antifuse link in the selected is not shorted, no that a logic value of "1 " will be permanently current will flow to the reference voltage line. This stored therein, by applying a low voltage VL to second read method has an advantage over the 5 the reference voltage line and a high voltage first method, in that reference voltage line may VH to the bitline (48 + 49) associated with that remain permanently grounded. cell to be programmed, such that VH-VL is Although only a single embodiment of the im- greater than the breakdown voltage of the sili- proved PROM array has been disclosed, it will be con nitride dielectric layer (46); activating the obvious to those having ordinary skill in the art that io wordline associated with the cell to be pro- changes and modifications may be made thereto grammed so that substantially the entire poten- without departing from the spirit and scope of the tial VH-VL is applied across the antifuse link invention as claimed. For example, instead of which pertains to that cell, thus causing it to trenching the substrate beneath the reference volt- break down and form a permanent conductive age lines and placing the silicon nitride dielectric is path between the reference voltage line (34) layer beneath the reference voltage line, the sub- and the adjacent transistor junction (50B). strate beneath the bitline contact may be trenched and the silicon nitride placed beneath the bitline 7. The PROM array of Claim 5, wherein a particu- contact. However, such a modified cell design, lar cell within the array is programmable, such although workable in theory, would make program- 20 that a logic value of "1 " will be permanently ming a far more complicated task. stored therein, by grounding the voltage source lines (34) within the array; applying a Claims voltage higher than the breakdown voltage of the silicon nitride dielectric layer (46) to the 1. A one-time, voltage-programmable, read-only 25 bitline (48 + 49) associated with the cell to be memory (PROM) array having individual mem- programmed (the selected bitline); applying a ory cells each of which comprises an voltage to the wordline (33) associated with the insulated-gate, field-effect transistor (33 + 42 cell to be programmed (the selected wordline) + 50A + 50B), the channel of which provides, that is at least sufficient to activate the cell through a voltage-programmable anti-fuse ele- 30 access transistor of the cell to be programmed. ment (46), a current path between a reference voltage line (34) and a bitline (48 + 49). 8. The PROM array of Claim 7, wherein the volt- age applied to the selected bitline (48 + 49) is 2. The PROM array of Claim 1, wherein the an- substantially equal to the voltage applied to the tifuse element is a silicon nitride layer (46) 35 selected wordline. interposed between the reference voltage line (34) and an adjacent junction of the field-effect 9. The PROM array of Claim 8, wherein the volt- transistor (50B), said junction having been age applied to the selected bitline and the formed in a semiconductor substrate (41). selected wordline is within a range of 10-12 40 volts. 3. The PROM array of Claim 2, wherein shorting of the antifuse element during high-voltage 10. The PROM array of Claim 7, wherein the logic programming occurs on a substantially vertical value stored within a particular cell within the surface of a trench which extends vertically array may be read by applying a voltage to the into the substrate below the depth of said 45 wordline associated with the cell to be read adjacent junction (50B). (the selected wordline) that is sufficient to ac- tivate the transistors associated therewith; 4. The PROM array of Claim 3, which further maintaining unselected wordlines at a potential comprises a series of substantially parallel insufficient to activate the transistors associ- wordlines (33A-33F) patterned from a 50 ated therewith; applying a reference voltage to dielectrically-coated conductive layer. the reference voltage lines (34); placing the digitlines (48 + 49) at ground potential; and 5. The PROM array of Claim 4, wherein said determining whether or not current is flowing conductive layer comprises a conductively from the cell's reference voltage line to the doped polycrystalline silicon layer (43) and a 55 bitline associated with the cell to be read (the superjacent refractory metal silicide layer (44). selected bitline).

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11. The PROM array of Claim 10, wherein activa- tion voltage for a selected wordline during a cell read operation is within a range of 4-6 volts. 5 12. The PROM array of Claim 11, wherein refer- ence voltage lines (34) are held at a potential with a range of 2-3 volts.

13. The PROM array of Claim 7, wherein the logic 10 value stored within a particular cell within the array may be read by applying a voltage to the wordline associated with the cell to be read (the selected wordline) that is sufficient to ac- tivate the transistors associated therewith; is15 maintaining unselected wordlines at a potential insufficient to activate the transistors associ- ated therewith; grounding the reference voltage lines; applying a voltage of 2-3 volts to the bitline associated with the cell to be read (the 20 selected bitline); determining whether or not current is flowing from the selected bitline to the cell reference voltage line.

14. The PROM array of Claim 13, wherein activa- 25 tion voltage for a selected wordline during a cell read operation is within a range of 4-6 volts.

15. The PROM array of Claim 3, which is further 30 characterized by a non-folded bitline architec- ture.

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