Europaisches Patentamt European Patent Office 0 Publication number: 0 528 417 A2 Office europeen des brevets EUROPEAN PATENT APPLICATION 0 Application number: 92114148.7 int.Ci.5:G11C 17/16, H01L27/112 0 Date of filing: 19.08.92 0 Priority: 19.08.91 US 746824 0 Applicant: MICRON TECHNOLOGY, INC. 2805 East Columbia Road © Date of publication of application: Boise, ID 83706(US) 24.02.93 Bulletin 93/08 0 Inventor: Lowrey, Tyler A. 0 Designated Contracting States: 2599 E. Plateau DE Boise, Idaho 8371 2(US) Inventor: Lee, Ruojia 3351 Raindrop Dr. Boise, Idaho 83706(US) 0 Representative: Klunker . Schmitt-Nilson . Hirsch Winzererstrasse 106 W-8000 Munchen 40 (DE) One-time, voltage-programmable, read-only memory array having memory cell igfets, each of which is coupled to a reference voltage line via an anti-fuse element. 0 A one-time, voltage-programmable, read-only when subjected to a programming voltage. A series memory array in which individual memory cells com- of minimum pitch bitlines (48 + 49), which run prise an insulated-gate, field-effect transistor, the parallel to the wordlines (33), completes the memory channel of which provides, through a voltage-prog- array. Each bitline (48 + 49) makes direct contact rammable anti-fuse element, a current path between with each pair of cell junctions along its length. The a reference voltage line (34) and a bitline (48 + 49). array is characterized by a non-folded bitline ar- In a preferred embodiment, the array comprises a chitecture. semiconductor substrate having a series of parallel, alternating, minimum-pitch field isolation regions (31) and active area strips (32), a series of parallel, minimum-pitch wordlines (33A-33F) overlying and CM perpendicular to the field isolation region (31) and < active area strips, the wordlines being insulated from the active areas by a gate dielectric layer (42) and being dielectrically insulated on their edges and up- per surfaces, source/drain junction regions (50) be- tween each wordline and field isolation 00 pair strip CM pair, a reference voltage line (34) between and co- 50B m extensive with every other wordline pair that makes anti-fusible contact to each subjacent pair of cell junctions along its length, anti-fusible contact for each cell being made within a trench that extends below junction depth, and is lined with conformal FIG. 4 silicon nitride dielectric layer (46) that breaks down Rank Xerox (UK) Business Services (3. 10/3.5x/3.0. 1) 1 EP 0 528 417 A2 2 Field of the Invention suffer from several disadvantages. Reverse bias leakage will result in high background current val- This invention relates to integrated circuit tech- ues. In addition, the programming operation tends nology, one-time-programmable memory arrays, to stress the dielectric on cells which are to remain memory cells having an insulated-gate, field-effect 5 unshorted. Finally, it is difficult to balance the need transistor as the selective element, and a shortable to utilize a read voltage which will be sufficient to capacitor, or anti-fuse, as the programmable ele- trigger the column sense amps without exerting ment. undue stress on the dielectric of the unshorted cells during the useful life of the device. BACKGROUND OF THE INVENTION w The PROM cells described in U.S. Pat. Nos. 4,322,822 and 4,507,757 utilize a programmable Read Only Memory (ROM) are commonly used antifuse capacitor in combination with a MOS tran- to store programs in computer systems. Although sistor, which functions as the selection element. mask-programmed ROMs are the least expensive The first referenced patent discloses an when manufactured in high volume, they have the 75 electrically-programmable memory array having ca- disadvantages of high initial design cost and long pacitor devices formed in anisotropically etched V- lead time to manufacturing. Programmable ROMs grooves, which provide enhanced dielectric break- (PROMs), of which there are many types, have the down at the apex of the groove. After breakdown advantage of being field programmable. (i.e., programming), a cell exhibits a low resistance Bipolar PROMs, which incorporate bipolar fus- 20 to a grounded substrate. This cell structure is ible links or vertical shorting junction elements, somewhat difficult to manufacture, in that it re- have typically been used for high-speed applica- quires a highly-conductive, grounded substrate. Ad- tions, despite their relatively high manufacturing ditionally, the design does not lend itself to high cost, high power consumption, and low circuit den- density circuit layout. The second referenced pat- sity. Fusible links are particularly problematic. Not 25 ent ('757) discloses an electrically-programmable only are high current values required to blow the memory array having a thin-oxide avalanche fuse fusible links during programming, but the element which is programmed at voltage below the photolithographic and etch steps required for their oxide breakdown level. Such a design is extremely formation must be precisely controlled so as to susceptible to manufacturing process variability, minimize process variability. Unless link size and 30 since the avalanche phenomenon is difficult to con- shape is controlled within a narrow range, it will not trol. function effectively both as a conductor if not blown and as a completely open circuit if blown. Summary of the Invention Where speed is not of paramount importance, electrically-programmable ROMs (EPROMs) em- 35 The invention is an improved one-time, ploying floating gate technology have been typi- voltage-programmable, read-only memory array in cally employed. Such EPROMs feature greater cir- which individual memory cells comprise an cuit density than bipolar EPROMs, due to a more insulated-gate, field-effect transistor, the channel of compact cell design. However, the manufacture of which provides, through a voltage-programmable floating gate EPROMs requires complicated pro- 40 anti-fuse element, a current path between a refer- cessing. Additionally, data is retained in the floating ence voltage line and a bitline. The function of the gate, which is vulnerable to leakage and ultraviolet cell may be compared with that of a conventional radiation, either of which may result in the perma- dynamic random access memory (DRAM) cell. nent loss of data. In a DRAM cell, charge stored within a cell Various other PROM cells have been proposed 45 capacitor is accessed through an insulated-gate that utilize antifuse elements for the programmable field effect transistor (the access transistor), which link. Generally, the antifuse elements are essen- is turned on by activating a single word line. The tially capacitors, consisting of two conductive or cell capacitor has a node called the cell plate, semiconductive materials separated by a dielectric which is electrically common to all other cells with- layer. During programming, the dielectric layer is 50 in the array. The voltage of the cell plate is held to broken down by the application of a programming approximately Vcc/2 (Vcc being the voltage sup- voltage that is significantly greater than the normal plied to the chip). A "1 " is stored in the capacitor read voltage, thereby electrically connecting the of a memory cell by charging the cell capacitor's conducting materials. uncommon node, or storage-node plate, to Vcc For the PROM cells described in U.S. Pat. Nos. 55 through the access transistor. Likewise, a "0" is 3,634,929 and 4,499,557, an isolated diode is used stored by discharging the uncommon node to Vss - as the selection element and a capacitor is used as (generally ground potential) through the access the programmable antifuse element. Such designs transistor. The charge on the capacitor is read by 2 3 EP 0 528 417 A2 4 first equilibrating the cell plate and all digit lines to Brief Description of the Drawings Vcc/2. After the equilibration voltage is disconnect- ed from the digit lines and cell plate, the access Figure 1A is a proposed schematic symbol for a transistor is turned on, dumping the charge stored non-shorted antifuse element; in the cell's capacitor to an interconnected digit 5 Figure 1 B is a proposed schematic symbol for a line. If the uncommon node of the cell capacitor shorted antifuse element; had been charged to Vcc,the voltage on that digit Figure 2 is an abbreviated circuit schematic for line will be increased slightly, whereas if the un- the improved PROM array; common node had been grounded to Vss, the Figure 3 is a top plan view of a portion of the voltage on that digit line will be decreased slightly. io improved PROM array; and An adjacent digit line, to which no charge has been Figure 4 is a cross-sectional view through dumped during this read cycle, is used as a refer- broken line 4-4 of Figure 3, which fully depicts a ence. The voltage differential between the two digit single memory cell within the array. lines will be within a range of approximately 200 to 400mV. This differential voltage is then amplified is Preferred Embodiment of the Invention by cross-coupled N-channel and P-channel transis- tors (differential sense amplifiers), which pull the Since the charge storage characteristics of a digit line having the slightly lower voltage to Vss capacitor are typically immaterial to antifuse ele- and the digit line having the slightly higher voltage ment performance, the schematic representation of to Vcc.Once this has occurred, the voltages on the 20 such elements using capacitor symbols is some- digit lines is passed out of the array to a column what misleading. Given this realization, antifuse ele- decoder and read by an output buffer. ments have been variously represented with gate- Within the subject PROM array, cells have like and fuse-like symbols.