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Pure CMOS One-Time Programmable Memory Using Gate-Ox Anti-Fuse

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Pure CMOS One-Time Programmable Memory Using Gate-Ox Anti-Fuse IEEE 2004 CUSTOM INTEGRATED CIRCUITS CONFERENCE Pure CMOS One-time Programmable Memory using Gate-Ox Anti-fuse Hiroshi Ito, Toshimasa Namekawa SoC Research and Development Center, Toshiba Corporation 580-1, Horikawa-cho, Saiwai-ku, Kawasaki, 212-8520, Japan Abstract- A pure CMOS one-time programmable (PCOP) memory is developed as electrically programmable nonvolatile memory for general purposes. The memory cell consists of a thin- oxide PMOS transistor, a thick-oxide NMOS barrier transistor and a selection transistor. It is programmed with the dielectric breakdown of the thin gate oxide. A high voltage generator is si (b) built-in so as to be programmable after packaging. L-2 I. INTRODUCTION There are wide applications for small bit nonvolatile mem- ory such as trimming analog circuits, configuring digital circuits, chip ID, security code storage, and redundancy repair of SRAMDRAM. Fig. 1. Gate-oxide hard breakdown process For many years, DRAM’S have been using laser fuse for re- dundancy programming. The CMOS technology is continuing to be scaled down and device size is becoming smaller. On the other hand, the pitch of laser fuse is limited by the wavelength of laser and not scalable with recent advanced CMOS process. The laser fuse programming must be done on wafer state and specific fuse blow equipments are necessary. Electrically programmable nonvolatile memory is required in order to make possible post-package trimming, configura- tion, redundancy and so on. One or a few time programming is enough for most applications. Embedded Electrically Erasable PROM usually needs additional process and is much expen- sive. Some electrical fuse (eFuse) available in the standard CMOS process is desirable to meet the demands. Polysilicon fuse is one of the candidates for eFuse. Joule heating by large current changes the resistance of polysili- con fuse irreversibly. The polysilicon fuse programming is I . ....I . -7 dependent on many factors such as current density, current 0.1 1 10 100 1000 Time to breakdown [psec] pulse duration, fuse layout, polysilicon interconnect structure. Electro migration [ 11, salicide agglomeration [2] and segrega- Fig. 2. Weibull plot of TM tion have been reported as the mechanism of polysilicon fuse programming and the reliability of polysilicon fuse must be carefully confirmed. Another candidate for eFuse in standard CMOS process is 11. GATE-OXANTI-FUSE the anti-fuse using the gate-oxide of MOS transistor [3],[4]. Fig. 1 shows the process of the hard gate-oxide break- The mechanism of the anti-fuse programming is the hard down [5]. When voltage stress is applied to gate-oxide, defects 1 breakdown of gate-oxide. are generated. When the defect density reaches a certain ’ The gate-oxide dielectric breakdown has been investigated critical value, the current floods into the chain of defects and extensively from the viewpoints of MOS transistor reliability. with its thermal effect a conductive filament is formed in the The phenomenon of dielectric breakdown is well known. The gate oxide. post-hard-breakdown state of gate-oxide is very stable and can Fig. 2 shows the cumulative distribution of time to break- be used as a reliable eFuse. down (Tbd) in the case of PMOS transistor with 1.8nm-oxide 0-7803-8495-4/04/$20.0002004 IEEE. 20-4-1 469 1 0.8 E .-- g3 ._ 0.6 n m -=.m a 5 0.4 0 0.2 0 0 50 100 150 200 250 300 350 400 0 0.2 0.4 0.6 0.8 1 1.2 1.4 Rbd [MI Voltage PJ] Fig. 3. Distribution of Rbd Fig. 4. Ibd (post-breakdown current) characteristics thickness, fabricated with a 90nm standard CMOS process. The high voltage stresses (VBP= 5.6/5.8/6.0V) were applied VBP to the bodylsourceldrain of PMOS transistor with the gate P terminal grounded. The current at breakdown was limited to 2mA. Tbd is described well with the Weibull distribution even in such very short time range (< lms). n’ I Fig. 3 shows the cumulative distribution of post-breakdown resistance (Rbd), where Rbd is defined at 0.W bias of VBP. I 4 MP4 MP5 h The mode of Rbd was 20kR and the maximum was 420kR. Fig. 4 shows the post-breakdown current characteristics. The data indicated with circles were measured from a sample with the mode Rbd. The data measured from a sample with maximum Rbd are plotted with triangles and show a diode- like characteristic. It is considered that the difference is due to the location of the breakdown spots [6]. If the breakdown spot is located in the gate-source/drain overlap region, the gate current would behave ohmic. When the breakdown path is formed in the channel region, the breakdown spot may act as Fig. 5. eFuse element and S/A circuits an additional drain, then the gate current characteristics would resemble that of MOS transistor. 111. PCOP MEMORY By switching on the selection transistor MN1, the high programming voltage VBP will be applied to the gate-oxide A. eFuse Element of PMOS MPO and will cause a hard breakdown. The barrier An eFuse element using the gate-oxide anti-fuse is shown in transistor MNO limits the voltage of node nO to VBT-Vth, Fig. 5(a). It consists of a thin-oxide PMOS transistor, a thick- protecting the circuits other than the anti-fuse from high oxide NMOS barrier transistor and a selection transistor. voltage stress during the programming. The only one requirement of the eFuse element is dual Tox The level of the programming voltage VBP is chosen so that process. Recent CMOS technology has two kinds of oxide Tbd becomes less than loopsec (see the Weibull distribution thicknesses for internal logic circuits and U0circuits, because in Fig. 2). However the programming with dielectric break- of higher interface voltage than core voltage. It means that down is a stochastic process. It must be taken care of that some PCOP memory is available in the recent standard CMOS bits might not be broken in a predetermined programming technology without any additional process. time. The capability of “program verify” is necessary. 470 20-4-2 VSAREF 11VDD VREFGO DVREQO] : MemoryBlock DVREF[l] i Control Circui;, DVREF[f DVREQ3] ,64bit Memory Block 64bit Memory Block0 Fig. 6. S/A reference level generator B. Sensing Scheme Fig. 7. The block diagram of the PCOP memory macro Fig. 5(b) shows the sense amplifier (S/A) circuit of PCOP memory. The S/A is a differential latch type circuit with the reference level VSAREF. operation of the PCOP memory needs VDD power supply Fig. 6 shows the S/A reference level generator circuit. The only. VSAREF is generated dynamically with charge sharing, and is controlled by the digital signals DVREF’s. D. Programming and Venfy The sensing operation has two steps. In the first step, the Fig. 8 shows the detailed bit cell circuit schematics in the eFuse node nO is reset to GND level with the discharge transis- memory block. Each bit has a fuse data register and a program tor MN2. After the reset, the node voltage of programmed bit control register. begins to develop to VBP level (=VDD during read operation), Programming consists of the following two steps. First the while that of non-programmed bit stays near GND level. data are loaded to the fuse data registers from the serial input During sensing, the VBT level is higher than VDD to avoid SI. Secondly the program control input PI is set to VDD signal loss due to the Vthof the barrier transistor MNO. After a level and the program clock is toggled. The bits with data proper signal development time (SDT), S/A will be activated. register set to ”1” will be programmed bit by bit. During the The SDT is timed with counting the clock of an internal programming cycle of the last bit, the program over signal PO oscillator and can be controlled by changing counter initial goes to VDD. value. The values of VSAREF and SDT are optimized for Verifying programmed data has two steps also. Firstly eFuse being able to sense the high Rbd anti-fuse elements, which data are sensed with reduced ”1” data sense margin. The may have hard-breakdown spots in the channel region. purpose of reducing “1” sensing margin is to detect possible weakly programmed bits which might be soft breakdowned C. PCOP Memory Architecture but halted at the phase of Fig. l(b). The sensing margin is Fig. 7 shows the block diagram of the PCOP memory controlled with changing SDT and/or VSAREF. macro. The 64bit memory block is the basic unit, so the In the second step, the sensed data are compared to the granularity of the PCOP memory is 64 bit. The memory block contents of fuse data register to detect any program-failure. consists of 64 bit cell circuits and a control circuit including If the programming passes/fails, then “O”/”l” is reloaded to the S/A reference level generator. Each memory block is the fuse data register respectively. If there is no fail, the PO connected serially. It means that the PCOP memory is one goes to VDD as soon as the PI is set to VDD. If any failure long serial register. Plural PCOP memory macros can be daisy is detected, the PO stays at GND level when the PI is set to chained. VDD and failed ”1”s are re-programmed immediately. The charge pump circuits are built in for internal VBPNBT generation. They are Dickson-type charge pump circuits that E. Silicon use body-controlled PMOS transistors as transfer gate.
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