Fabrication and Modeling of Thin-Film Anodic Titania Memristors Kyle James Miller Iowa State University

Total Page:16

File Type:pdf, Size:1020Kb

Fabrication and Modeling of Thin-Film Anodic Titania Memristors Kyle James Miller Iowa State University View metadata, citation and similar papers at core.ac.uk brought to you by CORE provided by Digital Repository @ Iowa State University Iowa State University Capstones, Theses and Graduate Theses and Dissertations Dissertations 2010 Fabrication and modeling of thin-film anodic titania memristors Kyle James Miller Iowa State University Follow this and additional works at: https://lib.dr.iastate.edu/etd Part of the Electrical and Computer Engineering Commons Recommended Citation Miller, Kyle James, "Fabrication and modeling of thin-film anodic titania memristors" (2010). Graduate Theses and Dissertations. 11426. https://lib.dr.iastate.edu/etd/11426 This Thesis is brought to you for free and open access by the Iowa State University Capstones, Theses and Dissertations at Iowa State University Digital Repository. It has been accepted for inclusion in Graduate Theses and Dissertations by an authorized administrator of Iowa State University Digital Repository. For more information, please contact [email protected]. Fabrication and modeling of thin-film anodic titania memristors by Kyle Miller A thesis submitted to the graduate faculty in partial fulfillment of the requirements for the degree of MASTER OF SCIENCE Major: Electrical Engineering Program of Study Committee: Nathan Neihart, Co-Major Professor Sumit Chaudhary, Co-Major Professor Ayman Fayed Iowa State University Ames, Iowa 2010 Copyright © Kyle Miller, 2010. All rights reserved. ii TABLE OF CONTENTS LIST OF FIGURES ..................................................................................................... iv ACKNOWLEDGEMENTS ......................................................................................... vi ABSTRACT ................................................................................................................ vii CHAPTER 1. INTRODUCTION ................................................................................ 1 CHAPTER 2. REVIEW OF LITERATURE ............................................................... 3 2.1 Introduction ........................................................................................................ 3 2.2 Switching Mechanisms ...................................................................................... 6 2.3 Fabrication ....................................................................................................... 12 2.4 Modeling .......................................................................................................... 14 2.5 Applications ..................................................................................................... 18 2.6 Summary .......................................................................................................... 20 CHAPTER 3. METHODS AND PROCEDURES .................................................... 22 3.1 Introduction ...................................................................................................... 22 3.2 Fabrication ....................................................................................................... 22 3.3 Testing.............................................................................................................. 24 3.4 Modeling .......................................................................................................... 26 3.5 Summary .......................................................................................................... 28 CHAPTER 4. RESULTS ........................................................................................... 29 iii 4.1 Keithley Measurement Results ........................................................................ 29 4.2 Atomic Force Microscopy Results................................................................... 34 4.3 Ideal Matlab Modeling Results ........................................................................ 35 4.4 ORCAD Pspice Memristor Model ................................................................... 36 4.5 Summary .......................................................................................................... 40 CHAPTER 5. FUTURE WORK ............................................................................... 42 5.1 Memristor Fabrication ..................................................................................... 42 5.2 Memristor Modeling ........................................................................................ 43 5.3 Summary .......................................................................................................... 43 APPENDIX A: MATLAB MEMRISTOR MODEL CODE ..................................... 44 A.1 Main Body of Code ......................................................................................... 44 A.2 ODE45 Function Code .................................................................................... 45 APPENDIX B: VERILOGA MEMRISTOR CODE ................................................. 46 BIBLIOGRAPHY ....................................................................................................... 47 iv LIST OF FIGURES Figure 1. Figure showing ideal memristor behavior. OFF and ON states shown by (b) and (c) respectively. The operation between states is illustrated in (a). ................. 5 Figure 2. (a) Unipolar switching and (b) bipolar switching curve examples. Reprinted by permission from Macmillan Publishers Ltd: Nature Materials [4], © 2007. ................................................................................................................... 6 Figure 3. Formation of a filament in the switching medium for (a) vertical and (b) horizontal structures. Reprinted by permission from Macmillan Publishers Ltd: Nature Materials [4], © 2007. ............................................................................... 7 Figure 4. Test vehicle to test TiO 2 memristor switching mechanisms. Reprinted by permission from Macmillan Publishers Ltd: Nature Nanotechnology [6], © 2008............................................................................................................................. 11 Figure 5. Close-up of each junction and a plot of its work function. Reprinted by permission from Macmillan Publishers Ltd: Nature Nanotechnology [6], © 2008............................................................................................................................. 11 Figure 6. SPICE Macro Model of a Memristor. .................................................................... 18 Figure 7. Anodization equipment. ......................................................................................... 23 Figure 8. Example of a finished sample on a titanium film. .................................................. 24 Figure 9. Example of sample made with titanium deposited on a glass slide. ...................... 24 Figure 10. Probe station with sample under test. ................................................................... 25 Figure 11. Keithley 4200 Semiconductor Characterization System. ..................................... 26 Figure 12. Samples that were not annealed. The number above each plot states how many seconds the sample was anodized for. All currents have been normalized and arrows denote the direction of the sweep. ......................................... 30 Figure 13. Annealed samples. The anodization time for each sample is above the respective plot. All currents have been normalized. ................................................... 31 v Figure 14. Three consecutive sweeps on the not-annealed ten second sample. .................... 32 Figure 15. "Soft-Switching" sweeps for the not-annealed samples. ...................................... 33 Figure 16. "Soft-Switching" sweeps for annealed samples. .................................................. 34 Figure 17. AFM images for not-annealed samples. Left to Right: 60s, 10s, 3s, 1s. ............. 34 Figure 18. Plot made with Matlab memristor model. ............................................................ 36 Figure 19. Comparison of Biolek Pspice model to 10 second sample................................... 38 Figure 20. Pspice V vs time memristor model curve. ............................................................ 39 Figure 21. Pspice I vs time memristor model curve. ............................................................. 40 vi ACKNOWLEDGEMENTS I would like to thank Dr. Neihart and Dr. Chaudhary for giving me the opportunity to do research on a very cutting-edge and interesting topic. Memristors did not exist as an area of research at Iowa State, and both of them supported me in the creation of this new research. Without their help and support, this work would not have been possible. I would also like to thank my parents who supported me financially and emotionally through college. They instilled the notion of the importance of higher level education in my life. vii ABSTRACT A new method for the fabrication of memristors is exhibited involving the electrochemical anodization of titanium. This is an inexpensive, room temperature alternative to the current methods of fabrication. Two sets of devices were fabricated with varying anodization times and the devices were characterized. One set of the devices was annealed before characterization to evaluate the importance of annealing as stated in papers. The devices not annealed yielded memristive behavior due to oxygen vacancies created at the titanium-TiO 2 junction buried below the surface of the device. The annealed devices behaved as resistors
Recommended publications
  • Monolithic Integration of a Novel Microfluidic Device with Silicon Light Emitting Diode-Antifuse and Photodetector
    ESSDERC 2002 Monolithic Integration of a Novel Microfluidic Device with Silicon Light Emitting Diode-Antifuse and Photodetector P. LeMinh, J. Holleman, J.W.Berenschot,N.R.Tas,A.vandenBerg MESA+ Research Institute, University of Twente, the Netherlands E-mail [email protected] Abstract developing an CMOS compatible etching recipe using Tetra Methyl Ammonium Hydroxide (TMAH). Light emitting diode antifuse has been integrated into In the next sections of the paper, fabrication process, a microfluidic device that is realized with extended some critical technological design parameters, electrical standard CMOS technological steps. The device and optical properties, few results on first applications comprises of a microchannel sandwiched between a will be described respectively. photodiode detector and a nanometer-scale diode antifuse light emitter. Within this contribution, the 2. Device realization device fabrication process, working principle and properties will be discussed. Change in the interference The realization of the device (figure 1) is a 10-mask fringe of the antifuse spectra has been measured due to process. The starting material is a 3-in silicon n-type the filling of the channel. Preliminary applications are wafer with standard doping. First of all, junction electroosmotic flow speed measurement, detection of photodiode areas were fabricated by implantation of absorptivity of liquids in the channel… boron. So as not to make any step height difference at the junction between n-type and p-type region, thick resist 1. Introduction was used as masking layer for the implantation. This is important to the evenness of the channel. The shape of Silicon is well-known as an electronic and mechanical the channel was then produced by shaping a layer of material but hardly ever used as an active optoelectronic 500nm thick LPCVD polysilicon deposited on top of the element, due to its inefficient radiative recombination first silicon rich nitride (SiRN) layer.
    [Show full text]
  • PPBI for OTP Fpgas Final Report
    ESA UNCLASSIFIED – For Official Use estec European Space Research and Technology Centre Keplerlaan 1 2201 AZ Noordwijk The Netherlands Tel. (31) 71 5656565 Fax (31) 71 5656040 www.esa.int PPBI for OTP FPGAs Final Report Prepared by: Ken Hernan Reference: ESCC WG 01/13 Issue: 1 Revision: 9 Date of Issue: 23rd May 2014 Status: Final Document Type: WG Report ESA UNCLASSIFIED – For Official Use ESA UNCLASSIFIED – For Official Use Table of contents: 1 INTRODUCTION ...................................................................................................................................................... 5 1.1 SCOPE OF THE DOCUMENT ..................................................................................................................................... 5 1.2 APPLICABLE AND REFERENCE DOCUMENTS ........................................................................................................... 5 1.2.1 Reference Documents (RDs) .......................................................................................................................... 5 1.3 ACRONYMS AND ABBREVIATIONS .......................................................................................................................... 6 2 EXECUTIVE SUMMARY ........................................................................................................................................ 9 3 WOKRING GROUP ACTIVITIES ........................................................................................................................ 15 4 BACKGROUND
    [Show full text]
  • Semiconductor Devices
    H01L CPC COOPERATIVE PATENT CLASSIFICATION H ELECTRICITY (NOTE omitted) H01 BASIC ELECTRIC ELEMENTS (NOTES omitted) H01L SEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR (use of semiconductor devices for measuring G01; resistors in general H01C; magnets, inductors, transformers H01F; capacitors in general H01G; electrolytic devices H01G 9/00; batteries, accumulators H01M; waveguides, resonators, or lines of the waveguide type H01P; line connectors, current collectors H01R; stimulated-emission devices H01S; electromechanical resonators H03H; loudspeakers, microphones, gramophone pick-ups or like acoustic electromechanical transducers H04R; electric light sources in general H05B; printed circuits, hybrid circuits, casings or constructional details of electrical apparatus, manufacture of assemblages of electrical components H05K; use of semiconductor devices in circuits having a particular application, see the subclass for the application) NOTES 1. This subclass covers: • electric solid state devices which are not covered by any other subclass and details thereof, and includes: semiconductor devices adapted for rectifying, amplifying, oscillating or switching; semiconductor devices sensitive to radiation; electric solid state devices using thermoelectric, superconductive, piezo-electric, electrostrictive, magnetostrictive, galvano- magnetic or bulk negative resistance effects and integrated circuit devices; • photoresistors, magnetic field dependent resistors, field effect resistors, capacitors with potential-jump
    [Show full text]
  • Recent Advancement in the Memristor Memory Development Ravikumar K
    International Journal of Innovative Technology and Exploring Engineering (IJITEE) ISSN: 2278-3075, Volume-9 Issue-7, May 2020 Recent Advancement in the Memristor Memory Development Ravikumar K. I, Sukumar R voltages as referred to in [19]) and d) manufacturing methods Abstract: Meritor is a newly-created tool and because of its compliant with CMOS relative to other NVM systems. nanometer scale and different electrical properties it has received Relative to other MRM (Resistive random access memory) much interest from advanced electronics designers since it was there are specific advantages. The RRAM is combined with discovered. The memory capacity of a memrist is one of the most significant features. In this paper, about 50 papers on designing the SRAM cell in past works such as [20–23], but each of memristor, optimization rules for reducing power, area for configuration either contributes to substantial deterioration of storing the data into memristor and implemented the full adders the fundamental SRAM reading process or absorbs a huge using memristor using the Pspice simulator. The paper ultimately amount of energy for the storage / restoration of data to / from addresses the complex study lapses and obstacles in constructing RRAM as described further in depth in section 4. In our paper the memorial that will enable scholars and thinkers lead to more analysis. we give a new NV-SRAM 8T1R that is similar to a standard Keywords: memristor, optimization. SRAM 6 T device with reading power, delay and noise tolerance. In turn, since only one RRAM cell is required for I. INTRODUCTION the off-time storage of SRAM data, energy used for processing RRAM data is reduced by more than 60% relative The resistive memory of the Crossbar has recently gained to the lowest energy density of previous RRAM NV-SRAM tremendous publicity owing to its amazing high density and designs.
    [Show full text]
  • Reliability of the Amorphous Silicon Antifuse
    Reliability of the Amorphous Silicon Antifuse • • • • • • QuickLogic® White Paper Abstract Development processes at QuickLogic control the reliability of the QuickLogic ViaLink® antifuse. ViaLink reliability is built into the silicon at every step, beginning with design rules and device characterization. But unlike other fab processes, the reliability work continues with the layout rules, test methodology, place and route software, ViaLink programming sequence, programming algorithm, qualification plans, and quality assurance process. All these factors come together to create the reliable QuickLogic ViaLink. Introduction Semiconductor reliability has been studied and characterized [1]. The initial failure rate, also called infant mortality, is high due to defects. The midterm life of a semiconductor component has a low failure rate. Most of the defects have already failed, and the wear out failure for mechanisms has not started. At the end of the semiconductor component life, many elements of the semiconductor begin to wear out. Physical changes to the metals, semiconductor, and dielectrics cause the component to no longer meet the original specification. These failures are predictable and increase with time. This high-low-high failure rate is known as the bathtub curve and is shown in Figure 1. Figure 1: Bathtub curve for semiconductor failure rate. Semiconductor manufacturers have reduced the infant mortality by decreasing the number of defects and screening for the remaining defects. Defects have been reduced with improved and automated wafer handling, improved equipment and improved processes. Automatic inspections have been added during wafer fabrication for the purpose of detecting wafers with defects. Wafers that cannot be reworked are scrapped. After fabrication, wafers are tested for correct electrical parameters.
    [Show full text]
  • (12) Patent Application Publication (10) Pub. No.: US 2012/0314475A1 L (43) Pub
    US 2012O314475A1 (19) United States (12) Patent Application Publication (10) Pub. No.: US 2012/0314475A1 L (43) Pub. Date: Dec. 13, 2012 (54) LOW VOLTAGE PROGRAMMABLE MOSFET (52) U.S. Cl. ........................................................ 365/104 ANTIFUSE WITH BODY CONTACT FOR DIFFUSION HEATING (57)57 ABSTRACT An antifuse can include an insulated gate field effect transis (75) Inventor: YANZUN LI, Lagrangeville, NY tOr “IGFET) havingaV1ng an active Sem1COnductOrreg1Onicond gion 1ncludinclud (US) ing a body and first regions, i.e., at least one source region and at least one drain region separated from one another by the body. A gate may overlie the body and a body contact is (73) Assignee: INTERNATIONAL BUSINESS electrically connected with the body. The first regions have MACHINES CORPORATION, opposite conductivity (i.e., n-type or p-type) from the body. Armonk, NY (US) The IGFET can be configured such that a programming cur rent through at least one of the first regions and the body (21) Appl. No.: 13/158,510 contact causes heating sufficient to drive dopant diffusion from the at least one first region into the body and cause an (22) Filed: Jun. 13, 2011 edge of the at least one first region to move closer to an adjacent edge of at least one other of the first regions. In Such way, the programming current can permanently reduce elec Publication Classification trical resistance by one or more orders of magnitude between (51) Int. Cl. the at least one first region and the at least one other first GITC 17/08 (2006.01) region. 122 118 118 116 Patent Application Publication Dec.
    [Show full text]
  • One-Time, Voltage-Programmable, Read-Only Memory Array Having Memory Cell Igfets, Each of Which Is Coupled to a Reference Voltage Line Via an Anti-Fuse Element
    Europaisches Patentamt European Patent Office 0 Publication number: 0 528 417 A2 Office europeen des brevets EUROPEAN PATENT APPLICATION 0 Application number: 92114148.7 int.Ci.5:G11C 17/16, H01L27/112 0 Date of filing: 19.08.92 0 Priority: 19.08.91 US 746824 0 Applicant: MICRON TECHNOLOGY, INC. 2805 East Columbia Road © Date of publication of application: Boise, ID 83706(US) 24.02.93 Bulletin 93/08 0 Inventor: Lowrey, Tyler A. 0 Designated Contracting States: 2599 E. Plateau DE Boise, Idaho 8371 2(US) Inventor: Lee, Ruojia 3351 Raindrop Dr. Boise, Idaho 83706(US) 0 Representative: Klunker . Schmitt-Nilson . Hirsch Winzererstrasse 106 W-8000 Munchen 40 (DE) One-time, voltage-programmable, read-only memory array having memory cell igfets, each of which is coupled to a reference voltage line via an anti-fuse element. 0 A one-time, voltage-programmable, read-only when subjected to a programming voltage. A series memory array in which individual memory cells com- of minimum pitch bitlines (48 + 49), which run prise an insulated-gate, field-effect transistor, the parallel to the wordlines (33), completes the memory channel of which provides, through a voltage-prog- array. Each bitline (48 + 49) makes direct contact rammable anti-fuse element, a current path between with each pair of cell junctions along its length. The a reference voltage line (34) and a bitline (48 + 49). array is characterized by a non-folded bitline ar- In a preferred embodiment, the array comprises a chitecture. semiconductor substrate having a series of parallel, alternating,
    [Show full text]
  • International Roadmap for Devices and Systems
    INTERNATIONAL ROADMAP FOR DEVICES AND SYSTEMS 2020 EDITION BEYOND CMOS THE IRDS IS DEVISED AND INTENDED FOR TECHNOLOGY ASSESSMENT ONLY AND IS WITHOUT REGARD TO ANY COMMERCIAL CONSIDERATIONS PERTAINING TO INDIVIDUAL PRODUCTS OR EQUIPMENT. ii © 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works. THE INTERNATIONAL ROADMAP FOR DEVICES AND SYSTEMS: 2020 COPYRIGHT © 2020 IEEE. ALL RIGHTS RESERVED. iii Table of Contents Acknowledgments .............................................................................................................................. vi 1. Introduction .................................................................................................................................. 1 1.1. Scope of Beyond-CMOS Focus Team .............................................................................................. 1 1.2. Difficult Challenges ............................................................................................................................ 2 1.3. Nano-information Processing Taxonomy........................................................................................... 4 2. Emerging Memory Devices ..........................................................................................................
    [Show full text]
  • A Novel, Diode-Based Organic Memory Device
    Technische Universität Dresden pinMOS Memory: A novel, diode-based organic memory device Yichu Zheng, M. E. der Fakultät Elektrotechnik und Informationstechnik der Technischen Universität Dresden zur Erlangung des akademischen Grades Doktoringenieur (Dr.-Ing.) genehmigte Dissertation Vorsitzender: Prof. Dr.-Ing. Prof. Hubert Lakner Tag der Einreichung: 24.10.2019 Gutachter: Prof. Dr. rer. nat. Stefan Mannsfeld Tag der Verteidigung: 07.08.2020 Gutachter: Prof. Dr. Koen Vandewal ii Abstract A novel, non-volatile, organic capacitive memory device called p-i-n-metal-oxide-semiconductor (pinMOS) memory is demonstrated with multiple-bit storage that can be programmed and read out electrically and optically. The diode-based architecture simplifies the fabrication process, and makes further optimizations easy, and might even inspire new derived capacitive memory devices. Furthermore, this innovative pinMOS memory device features local charge up of an integrated capacitance rather than of an extra floating gate. Before the device can perform as desired, the leakage current due to the lateral charge up of the doped layers outside the active area needs to be suppressed. Therefore, in this thesis, lateral charging effects in organic light-emitting diodes (OLEDs) are studied first. By comparing the results from differently structured devices, the presence of centimeter-scale lateral current flows in the n-doped and p-doped layers is shown, which results in undesirable capacitance increases and thus extra leakage currents. Such lateral charging can be controlled via structuring the doped layers, leading to extremely low steady-state leakage currents in the OLED (here 10-7 mA/cm2 at -1 V). It is shown that these lateral currents can be utilized to extract the conductivity as well as the activation energy of each doped layer when modeled with an RC circuit model.
    [Show full text]
  • United States Patent (19) 11 Patent Number: 5,962,815 Lan Et Al
    USOO5962815A United States Patent (19) 11 Patent Number: 5,962,815 Lan et al. (45) Date of Patent: Oct. 5, 1999 54 ANTIFUSE INTERCONNECT BETWEEN FOREIGN PATENT DOCUMENTS TWO CONDUCTING LAYERS OF A PRINTED CIRCUIT BOARD 0336359 10/1989 European Pat. Off.. 59-13368 1/1984 Japan. (75) Inventors: James J. D. Lan, Fremont; Steve S. 2-281685 11/1990 Japan. Chiang, Saratoga, both of Calif.; William H. Shepherd, Placitas, OTHER PUBLICATIONS N.Mex.; Paul Y. F. Wu, San Jose, Calif. Joshua Silver, “High-Performance Scalable Switch Design,” ASIC & EDA, Jun. 1994, pp. 38–48. Assignee: Prolinx Labs Corporation, San Jose, Calif. Kathryn E. Gordon and Richard J. Wong, “Conducting Filament of the Programmed Metal Electrode Amorphous Appl. No.: 08/374,941 Silicon Antifuse," IEEE, 1993, pp. 27–30. Paul C. Yu, Steven J. Decker, Hae-Seung Lee, Charles G. Filed: Jan. 18, 1995 Sodini and John L. Wyatt, “CMOS Resistive Fuses for Int. Cl." ................................................ HO1R 9/09 Image Smoothing and Segmentation,” 1992 IEEE, IEEE U.S. C. ... 174/262; 257/665; 361/779 Journal of Solid-State Circuits, vol. 27, No. 4, Apr. 1992, pp. Field of Search ..................................... 174/262, 250, 545-553. 174/264, 265, 261, 255; 257/.530, 665, 209, 529; 361/779, 777; 29/847 (List continued on next page.) References Cited Primary Examiner Kristine Kincaid U.S. PATENT DOCUMENTS ASSistant Examiner-Kamand Cuneo Attorney, Agent, or Firm-Skjerven, Morrill, MacPherson, 3,335,327 8/1967 Damon et al. .......................... 361/767 Franklin & Friel; Alan H. MacPherson, Omkar K. 3,384.879 5/1968 Stahl et al.
    [Show full text]
  • A 32-KB Standard CMOS Antifuse One-Time Programmable ROM
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 9, SEPTEMBER 2006 2115 A 32-KB Standard CMOS Antifuse One-Time Programmable ROM Embedded in a 16-bit Microcontroller Hyouk-Kyu Cha, Student Member, IEEE, Ilhyun Yun, Jinbong Kim, Byeong-Cheol So, Kanghyup Chun, Ilku Nam, Member, IEEE, and Kwyro Lee, Senior Member, IEEE Abstract—A 32-KB standard CMOS antifuse one-time pro- [10] such as polyfusing or utilization of oxide–nitride–oxide grammable (OTP) ROM embedded in a 16-bit microcontroller (ONO) [11] and metal–oxide–metal [12], [13] as the antifuse as its program memory is designed and implemented in 0.18- m (AF) element which are candidates to be used as the PM of standard CMOS technology. The proposed 32-KB OTP ROM cell array consists of 4.2 mP three-transistor (3T) OTP cells where microcontrollers. However, polyfusing is not reliable enough each cell utilizes a thin gate-oxide antifuse, a high-voltage blocking for manufacturing, while metal–oxide–metal and ONO require transistor, and an access transistor, which are all compatible with additional processes in order to apply it to standard CMOS standard CMOS process. In order for high density implementa- products. On the other hand, continuous advances and scaling tion, the size of the 3T cell has been reduced by 80% in comparison in CMOS technology has enabled the use of the thin gate-oxide to previous work. The fabricated total chip size, including 32-KB OTP ROM, which can be programmed via external IPC master of CMOS as the AF for programming [14], [15].
    [Show full text]
  • Chapter 4: Programmable Logic Devices
    Chapter 4: Programmable Logic Devices 4.1 Chapter Overview This Chapter provides an overview on Programmable Logic Devices (PLDs) form the history of programmable logic devices to the device types. PLDs come in two forms, Complex Programmable Logic Devices (CPLDs) and Field Programmable Gate Arrays (FPGAs) both having their advantages and disadvantages with respect to the specific application or design they are to be used in. The PLD used for our design, which was a CPLD from Lattice Semiconductor is discussed. There is a need for design of smaller more dense electronic designs requiring less board space as well as less power in the space and military industries there are very few PLD vendors that provide Radiation Hardened components. Unfortunately intellectual Property Cores will be discussed which is the latest trend for vendors to provide system-on-a-chip capability for their FPGA’s. 4.2 Introduction 4.2.1 Background of Programmable Logic Devices A programmable Logic device refers to any type of integrated circuit that a logic design can be implemented and reconfigured in the field by the end user. Since these logic devices can be programmed in the field they are also called Field Programmable Logic Devices (FPLDs). The PLD provides flexibility for designers to implement many different designs in varying complexities for many different applications. One of the most common PLDs is the one time Programmable Read-only Memory (PROM). This comes in two different types: (a) mask programmable devices programmed by the vendor using a custom mask and interconnects and (b) field programmable devices that are 16 configured by the user.
    [Show full text]