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Memristor Devices: Fabrication, Characterization, Simulation MEMRISTOR DEVICES: FABRICATION, CHARACTERIZATION, SIMULATION, AND CIRCUIT DESIGN Thesis Submitted to The School of Engineering of the UNIVERSITY OF DAYTON In Partial Fulfillment of the Requirements for The Degree of Master of Science in Electrical Engineering By Chris Yakopcic Dayton, Ohio August, 2011 MEMRISTOR DEVICES: FABRICATION, CHARACTERIZATION, SIMULATION, AND CIRCUIT DESIGN Name: Yakopcic, Chris APPROVED BY: _________________________________ _________________________________ Tarek M. Taha, Ph.D. Guru Subramanyam, Ph.D. Advisory Committee Chairman Committee Member Associate Professor Chair and Professor Electrical and Computer Engineering Electrical and Computer Engineering _________________________________ Andrew Sarangan, Ph.D. Committee Member Associate Professor Electro-Optics _________________________________ _________________________________ John G. Weber, Ph.D. Tony E. Saliba, Ph.D. Associate Dean Dean, School of Engineering School of Engineering & Wilke Distinguished Professor ii ©Copyright by Chris Yakopcic All Rights Reserved 2011 iii ABSTRACT MEMRISTOR DEVICES: FABRICATION, CHARACTERIZATION, SIMULATION, AND CIRCUIT DESIGN Name: Yakopcic, Chris University of Dayton Advisor: Dr. Tarek M. Taha Significant interest has been placed on developing systems based on memristors since the initial fabrication by HP Labs in 2008 [1]. The memristor is a nanoscale device with dynamic resistance that is able to retain the last programmed resistance value after power is removed from the device. This property shows that the memristor can be used as a non-volatile memory component, and has potential to enhance many types of systems, such as high density memory, and neuromorphic computing architectures. This thesis presents the fabrication and characterization results obtained based memristor devices developed at the University of Dayton. In addition, a comparison between the existing memristor device models was completed to show how the memristor can be used in a multistate operation. Lastly, circuit designs were completed that demonstrate the writing and reading of information to and from memristor devices. These represent the initial steps required in developing electronic systems based on memristors. A large portion of the work completed in this thesis has been published in [2-4]. iv ACKNOWLEDGMENTS My special thanks are in order to Dr. Tarek M. Taha, my advisor, for providing the time and equipment necessary for the work contained herein, and for directing this thesis and bringing it to its conclusion with patience and expertise. I would also like to express my appreciation to everyone who has helped me with this work. This includes Dr. Andrew Sarangan and Dr. Eunsung Shin, who were responsible for fabricating the devices characterized in these experiments; Dr. Guru Subramanyam and Dr. Douglas Hansen, who provided the necessary equipment for characterizing the devices; and Mark Patterson, who offered his help and expertise when designing the mask set used for the second device fabrication experiment. v TABLE OF CONTENTS ABSTRACT ....................................................................................................................... iv ACKNOWLEDGMENTS ...................................................................................................v LIST OF FIGURES ........................................................................................................... ix I. INTRODUCTION ............................................................................................................1 II. BACKGROUND .............................................................................................................5 2.1 Memristor Origin ....................................................................................................... 5 2.2 Physical Memristor Discovery .................................................................................. 6 2.2.1 HP Labs Titanium Dioxide Memristor................................................................ 7 2.2.2 Alternative Thin-Film Memristor Designs .......................................................... 9 2.2.3 Spintronic Memristor Devices .......................................................................... 10 2.3 RRAM ..................................................................................................................... 11 2.4 Device Modeling ..................................................................................................... 11 2.5 Circuit Design .......................................................................................................... 12 2.6 Applications ............................................................................................................. 14 III. PHYSICAL DEVICE EXPERIMENT 1 .....................................................................15 3.1 Device Fabrication ................................................................................................... 15 vi 3.2 Experimental Test Setup .......................................................................................... 17 3.3 Experimental Test Results ....................................................................................... 18 3.3.1 Characterization by User Controlled Test Setup ............................................... 18 3.3.2 Characterization by Computer Controlled Test Setup ...................................... 22 3.3.3 Characterization Using Pulse Waveform .......................................................... 25 IV. PHYSICAL DEVICE EXPERIMENT 2 .....................................................................27 4.1 Mask Design for Future Devices ............................................................................. 27 4.1.1 Overall Mask Set ............................................................................................... 28 4.1.2 Device Patterns in Mask Design ....................................................................... 29 4.2 Second Generation Device Fabrication ................................................................... 31 4.3 Second Generation Device Characterization ........................................................... 34 V. COMPARISON OF DEVICE MODELING METHODS ............................................37 5.1 Modeling Equations ................................................................................................. 37 5.2 Equation Based Device Simulation ......................................................................... 40 5.2.1 Device Simulation Based on Linear Model ...................................................... 40 5.2.2 Device Simulation Based on Non-Linear Model 1 ........................................... 42 5.2.3 Device Simulation Based on Non-Linear Model 2 ........................................... 43 5.3 Resistance State Analysis Based on Device Models ............................................... 44 5.3.1 Resistance States in the Linear Device Model .................................................. 44 5.3.2 Resistance States in the Non-Linear Device Models ........................................ 45 vii 5.3.3 Resistance State Comparison ............................................................................ 47 5.4 Device Modeling Based on Fabrication Data .......................................................... 50 VI. CIRCUIT DESIGN BASED ON NON-LINEAR DRIFT MODEL ...........................53 6.1 Circuit for Writing to Memristor ............................................................................. 53 6.1.1 Write Circuit Schematic .................................................................................... 53 6.1.2 Simulation Results for Memristor Write Circuit ............................................... 54 6.2 Circuit for Reading Resistance of a Memristor Device ........................................... 56 6.2.1 Read Circuit Schematic ..................................................................................... 56 6.2.2 Simulation Results for Memristor Read Circuit ................................................ 57 VII. CONCLUSION ..........................................................................................................59 BIBLIOGRAPHY ..............................................................................................................62 viii LIST OF FIGURES 3.1. Device layout for UDMEM1. .................................................................................... 16 3.2. Device layout for UDMEM2. .................................................................................... 16 3.3. Device layout for UDMEM8. .................................................................................... 16 3.4. Memristors on wafer: (a) alignment of multiple memristors on a wafer, and (b) probe applied to test a single device. .......................................................................................... 17 3.5. Test results for UDMEM1 with a voltage loop ranging from -4V to 4V. ................. 19 3.6. Test results for UDMEM2 with a voltage loop ranging from -4V to 4V. ................. 19 3.7. I-V curve results for UDMEM2 with voltage ranging from -8V to 5V.................... 20 3.8. Multiple voltage loop test, first pass. ......................................................................... 21 3.9. Multiple voltage loop test, second pass. .................................................................... 21 3.10. Multiple voltage loop test, third pass. .....................................................................
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