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Carbon Nanotube Based VLSI Interconnects Analysis and Design SPRINGER BRIEFS IN APPLIED SCIENCES AND TECHNOLOGY Brajesh Kumar Kaushik Manoj Kumar Majumder Carbon Nanotube Based VLSI Interconnects Analysis and Design SpringerBriefs in Applied Sciences and Technology More information about this series at http://www.springer.com/series/8884 Brajesh Kumar Kaushik Manoj Kumar Majumder Carbon Nanotube Based VLSI Interconnects Analysis and Design 1 3 Brajesh Kumar Kaushik Manoj Kumar Majumder Department of Electronics and Communication Engineering Indian Institute of Technology Roorkee Roorkee Uttarakhand India ISSN 2191-530X ISSN 2191-5318 (electronic) ISBN 978-81-322-2046-6 ISBN 978-81-322-2047-3 (eBook) DOI 10.1007/978-81-322-2047-3 Library of Congress Control Number: 2014946403 Springer New Delhi Heidelberg New York Dordrecht London © The Author(s) 2015 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. Exempted from this legal reservation are brief excerpts in connection with reviews or scholarly analysis or material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. Duplication of this publication or parts thereof is permitted only under the provisions of the Copyright Law of the Publisher’s location, in its current version, and permission for use must always be obtained from Springer. Permissions for use may be obtained through RightsLink at the Copyright Clearance Center. Violations are liable to prosecution under the respective Copyright Law. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. While the advice and information in this book are believed to be true and accurate at the date of publication, neither the authors nor the editors nor the publisher can accept any legal responsibility for any errors or omissions that may be made. The publisher makes no warranty, express or implied, with respect to the material contained herein. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com) Preface Aggressive scaling of semiconductor process technology over the last several dec- ades has resulted in creation of many new products, such as computers, camera, cell phones, and information appliances. This trend is expected to continue for the coming years and create countless opportunities and challenges. Recent develop- ments in the semiconductor industry shows a rapid increase in interconnect fre- quency and design complexity. Introduction of newer technologies is now moving toward a 2-year cycle as compared to the traditional 3-year cycle. Though tech- nology scaling helps in addressing design complexity and performance trends, it opens up a whole new spectrum of design validation challenges. As technology scaling trend continues, interconnect parasitics play domi- nant role in determining chip performance and functionality. Interconnect delay becomes a significant portion of chip delay and noise/crosstalk caused due to par- asitic coupling poses threat to circuit functionality. With increasing demands for high signal speeds coupled with reduced feature sizes, interconnect effects such as signal delay, distortion, and crosstalk become the dominant factors limiting over- all performance of high-speed systems. If not considered during the design stage, interconnect effects can cause failed designs. Advancement of VLSI technology leads to the development of high-speed com- plex integrated circuits (ICs) in deep submicron and nanoscale regime. Due to shrinking feature size and increasing clock frequency, interconnect plays an impor- tant role in determining the overall chip performance. In current scenario, inter- connect delay dominates over gate delay. Depending on the length, interconnects can be classified to local, semi-global, and global interconnects. With ever-increas- ing lengths, global interconnects are prone to large interconnect delays, signal integrity issues, and higher current densities. The global interconnects are widely employed to distribute data, clock, power supply, and ground throughout the entire chip. At global level of interconnects, most of the conventional materials (such as Al or Cu) are susceptible to electromigration due to high current density. This elec- tromigration problem substantially affects the reliability of high-speed circuits. To avoid such problems, researchers are forced to find an alternative solution. v vi Preface Carbon nanotubes (CNTs) can be considered as an alternative interconnect material for current nanoscale technologies. After discovery in 1991, CNTs have received tremendous research interest for their unique mechanical, electrical, thermal, and chemical properties. The sp2 bonding in graphene is even stronger than the sp3 bonds in diamond that gives CNTs very high mechanical strength. The unique electrical and thermal properties are mainly due to movement of elec- trons in one-dimension (1D). Due to 1D movement, electrons can be scattered only in backward direction. Mean free path (mfp) in high quality nanotubes is in the range of micrometers. This is in contrast to a three-dimensional (3D) metal- lic wire wherein electrons can be backscattered by a series of small angle scatter- ings, and therefore mfps are in the range of a few tens of nanometers. Due to long mfp, the ballistic phenomenon can be observed in CNTs that is responsible for its outstanding electrical and thermal behavior. Moreover, an isolated CNT can carry current density in excess of 109 A/cm2, which can enhance the electrical perfor- mance as well as eliminate electromigration reliability concerns that plagues cur- rent nanoscale Cu interconnects. This book primarily focuses on the performance analysis of CNT based inter- connects in current research scenario. Different CNT structures are modeled on basis of transmission line theory. Performance comparison for different CNT structures illustrates that CNTs are more promising than Cu or other materials used in global VLSI interconnects. The organization of the book chapters is as fol- lows: Chapter 1 provides an overview of current research scenario and basics of interconnects. Unique crystal arrangements and the physical properties of CNTs are described in Chap. 2. Furthermore, this chapter illustrates the production, purification, and applications of CNTs. Chapter 3 provides a brief review of the research work carried out in the area of CNT interconnect modeling. The geometry and equivalent RLC parameters for different single and bundled CNTs are also dis- cussed in this chapter. A comparative analysis of crosstalk and delay for different single and bundled CNT structures is carried out in Chap. 4. Finally, Chap. 5 intro- duces unique mixed CNT bundle structures and their equivalent electrical models. We would like to express our sincere gratitude to Mr. Arsalan Alam, Mr. Madimatla Satyanarayana Murthy and Mr. Nisarg D. Pandya for their unre- strained help in successful completion of this book. We also acknowledge for the help rendered by all the research scholars and faculty members of Microelectronics and VLSI group, Indian Institute of Technology Roorkee for con- structive technical discussions at various stages of preparation of this book. Brajesh Kumar Kaushik Manoj Kumar Majumder Contents 1 Interconnects ............................................... 1 1.1 Introduction ............................................ 1 1.2 Types of Interconnects .................................... 3 1.3 Evolution of Interconnects ................................. 4 1.3.1 Aluminum Interconnects ........................... 4 1.3.2 Reason Behind the Replacement of Al by Cu ........... 5 1.3.3 Demerits of Cu Interconnects ........................ 6 1.3.4 Demands in Future Interconnects ..................... 6 1.4 Carbon Nanotubes: The Ultimate Choice ..................... 14 2 Carbon Nanotube: Properties and Applications .................. 17 2.1 Introduction ............................................ 17 2.2 Structure and Types of Carbon Nanotubes ..................... 18 2.3 Electronic Band Structure of CNTs .......................... 20 2.3.1 Band Structure of CNTs from Graphene ............... 22 2.3.2 Metallicity and Semiconducting Properties of Zigzag CNTs .................................. 25 2.4 Properties of CNTs ....................................... 26 2.4.1 Electrical Conductivity ............................. 26 2.4.2 Strength and Elasticity ............................. 26 2.4.3 Thermal Conductivity and Expansion ................. 27 2.4.4 Field Emission ................................... 27 2.4.5 Aspect Ratio ..................................... 27 2.4.6 Absorbent ....................................... 28 2.5 Production of CNTs ...................................... 28 2.5.1 Arc Discharge Method ............................. 28 2.5.2 Laser Method .................................... 29 2.5.3 Chemical Vapor Deposition ......................... 29 2.5.4
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