Analysis of Local Interconnect Resistance at Scaled Process Nodes R

Analysis of Local Interconnect Resistance at Scaled Process Nodes R. Pandey1, N. Agrawal1, R. Arghavani2 and S. Datta1 1The Pennsylvania State University, University Park PA 16802, USA; 2Lam Research, CA, USA. Email: [email protected] Introduction: M0/M1 local interconnects exhibit steadily increasing resistance with Line-width (LW) and Critical Dimension (CD) scaling. Enhanced electron scattering from metal surface and grain boundaries as well as increased volume of highly resistive liners/diffusion barriers in the interconnect bulk are key contributors for this trend [1]. Via0 resistance was identified as dominant component of local interconnect resistance at 22 nm process node [1]. Consequently at 14 nm process node back end of line (BEOL) process relaxes Via0 CD [2]. We show that with the latest trend of M0/M1 LW scaling along with Via0 and Contact CD scaling, M0 and Contact emerge as prominent contributors to local interconnect resistance at 5 nm process node. We present comprehensive analysis of local interconnect resistance for interconnects fabricated from both dual damascene and single damascene processes. Additionally, we investigate impact of replacing Tungsten in Contact and M0 line by a lower resistivity Tungsten, at 5 nm process, and quantify subsequent improvement in transistor on-state performance. Local Interconnect Simulation: Numerical simulator Sentaurus TCAD [3] is used to model transport in 3- Dimensional (3D) M0/M1 local interconnect structure (Fig.1 (a)), with technology scaling from 22 nm to 5 nm node. In dual damascene (DD) interconnect (Fig. 1(b)), both metal line and via are fabricated simultaneously. On the contrary, in single damascene (SD) process metal line and via are formed in separate steps which results in an additional Metal-Nitride liner in between metal line and via (Fig. 1(c)). While DD process is preferable due to fewer number of steps, still it has challenges of lining and filling high aspect ratio metal line and via features which become significant with process scaling. We assume three fins contacted per Via0 at every process node. Fins make electrical connection with Tungsten (W) based local interconnect M0 through W Contact with Ti/TiN serving as liner/diffusion barrier. Copper via (Cu Via0) connects M0 to the first metal layer Cu M1 where TaN/Ta acts as barrier/liner layer. Contact and Via0 geometries as well as M0/M1 local interconnect (both bulk metal and liner) dimensions are adopted from published data for 22 nm and 14 nm processes [2,4]. Dimensions at 10 nm, 7 nm and 5 nm processes are estimated from ITRS 2013 projections (Fig. 1(d), [1]). Impact of increasing interconnect resistivity with LW and CD scaling is accounted in simulation by employing size-dependent resistivity for local interconnects from [5]. Resistance of each region is extracted from the solution of Fermi potential across each metal layer and corresponding current magnitude. Local Interconnect Resistance Analysis: Figure 2 shows the current density plot of 3D M0/M1 interconnect stack simulated at 22 nm and 5 nm process nodes. High current density is observed in Cu Via0 whereas the current density falls by nearly 2 orders of magnitudes in significantly resistive liners. Potential distribution and resistance breakdown for DD and SD interconnects is depicted in Fig. 3. In DD interconnect, at 22 nm process, major potential drop occurs Cu Via0 TaN/Ta layers as a result of narrow Via0 CD and high TaN/Ta resistivity (Fig. 3(a)). At 14 nm process, Via0 CD is relaxed to alleviate this bottleneck [2]. However with further interconnect scaling, W M0 and Contact become significant contributors to total M0/M1 resistance as shown in Fig 3(b). At 5 nm process W M0 and Contact comprise 65% of total M0/M1 stack resistance due to narrow CD as well as higher bulk metal resistivity. For SD interconnect the total resistance is even further degraded due to additional contribution from high resistivity liner layer interposing metal and via, which results in 12% higher total resistance compared to DD interconnect at 5 nm process (Fig. 3(c- d)). We further explore replacing W in both M0 and Contact by a lower resistivity W metal Wlo (in this case we assumed hypothetical resistivity equal to Cu). We assume a single diffusion barrier (TiN) for Wlo process. Figure 4(a) shows that replacement of bulk metal by Wlo reduces M0/M1 interconnect resistance by 43%. Benefits of introducing a lower resistivity W in M0 local interconnect are more pronounced for M0 lines (Figs. 4(b-c) show 75% improvement with low resistivity W) which connect devices over distances so that the current flows horizontally and effectively occupies entire volume of low resistivity fill metal. A 3D-FinFET set-up (Fig. 5(a-b)) initially calibrated to 22 nm process [6] and scaled to dimensions of 5 nm process with on-current (ION=1.5mA/μm) adjusted corresponding to ~15% rise with every process generation change at a constant off-current IOFF=10nA/μm, is employed to evaluate impact of parasitic M0/M1 interconnect resistance on FinFET performance. As observed from Fig. 5(c), ION improves by 5% on replacing W in M0 and Contact by lower resistivity W, providing significant saving at 5 nm process. Conclusion:!A detailed analysis of local interconnect resistance with process scaling to 5 nm technology node is presented for both SD and DD interconnects. W M0 and Contact are identified as key resistance contributors at 5 nm process. Introducing a lower resistivity W for metal fill in M0 and Contact shows 43% reduction in M0/M1 resistance along with 5% gain in ION which are significant for ultra-low Vcc based 5 nm process. [1] S. Datta et al., VLSI 2014 [2] S. Natarajan et al., IEDM 2014 [3] TCAD Sentaurus Device Manual, Synopsys Inc., 2010 [4] C.-H. Jan et al., IEDM 2012 [5] C. Adelmann et al., IEEE IITC 2014 [6] N. Agrawal et al., IEEE TED, Oct. 2013

978-1-4673-8135-2/15/$31.00 ©2015 IEEE A Current Dual-Damascene (DD) Single-Damascene (SD) Flow AA’A A’ (d) Process Dimensions CuC AA’ (a) (b) Cu (c) Cu M1 M1 M1 Cu Cu TaN/Ta Cu TaN/Ta Ti/TiN Via0 Via0 Liner Via0 Liner Liner Ti/TiN W W Liner M0 WContact M0 WContact B Gate Gate Gate Gate + n+ n Fin Fin B’ B B’ B B’ Fig. 1. (a) 3D schematic of simulated M0/M1 local interconnect structure. Three contacted fins are also shown for reference. 2D cross-section of the interconnect stack fabricated by (b) Dual-Damascene, and (c) Single-Damascene processes. (d) Process dimensions used in simulation. A 100 A’ ] Ti Contact Liner A V A’ 1.0 DD (a) VDD DD TiN Contact Liner Current Process Cu M1 3 fins contacted Cu TaN/Ta Cu Flow 0.8 Cu 75 W Contact M1 Liner M1 TaN/Taa Node Via0 W M0 Liner Cu 22 nm 0.6 TaN Via0 Liner (b) Ti/TiN Via0 Cu Ta Via0 Liner 5nm 50 Via0 7nm TaN/Ta DD Liner 0.4 Cu Via0 10nm Via0 Liner CurrentCuC rrent 14nm Cu M1 Flow W Ti/TiN 22nm M0 Liner 0.2 25 Normalized Potential (a) VSS WContact W M0 W 0.0 Y B Contact Ti/TiN Contact Liner 0 B’ Current Y 0 100 200 300 22nm 14nm 10nm 7nm 5nm Z X Density B X VSS B’ Height, M0/M1 Stack [nm] Interconnect Resistance [ Process Node

100 Ti Contact Liner ] TaN M1 Liner A VDD 1.0 TiN Contact Liner Ta M1 Liner (b) Cu M1 SD A’ W Contact Cu M1 TaN/Ta V Process TaN/Ta Ti M0 Liner Cu Liner A DD A’ 0.8 75 Cu Current Node M1M Liner TiN M0 Liner 3 fins contacted M1 M1 Flow Cu W M0 Cu TaN/Ta 0.6 Via0 TaN Via0 Liner (d) Via0 5 nm Cu Liner 50 Ta Via0 Liner 5nm TaN/Ta Ti/TiN Via0 0.4 7nm SD Cu Via0 Liner 10nm Via0 Liner CurrentCuC rrent 14nm Ti/TiN 22nm Flow W Liner 0.2 25 M0 Normalized Potential W M0 (c) WContact V 0.0 SS W Ti/TiN Contact Liner Ti/TiNTi//TiN M0 Liner L 0 Y B Current Contact 0 100 200 300 22nm 14nm 10nm 7nm 5nm B’ Y Height, M0/M1 Stack [nm] Density V Interconnect Resistance [ Process Node Z B X SS B’ X Fig. 3. Normalized potential distribution and resistance breakdown in (a), (b) Dual-Damascene, and Fig. 2. Simulated 3D structure with 2D cross- (c), (d) Single-Damascene M0/M1 interconnect structure, respectively as function of process section for DD interconnect at (a) 22nm and technology scaling. W M0 and W Contact emerge as prominent contributors to local interconnect (b) 5 nm process. High magnitude of current resistance at 5 nm process. FinFET, 5 nm process density through Cu Via0 (along with W M0 120 (a) Ideal [No M0/M1 Resistance] and W Contact in 5nm process) in contrastt Reference with low current density through liners is (b) Source Gate M0/M1 Resistance, observed. W M0 and Contact Drain (a) M0/M1 Resistance, 75 5nm process 90 W M0 and Contact ] 3 fins contacted DD lo A] V = 0.55 V Fin DS DD 43% Reduction 120 Current

50 0 Density 60 Ti Contact , per Fin [ Wlo Liner DS 1.0 3 110 m] 10 5 nm process 5% TiN Contact A] V = 0.55 V

A/ W Liner 0.8 2 DS [ 75% 10 [ DS Contact Reduction I 25 0.6 DS 1 100 M0 10 (b) 30 TaN Via0 Liner FinFET (c) 0 Lg 11 nm Ta Via0 Liner 0.4 10 Drain Current I 0.50 0.52 0.54 Cu Via0 EOT 0.65 nm V [V] -1 GS Cu M1 0.2 10 Fin Width 4 nm Interconnect Resistance [ 0 Fin Height 38 nm (c) WCoWlo 10-2 Spacer 5 nm 0.0 Drain Current, I 0 M0 and Contact Fill Metal W Wlo 0.0 0.1 0.2 0.3 0.4 0.5 0.0 0.1 0.2 0.3 0.4 0.5

Normalized Line Resistance, M0 M0 Fill Metal Gate Voltage, VGS [V] Gate Voltage, VGS [V] Fig. 4. (a) M0 and contact resistance is reduced significantly at 5 nm Fig. 5. (a) FinFET at 5 nm process node with IDS-VGS shown in (b). process node by replacing in M0 and Contact fill by low resistivity Wlo. (c) Impact of M0/M1 (DD) interconnect resistance on on-current

(b) 3D simulation of M0 local interconnect at 5 nm process, showing ION. Wlo based M0 and Contact process improve ION by 5% 75% line resistance reduction in Wlo M0 process compared to W M0 compared to W based process, providing significant saving at ultra- process (c). low Vcc based 5 nm process technology.