Risk Factors

•Today’s presentations contain forward-looking statements. All statements made that are not historical facts are subject to a number of risks and uncertainties, and actual results may differ materially. Please refer to our most recent Earnings Release and our most recent Form 10-Q or 10-K filing for more information on the risk factors that could cause actual results to differ.

•If we use any non-GAAP financial measures during the presentations, you will find on our website, intc.com, the required reconciliation to the most directly comparable GAAP financial measure.

Rev. 4/19/11

Today’s News

The world’s first 3-D Tri-Gate on a production technology

New 22nm transistors have an unprecedented combination of power savings and performance gains.

These benefits will enable new innovations across a broad range of devices from the smallest handheld devices to powerful cloud-based servers.

The transition to 3-D transistors continues the pace of technology advancement, fueling Moore’s Law for years to come.

The world’s first demonstration of a 22nm -- code-named Ivy Bridge -- that will be the first high-volume chip to use 3-D Tri-Gate transistors.

Energy-Efficient Performance Built on Moore’s Law

1 65nm 45nm 32nm 22nm

1x

0.1x

> 50%

0.01x reduction

Lower Active Power Active Lower

Lower Leakage Transistor Lower Active Power per Transistor (normalized) Transistor per Power Active 0.001x Constant Performance 0.1 65nm 45nm 32nm 22nm Higher Transistor Performance (Switching Speed) Planar Planar Planar Tri-Gate

Source: 22 nm Tri-Gate transistors increase the benefit from a new technology generation

Source: Intel Transistor Innovations Enable Technology Cadence

2003 2005 2007 2009 2011

90 nm 65 nm 45 nm 32 nm 22 nm

Invented 2nd Gen. Invented 2nd Gen. First to SiGe SiGe Gate-Last Gate-Last Implement Strained Strained Silicon High-k Metal Gate High-k Metal Gate Tri-Gate

Strained Silicon High k Metal gate Tri-Gate Transistor Innovations Enable Cost Benefits of Moore’s Law to Continue 1

200mm

0.1

$ / Transistor 300mm (relative to 0.35um)

0.01

0.001

.35um .25um .18um .13um 90nm 65nm 45nm 32nm 22nm 14nm 10nm

Source: Intel 22 nm Manufacturing Fabs

D1D -- Oregon D1C -- Oregon

Fab 32 -- Arizona Fab 28 -- Israel Fab 12 -- Arizona 22nm upgrades to be completed 2011-12 Tri-Gate Achievement Results from Long Term Commitment to Research Pathfinding Internal Research CE! transfer Development

Manufacturing Tri-Gate Tri-Gate Invented Selected for 22nm node

Tri-Gate Mfg

Single-fin Multi-fin Tri-gate Tri-gate RMG Tri-gate optimized transistor transistor SRAM cells process flow for HVM demonstrated demonstrated demonstrated developed Bringing innovative technologies to HVM is the result of a highly coordinated internal research-development-manufacturing pipeline “For years we have seen limits to how small transistors can get,” said Gordon E. Moore. “This change in the basic structure is a truly revolutionary approach, and one that should allow Moore’s Law, and the historic pace of innovation, to continue.” 22 nm 3-D Tri-Gate Transistor

3-D Tri-Gate transistors form conducting channels on three sides of a vertical fin structure, providing “fully depleted” operation Transistors have now entered the third dimension!

Source: Intel 22 nm 3-D Tri-Gate Transistor

Gates Fins Source: Intel 32 nm Planar Transistors 22 nm Tri-Gate Transistors

Source: Intel Std vs. Fully Depleted Transistors Bulk Transistor

Gate Inversion Gate Layer Oxide

Source Drain

Depletion Region

Silicon Substrate

Substrate voltage exerts some electrical influence on the inversion layer (where source-drain current flows) The influence of substrate voltage degrades electrical sub-threshold slope (transistor turn-off characteristics) NOT fully depleted

Source: Intel Std vs. Fully Depleted Transistors Partially Depleted SOI (PDSOI)

Gate Floating Body

Source Drain

Oxide

Silicon Substrate

Floating body exerts some electrical influence on inversion layer, degrading sub-threshold slope NOT fully depleted Not used by Intel

Source: Intel Std vs. Fully Depleted Transistors Fully Depleted SOI (FDSOI)

Gate

Extremely Source Drain Thin Silicon Layer

Oxide

Silicon Substrate

Floating body eliminated and sub-threshold slope improved Requires expensive extremely thin SOI , which adds ~10% to total process cost Not used by Intel

Source: Intel Std vs. Fully Depleted Transistors Fully Depleted Tri-Gate Transistor

Gate electrode controls silicon fin from three sides providing improved sub-threshold slope Inversion layer area increased for higher drive current Process cost adder is only 2-3%

Source: Intel Transistor Operation

“On” Current

Planar Channel Current (normalized) Threshold Voltage

“Off” Current

Operating Gate Voltage (V) Voltage

Maximize current in “on” state (for improved performance) Minimize current in “off” state (for lower power) Switch very quickly between the two states (for performance)

Source: Intel Transistor Operation

Planar Channel Current (normalized) Tri-Gate

Reduced Leakage

Gate Voltage (V)

The “fully depleted” characteristics of Tri-Gate transistors provide a steeper sub-threshold slope that reduces leakage current

Source: Intel Transistor Operation

Tri-Gate Reduced Threshold Voltage Channel Current (normalized) Tri-Gate

Reduced Gate Voltage (V) Operating Voltage

The steeper sub-threshold slope can also be used to target a lower threshold voltage, allowing transistors to operate at lower voltage to reduce power and/or improve switching speed

Source: Intel Transistor Gate Delay

32 nm Planar Transistor Slower Gate Delay (normalized)

Lower Voltage

Operating Voltage (V)

Transistor gate delay (switching speed) slows down as operating voltage is reduced

Source: Intel Transistor Gate Delay

32 nm Planar Transistor Gate Delay (normalized) 22 nm Planar

Operating Voltage (V)

22 nm planar transistors could provide some performance improvement, but would still have poor gate delay at low voltage

Source: Intel Transistor Gate Delay

37% 32 nm Faster Planar Transistor Gate Delay (normalized)

22 nm 18% Tri-Gate Faster

Operating Voltage (V)

22 nm 3-D Tri-Gate transistors provide improved performance at high voltage and an unprecedented performance gain at low voltage

Source: Intel Transistor Gate Delay

32 nm Planar Transistor Gate Delay (normalized) -0.2 V 22 nm Tri-Gate

Operating Voltage (V)

22 nm 3-D Tri-Gate transistors can operate at lower voltage with good performance, reducing active power by >50%

Source: Intel 3-D Tri-Gate Transistor Benefits

• Dramatic performance gain at low operating

voltage, better than Bulk, PDSOI or FDSOI 37% performance increase at low voltage >50% power reduction at constant performance

• Improved switching characteristics (On current vs. Off current)

• Higher drive current for a given transistor

footprint • Only 2-3% cost adder (vs. ~10% for FDSOI)

3-D Tri-Gate transistors are an important innovation needed to continue Moore’s Law

Source: Intel 22nm Product Update

Dadi Perlmutter Executive Vice President General Manager, Intel Architecture Group 22nm Silicon Technology Breakthrough Benefits Broad Range of Intel Architecture Devices

New 22nm 3-D transistors deliver unprecedented performance improvement and power reduction for Intel’s product portfolio • This benefits smallest handhelds to powerful cloud-based servers • 37% performance increase at low voltage vs. 32nm planar transistors* • Consumes only half the power at the same performance level as 2-D transistors on 32nm planar chips*

* Based on Intel Internal Data Intel Architecture Spans The Compute Continuum

Servers / Cloud

Desktops Laptops Netbooks Tablets Smartphones Smart TVs Embedded IA Processor Cores Built on a Common Architecture with Optimized Micro-Architectures

Intel Architecture 45nm 32nm 22nm

Optimized Power Nehalem Westmere Sandy Ivy Future Performance Bridge Bridge Microarchitecture Nehalem Microarchitecture Microarchitecture

Low Power Microarchitecture

Bonnell Saltwell Future Microarchitecture Microarchitecture Microarchitecture

Source: Intel Newest Manufacturing Technology Delivers Ivy Bridge

45 nm 32 nm 22 nm Process Technology Process Technology Process Technology

Penryn Nehalem Westmere Sandy Bridge Ivy Bridge Intel® Core™ NEW Intel® Intel® NEW Intel® Intel® Microarchitecture Microarchitecture Microarchitecture Microarchitecture Microarchitecture (Nehalem) (Sandy Bridge) TICK TOCK TICK TOCK TICK Intel’s First 22 nm Processor Cadence of Innovation Delivers New Microprocessor Efficiency on the 22 nm Process Ivy Bridge Sandy Bridge Migrated to 22nm Process Technology

Client: Efficient performance for thin and light form factors • Increased performance vs. today’s 2nd generation Intel® Core™ product family • Enhanced media and graphics performance with processor graphics • Enhanced security features

Server: Increased performance and improved efficiency • Integrated Storage Features

Further Demonstrating Intel Product and Process Leadership Ivy Bridge Client Roadmap 22nm Delivers Balance of Performance and Power Efficiency!

2011 2012

Desktop Waimea Bay Platform Extreme / Sandy Bridge-E (32nm) High-End Desktop Patsburg–X (LGA 2011)

Desktop Maho Bay Platform Performance / Mainstream Ivy Bridge (22nm) Processor Panther Point (LGA 1155) Future Intel® Mobile Chipset Extreme / Chief River Platform Microarchitecture Performance / Ivy Bridge (22nm) Mainstream / Panther Point (LGA 1155) Ultra Low Voltage

All products, dates, and figures specified are preliminary based on current expectations, and are subject to change without notice. Data Center Roadmap Transitioning to 22nm Across the Data Center Portfolio

2011

Boxboro-MC Platform

Itanium Platforms Intel® ® 9300 Processor Poulson Processor 22nm Kittson Processor

Boxboro-EX Platform Future Platform

E7 Platforms Intel® ® Processor E7-8800/4800/2800 Product Family 22 nm Ivy Bridge Based Processor

Tylersburg-EP Platform Romley - EP Platform Sandy Bridge-EP Efficient Performance Intel® Xeon® Processor 5600/5500 Series 22 nm Ivy Bridge Based Processor Platforms Processor Bromolow Platform Intel® Xeon® Processor E3-1200 Product Family 22 nm Ivy Bridge Based Processor E3 Platforms

Knights Ferry SDV 22nm Knights Corner Co-Processor MIC co-processor

All products, dates, and figures specified are preliminary based on current expectations, and are subject to change without notice. INTEL ARCHITECTURE FOR LOW POWER COMPUTING IA Platforms for Low Power Segments Optimized Performance for Phones, Tablets, and Consumer Electronics

1st Gen 45 nm 2nd Gen 45 nm 3rd Gen 32 nm 4th Gen 22 nm

Consumer Electronics Diamondville Groveland Cedar Trail Future Pine Trail Future Sodaville

Oak Trail Menlow Tunnel Creek Clover Trail Future Tablets / Embedded

Moorestown

Medfield Future Smart Phones

All products, dates, and figures specified are preliminary based on current expectations, and are subject to change without notice. Intel® ™ Processor Evolution Higher Performance with Faster Media and Graphics in the same power envelope 1st and 2nd Gen 3rd Gen 4th Gen 45 nm 32 nm 22 nm

Architectural 10X 50X Improvements CPU Thermal Platform Idle Power Reduction* Power Reduction* 1.5X CPU Performance per watt* Process 10X Technology Lower Leakage ~2X Improvements Transistors* Lower Active Power Transistors* ~2X Density Improvements*

* Compared to previous generation of Atom processors

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Risk Factors

The above statements and any others in this document that refer to plans and expectations for the second quarter, the year and the future are forward-looking statements that involve a number of risks and uncertainties. Words such as “anticipates,” “expects,” “intends,” “plans,” “believes,” “seeks,” “estimates,” “may,” “will,” “should,” and their variations identify forward-looking statements. Statements that refer to or are based on projections, uncertain events or assumptions also identify forward- looking statements. Many factors could affect Intel’s actual results, and variances from Intel’s current expectations regarding such factors could cause actual results to differ materially from those expressed in these forward-looking statements. Intel presently considers the following to be the important factors that could cause actual results to differ materially from the company’s expectations. Demand could be different from Intel's expectations due to factors including changes in business and economic conditions, including supply constraints and other disruptions affecting customers; customer acceptance of Intel’s and competitors’ products; changes in customer order patterns including order cancellations; and changes in the level of inventory at customers. Potential disruptions in the high technology supply chain resulting from the recent disaster in Japan could cause customer demand to be different from Intel’s expectations. Intel operates in intensely competitive industries that are characterized by a high percentage of costs that are fixed or difficult to reduce in the short term and product demand that is highly variable and difficult to forecast. Revenue and the gross margin percentage are affected by the timing of Intel product introductions and the demand for and market acceptance of Intel's products; actions taken by Intel's competitors, including product offerings and introductions, marketing programs and pricing pressures and Intel’s response to such actions; and Intel’s ability to respond quickly to technological developments and to incorporate new features into its products. The gross margin percentage could vary significantly from expectations based on capacity utilization; variations in inventory valuation, including variations related to the timing of qualifying products for sale; changes in revenue levels; product mix and pricing; the timing and execution of the manufacturing ramp and associated costs; start-up costs; excess or obsolete inventory; changes in unit costs; defects or disruptions in the supply of materials or resources; product manufacturing quality/yields; and impairments of long-lived assets, including manufacturing, assembly/test and intangible assets. Expenses, particularly certain marketing and compensation expenses, as well as restructuring and asset impairment charges, vary depending on the level of demand for Intel's products and the level of revenue and profits. The majority of Intel’s non-marketable equity investment portfolio balance is concentrated in companies in the market segment, and declines in this market segment or changes in management’s plans with respect to Intel’s investments in this market segment could result in significant impairment charges, impacting restructuring charges as well as gains/losses on equity investments and interest and other. Intel's results could be affected by adverse economic, social, political and physical/infrastructure conditions in countries where Intel, its customers or its suppliers operate, including military conflict and other security risks, natural disasters, infrastructure disruptions, health concerns and fluctuations in currency exchange rates. Intel’s results could be affected by the timing of closing of acquisitions and divestitures. Intel's results could be affected by adverse effects associated with product defects and errata (deviations from published specifications), and by litigation or regulatory matters involving intellectual property, stockholder, consumer, antitrust and other issues, such as the litigation and regulatory matters described in Intel's SEC reports. An unfavorable ruling could include monetary damages or an injunction prohibiting us from manufacturing or selling one or more products, precluding particular business practices, impacting Intel’s ability to design its products, or requiring other remedies such as compulsory licensing of intellectual property. A detailed discussion of these and other factors that could affect Intel’s results is included in Intel’s SEC filings, including the report on Form 10-K for the fiscal year ended Dec. 25, 2010.