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VAX 6000 Model 600 System Technical User’s Guide Order Number: EK–660EA–TM.001 This manual serves as a reference on how to write software to this machine and covers the information needed to do field-level repair or programming customized to the CPU. It includes information on interrupts, error handling, and detailed theory of operation. Digital Equipment Corporation First Printing, January 1992 The information in this document is subject to change without notice and should not be construed as a commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for any errors that may appear in this document. The software, if any, described in this document is furnished under a license and may be used or copied only in accordance with the terms of such license. No responsibility is assumed for the use or reliability of software or equipment that is not supplied by Digital Equipment Corporation or its affiliated companies. Copyright ©1992 by Digital Equipment Corporation All Rights Reserved. Printed in U.S.A. The postpaid READER’S COMMENTS form on the last page of this document requests the user’s critical evaluation to assist in preparing future documentation. The following are trademarks of Digital Equipment Corporation: DEC PDP VAXcluster DEC LANcontroller ULTRIX VAXELN DECnet UNIBUS VMS DECUS VAX XMI DWMVA VAXBI This document was prepared using VAX DOCUMENT, Version 1.2 Contents PREFACE xv CHAPTER 1 THE VAX 6000 MODEL 600 SYSTEM 1–1 1.1 SYSTEM ARCHITECTURE 1–2 1.2 SAMPLE SYSTEM 1–4 1.3 SYSTEM FRONT VIEW 1–6 1.4 SYSTEM REAR VIEW 1–8 1.5 SUPPORTED ADAPTERS 1–10 CHAPTER 2 KA66A CPU MODULE 2–1 2.1 OVERVIEW AND BLOCK DIAGRAM 2–2 2.1.1 NVAX CPU Chip 2–3 2.1.1.1 Ibox • 2–4 2.1.1.2 Ebox and Microsequencer • 2–5 2.1.1.3 Fbox • 2–5 2.1.1.4 Mbox • 2–5 2.1.1.5 Cbox • 2–6 2.1.2 Backup Cache 2–6 2.1.3 NEXMI Chip, System Support, and XMI Interface 2–7 2.2 CPU SECTION 2–8 2.2.1 Data Types 2–8 2.2.2 Instruction Set 2–9 2.2.3 Physical Address Space 2–10 2.2.4 Memory Management 2–11 2.2.4.1 Translation Buffer • 2–12 2.2.4.2 Memory Management Control Registers • 2–13 iii Contents 2.2.5 Exceptions and Interrupts 2–14 2.2.5.1 Interrupts • 2–15 2.2.5.2 Exceptions • 2–17 2.2.5.3 Unique Exceptions • 2–18 2.2.5.4 Console Halt • 2–23 2.2.6 System Control Block 2–25 2.2.7 Process Structure 2–28 2.3 CACHE OVERVIEW 2–30 2.3.1 Writeback Cache and Ownership Concepts 2–30 2.3.2 Virtual Instruction Cache 2–31 2.3.3 Primary Cache 2–32 2.3.4 Backup Cache 2–32 2.3.4.1 Backup Cache Operating Modes • 2–33 2.3.4.2 Cbox Internal Processor Registers • 2–33 2.3.4.3 Tag Store and Data RAM Control • 2–36 2.3.4.4 Backup Cache Is OFF • 2–36 2.3.4.5 Backup Cache Is in Force Hit Mode • 2–37 2.3.4.6 Backup Cache Is in Error Transition Mode • 2–37 2.3.4.7 How to Turn the B-Cache Off • 2–38 2.3.4.8 How to Turn the B-Cache On • 2–39 2.3.5 Cache Initialization 2–40 2.4 NVAX BOX DESCRIPTIONS 2–42 2.4.1 Ibox 2–42 2.4.1.1 Effects of Ibox Pipelining • 2–42 2.4.1.2 Branch Prediction Unit • 2–43 2.4.2 Ebox 2–43 2.4.3 Fbox 2–44 2.4.4 Mbox 2–44 2.4.4.1 Translation Buffer Tag Fills • 2–45 2.4.4.2 Translation Buffer PTE Fills • 2–45 2.4.4.3 Recording Mbox Errors • 2–47 2.4.5 Cbox 2–47 2.5 KA66A TOY CLOCK AND INTERVAL TIMER 2–49 2.5.1 Time-of-Day Register (TODR) 2–49 2.5.2 Programmable Interval Clock 2–49 2.5.3 Time-of-Year Clock 2–50 2.6 XMI INTERFACE 2–54 2.6.1 XMI Address Space 2–54 2.6.1.1 XMI Memory Space • 2–54 2.6.1.2 XMI I/O Space • 2–54 iv Contents 2.6.2 XMI Transaction Generation/Response Tables 2–56 2.6.3 Invalidates 2–57 2.6.4 Writeback Queues 2–58 2.6.5 Lockout Avoidance 2–58 2.6.6 Interrupts and IDENTs 2–59 2.6.6.1 Responding to XMI Interrupts • 2–59 2.6.6.2 Generating the IDENT • 2–59 2.6.6.3 XMI Device Interrupt Priority • 2–60 2.6.6.4 Implied Vector Interrupts (IVINTR) • 2–60 2.6.6.4.1 IVINTR Mask Generation • 2–60 2.6.6.4.2 Interprocessor IVINTR (IP IVINTR) Response • 2–60 2.6.6.4.3 Write Error IVINTR (WE IVINTR) Response • 2–61 2.6.7 XMI Registers 2–61 2.7 KA66A CPU MODULE REGISTERS 2–63 2.7.1 IPR and Cache Addressing 2–63 2.7.2 Internal Processor Registers 2–67 CPU IDENTIFICATION REGISTER (CPUID) 2–71 INTERVAL CLOCK CONTROL AND STATUS REGISTER (ICCS) 2–72 NEXT INTERVAL COUNT REGISTER (NICR) 2–74 INTERVAL COUNT REGISTER (ICR) 2–75 CONSOLE RECEIVER CONTROL AND STATUS REGISTER (RXCS) 2–76 CONSOLE RECEIVER DATA BUFFER REGISTER (RXDB) 2–78 CONSOLE TRANSMITTER CONTROL AND STATUS REGISTER (TXCS) 2–80 CONSOLE TRANSMITTER DATA BUFFER REGISTER (TXDB) 2–82 MACHINE CHECK ERROR SUMMARY REGISTER (MCESR) 2–83 CONSOLE SAVED PROGRAM COUNTER REGISTER (SAVPC) 2–84 CONSOLE SAVED PROCESSOR STATUS LONGWORD (SAVPSL) 2–85 I/O RESET REGISTER (IORESET) 2–90 SYSTEM IDENTIFICATION REGISTER (SID) 2–91 PATCHABLE CONTROL STORE CONTROL REGISTER (PCSCR) 2–93 EBOX CONTROL REGISTER (ECR) 2–96 CBOX CONTROL REGISTER (CCTL) 2–99 BACKUP CACHE DATA ECC REGISTER (BCDECC) 2–103 BACKUP CACHE ERROR TAG STATUS REGISTER (BCETSTS) 2–105 BACKUP CACHE ERROR TAG INDEX REGISTER (BCETIDX) 2–108 BACKUP CACHE ERROR TAG REGISTER (BCETAG) 2–109 BACKUP CACHE ERROR DATA STATUS REGISTER (BCEDSTS) 2–111 BACKUP CACHE ERROR DATA INDEX REGISTER (BCEDIDX) 2–114 v Contents BACKUP CACHE ERROR DATA ECC REGISTER (BCEDECC) 2–115 CBOX ERROR FILL ADDRESS REGISTER (CEFADR) 2–117 CBOX ERROR FILL STATUS REGISTER (CEFSTS) 2–118 NDAL ERROR STATUS REGISTER (NESTS) 2–123 NDAL ERROR OUTPUT ADDRESS REGISTER (NEOADR) 2–126 NDAL ERROR OUTPUT COMMAND REGISTER (NEOCMD) 2–127 NDAL ERROR DATA HIGH REGISTER (NEDATHI) 2–130 NDAL ERROR DATA LOW REGISTER (NEDATLO) 2–132 NDAL ERROR INPUT COMMAND REGISTER (NEICMD) 2–133 VIC MEMORY ADDRESS REGISTER (VMAR) 2–135 VIC TAG REGISTER (VTAG) 2–137 VIC DATA REGISTER (VDATA) 2–139 IBOX CONTROL AND STATUS REGISTER (ICSR) 2–140 PHYSICAL ADDRESS MODE REGISTER (PAMODE) 2–142 MEMORY MANAGEMENT EXCEPTION ADDRESS REGISTER (MMEADR) 2–143 MEMORY MANAGEMENT EXCEPTION PTE ADDRESS REGISTER (MMEPTE) 2–144 MEMORY MANAGEMENT EXCEPTION STATUS REGISTER (MMESTS) 2–145 TB PARITY ADDRESS REGISTER (TBADR) 2–148 TB PARITY STATUS REGISTER (TBSTS) 2–149 P-CACHE PARITY ADDRESS REGISTER (PCADR) 2–153 P-CACHE STATUS REGISTER (PCSTS) 2–154 P-CACHE CONTROL REGISTER (PCCTL) 2–157 2.7.3 XMI Registers 2–160 NDAL CONTROL AND STATUS REGISTER (NCSR) 2–162 NEXMI INPUT PORT REGISTER (IPORT) 2–168 NEXMI OUTPUT PORT0 REGISTER (OPORT0) 2–170 NEXMI OUTPUT PORT1 REGISTER (OPORT1) 2–172 DEVICE REGISTER (XDEV) 2–173 BUS ERROR REGISTER (XBER) 2–174 FAILING ADDRESS REGISTER (XFADR) 2–181 XMI GENERAL PURPOSE REGISTER (XGPR) 2–185 NODE-SPECIFIC CONTROL AND STATUS REGISTER (NSCSR) 2–186 XMI CONTROL REGISTER (XCR) 2–188 FAILING ADDRESS EXTENSION REGISTER (XFAER) 2–194 BUS ERROR EXTENSION REGISTER (XBEER) 2–197 WRITEBACK 0 FAILING ADDRESS REGISTER (WFADR0) 2–201 WRITEBACK 1 FAILING ADDRESS REGISTER (WFADR1) 2–202 2.8 KA66A CPU MODULE INITIALIZATION, SELF-TEST, AND BOOTING 2–203 2.8.1 Initialization Overview 2–203 vi Contents 2.8.2 Detailed Initialization Description 2–205 2.8.2.1 NVAX CPU Hardware/Microcode Initialization • 2–208 2.8.2.2 Console Initialization • 2–208 2.8.2.3 Unnecessary Explicit Initialization • 2–210 2.8.2.4 Warm Start Initialization • 2–210 2.8.2.5 Node Reset • 2–210 2.8.2.6 Boot Processor Determination • 2–211 2.8.2.7 Memory Configuration • 2–211 2.8.2.7.1 Selection of Interleave • 2–211 2.8.2.7.2 Memory Testing and the Bitmap • 2–212 2.8.2.8 DWMBB Configuration • 2–213 2.8.2.9 DWMVA Configuration • 2–213 2.8.3 Bootstrapping or Restarting the Operating System 2–214 2.8.3.1 Operating System Restart • 2–214 2.8.3.2 Failing Restart • 2–215 2.8.3.3 Restart Parameters • 2–216 2.8.3.4 Operating System Bootstrap • 2–216 2.8.3.5 Boot Algorithm • 2–217 2.8.3.6 Boot Parameters • 2–218 2.8.3.7 Bootstrap Software Sequence • 2–219 2.9 INTERPROCESSOR COMMUNICATION THROUGH THE CONSOLE PROGRAM 2–220 2.9.1 Required Communications Paths 2–220 2.9.2 Console Communications Area 2–221 2.9.3 Sending a Message to Another Processor 2–229 2.10 ERROR HANDLING 2–231 2.10.1 Error State Collection 2–233 2.10.2 Error Analysis 2–236 2.10.3 Error Recovery 2–237 2.10.3.1 Special Considerations when Memory Management Is Off • 2–238 2.10.3.2 Cache Coherence in Error Handling • 2–239 2.10.3.2.1 Disabling and Flushing the Caches (Leaving the B-Cache in ETM) • 2–240 2.10.3.2.2 Enabling the Caches • 2–241 2.10.3.3 Special Writeback Cache Recovery • 2–241 2.10.3.3.1 B-Cache Uncorrectable Error During Writeback • 2–241 2.10.3.3.2 Memory State • 2–241 2.10.3.3.2.1 Accessing Memory State • 2–242 2.10.3.3.2.2 Repairing Memory State (Fill Errors) • 2–242 2.10.3.3.2.3 Repairing Memory State (Tagged-Bad Locations) • 2–243 2.10.3.3.3 Extracting Data from the B-Cache • 2–243 2.10.3.3.4 Address Determination Procedure for Recovery from Uncorrectable B-Cache Data RAM Errors • 2–243 2.10.3.3.5 Special Address Determination Procedure for Recovery from Uncorrectable B-Cache Tag Store Errors • 2–244 2.10.3.4 Cache and TB Test Procedures • 2–245 vii Contents 2.10.3.5 NEXMI Error Handling • 2–245 2.10.4 Error Retry 2–246 2.10.4.1 General Multiple Error Handling Philosophy • 2–246 2.10.4.2 Retry Special Cases • 2–247 2.10.5 Console Halt and Halt Interrupt 2–247 2.10.6 Machine Check Exception 2–249 2.10.6.1 MCHK_UNKNOWN_MSTATUS • 2–259 2.10.6.2 MCHK_INT.ID_VALUE • 2–259 2.10.6.3 MCHK_CANT_GET_HERE • 2–259 2.10.6.4 MCHK_MOVC.STATUS • 2–259 2.10.6.5 MCHK_ASYNC_ERROR • 2–259 2.10.6.5.1 TB Parity Errors • 2–260 2.10.6.5.2 Ebox Stage 3 STALL Timeout Error • 2–260 2.10.6.6 MCHK_SYNC_ERROR • 2–260 2.10.6.6.1 VIC Parity Errors • 2–261 2.10.6.6.2 B-Cache Data RAM Uncorrectable
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  • The Vaxstation 4000 Model 90

    The Vaxstation 4000 Model 90

    The VAXstation 4000 Model 90 By Michael A. Callander, Sr., Lauren M. Carlson, Andrew R. Ladd, Mitchell O. Norcross 1 Abstract The VAXstation 4000 Model 90 is the latest member of the VAXstation product line. Based on the NVAX CPU, the Model 90 was designed as a module upgrade to the VAXstation 4000 Model 60 system. The Model 90 has 2.7 times the CPU performance of the Model 60 and provides base-level, two-dimensional graphics performance of 266,000 vectors per second. It supports up to 128MB of memory, an SCSI-1 bus interface, a TURBOchannel option, a synchronous communication option, and several graphics options. The design team used only programmable devices to implement the new logic designed into the system. In addition, a breadboard provided the basis for logic and software verification. 2 Introduction During the summer of 1991, Digital's Semiconductor Engineering Group began planning a new VAX workstation based on the NVAX CPU chip.[1] The development process had three main goals: to increase CPU performance, to maintain an aggressive time-to-market schedule, and to provide upgrade compatibility with the VAXstation Model 60. The primary goal of the VAXstation 4000 Model 90 design was to implement a workstation with well over twice the CPU performance of its predecessor, the Model 60. The advent of high-performance workstations based on reduced instruction set computers (RISC) required any new VAX workstation to provide a significant performance increase over previous VAX workstations to be competitive in the marketplace. The Model 90 met this goal by achieving 2.7 times the performance of the VAXstation Model 60.