Validated Products List, Volume 1, 1995 No. 1
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Validated Products List, 1995 No. 3: Programming Languages, Database
NISTIR 5693 (Supersedes NISTIR 5629) VALIDATED PRODUCTS LIST Volume 1 1995 No. 3 Programming Languages Database Language SQL Graphics POSIX Computer Security Judy B. Kailey Product Data - IGES Editor U.S. DEPARTMENT OF COMMERCE Technology Administration National Institute of Standards and Technology Computer Systems Laboratory Software Standards Validation Group Gaithersburg, MD 20899 July 1995 QC 100 NIST .056 NO. 5693 1995 NISTIR 5693 (Supersedes NISTIR 5629) VALIDATED PRODUCTS LIST Volume 1 1995 No. 3 Programming Languages Database Language SQL Graphics POSIX Computer Security Judy B. Kailey Product Data - IGES Editor U.S. DEPARTMENT OF COMMERCE Technology Administration National Institute of Standards and Technology Computer Systems Laboratory Software Standards Validation Group Gaithersburg, MD 20899 July 1995 (Supersedes April 1995 issue) U.S. DEPARTMENT OF COMMERCE Ronald H. Brown, Secretary TECHNOLOGY ADMINISTRATION Mary L. Good, Under Secretary for Technology NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY Arati Prabhakar, Director FOREWORD The Validated Products List (VPL) identifies information technology products that have been tested for conformance to Federal Information Processing Standards (FIPS) in accordance with Computer Systems Laboratory (CSL) conformance testing procedures, and have a current validation certificate or registered test report. The VPL also contains information about the organizations, test methods and procedures that support the validation programs for the FIPS identified in this document. The VPL includes computer language processors for programming languages COBOL, Fortran, Ada, Pascal, C, M[UMPS], and database language SQL; computer graphic implementations for GKS, COM, PHIGS, and Raster Graphics; operating system implementations for POSIX; Open Systems Interconnection implementations; and computer security implementations for DES, MAC and Key Management. -
Computer Conservation Society
Issue Number 88 Winter 2019/20 Computer Conservation Society Aims and Objectives The Computer Conservation Society (CCS) is a co-operative venture between BCS, The Chartered Institute for IT; the Science Museum of London; and the Science and Industry Museum (SIM) in Manchester. The CCS was constituted in September 1989 as a Specialist Group of the British Computer Society. It is thus covered by the Royal Charter and charitable status of BCS. The objects of the Computer Conservation Society (“Society”) are: To promote the conservation, restoration and reconstruction of historic computing systems and to identify existing computing systems which may need to be archived in the future; To develop awareness of the importance of historic computing systems; To develop expertise in the conservation, restoration and reconstruction of historic computing systems; To represent the interests of the Society with other bodies; To promote the study of historic computing systems, their use and the history of the computer industry; To publish information of relevance to these objectives for the information of Society members and the wider public. Membership is open to anyone interested in computer conservation and the history of computing. The CCS is funded and supported by a grant from BCS and from donations. There are a number of active projects on specific computer restorations and early computer technologies and software. Younger people are especially encouraged to take part in order to achieve skills transfer. The CCS also enjoys a close relationship with the National Museum of Computing. Resurrection The Journal of the Computer Conservation Society ISSN 0958-7403 Number 88 Winter 2019/20 Contents Society Activity 2 News Round-Up 9 The Data Curator 10 Paul Cockshott From Tea Shops to Computer Company: The Improbable 15 Story of LEO John Aeberhard Book Review: Early Computing in Britain Ferranti Ltd. -
Ece585 Lec2.Pdf
ECE 485/585 Microprocessor System Design Lecture 2: Memory Addressing 8086 Basics and Bus Timing Asynchronous I/O Signaling Zeshan Chishti Electrical and Computer Engineering Dept Maseeh College of Engineering and Computer Science Source: Lecture based on materials provided by Mark F. Basic I/O – Part I ECE 485/585 Outline for next few lectures Simple model of computation Memory Addressing (Alignment, Byte Order) 8088/8086 Bus Asynchronous I/O Signaling Review of Basic I/O How is I/O performed Dedicated/Isolated /Direct I/O Ports Memory Mapped I/O How do we tell when I/O device is ready or command complete? Polling Interrupts How do we transfer data? Programmed I/O DMA ECE 485/585 Simplified Model of a Computer Control Control Data, Address, Memory Data Path Microprocessor Keyboard Mouse [Fetch] Video display [Decode] Printer [Execute] I/O Device Hard disk drive Audio card Ethernet WiFi CD R/W DVD ECE 485/585 Memory Addressing Size of operands Bytes, words, long/double words, quadwords 16-bit half word (Intel: word) 32-bit word (Intel: doubleword, dword) 0x107 64-bit double word (Intel: quadword, qword) 0x106 Note: names are non-standard 0x105 SUN Sparc word is 32-bits, double is 64-bits 0x104 0x103 Alignment 0x102 Can multi-byte operands begin at any byte address? 0x101 Yes: non-aligned 0x100 No: aligned. Low order address bit(s) will be zero ECE 485/585 Memory Operand Alignment …Intel IA speak (i.e. word = 16-bits = 2 bytes) 0x107 0x106 0x105 0x104 0x103 0x102 0x101 0x100 Aligned Unaligned Aligned Unaligned Aligned Unaligned word word Double Double Quad Quad address address word word word word -----0 address address address address -----00 ----000 ECE 485/585 Memory Operand Alignment Why do we care? Unaligned memory references Can cause multiple memory bus cycles for a single operand May also span cache lines Requiring multiple evictions, multiple cache line fills Complicates memory system and cache controller design Some architectures restrict addresses to be aligned Even in architectures without alignment restrictions (e.g. -
VAX 4000 V96-2.3—10 Feb 1997
TM VAX 4000 V96-2.3—10 Feb 1997 DIGITAL Systems and Options Catalog Product Description VAX 4000 systems provide commercial systems performance, high availability, and a compact footprint. They support a wide range of applications and options, including FDDI networks and Q-bus peripherals. System enclosure supports internal storage and Q-bus expansion through a B400X expansion cabinet. VAX 4000 systems come in three packages: Desktop Model 106A, Desktop/Deskside Model 108, and Pedestal/Deskside Model 505A/705A DSSI and Ethernet adapter chips—each driven by a 10-MIP on-chip RISC processor—are tightly integrated on the CPU module with direct access to memory. Digital's DSSI to SCSI HSD10 storage solutions replace DSSI RF36 disk technology in all VAX 4000 systems. Digital’s HSD10 DSSI-to-SCSI controller. mounted internally in system cabinet, supports standard RZxx SCSI storage on VAX 4000 systems while still supporting DSSI clustering. External StorageWorks HSD10 controllers are supported. VAX 4000 Model 106A offers performance of 10-ns NVAX chip. Systems achieve 215 transactions per second (TPS). With internal support for the HSD10, DSSI-to-SCSI controller, VAX 4000 customers can take advantage of low-cost, more flexible and open StorageWorks solutions. VAX 4000 Model 108 offers identical performance, is compatible with Model 106A, but is housed in a new Desktop/Deskside minitower enclosure. In addition, these systems offer enchancements in the memory and storage capacity, supporting up to 512 MB of standard SIMM memory and six storage devices in the system enclosure. VAX 4000 Model 505A and 705A offer 12 ns and 9 ns performance, respectively in a Q-bus Pedestal package. -
I Txso C~T Dc~ 5 SPD / LETTER FC~R
i DIGITAL Digital Equipm~t3t Corporation SOFTW~►,RE Digital Drive SILL OF MATERIALS Westminster, Massachusetts 01473-0471 Option Number Option Title Date Page ~ QA-10 OAA-W55.6 ~rAX FORTF~? V5.6 UPD TK5 0 28-Feb-91 1 of 1 ~TY PICK LOCATION PART NLJL~ER PART DESCRIPTION .~_ -.. 1 *FS* 36-28231-07 TRE~I~ZA~L S~~RCODE LABEL 1 *FS* 99-08545-02 BOOKT~IRAP 1 t UR) AQ-FP 8 6N-BN ~irAX FORTP~AN V5.6 BIN TK5 0 1 ~ DP ~ AV-PF4FA-TK SUP REPLACEMENT LETTER 1 EN-01044-07 SFT'WR PERFOF~!~ANCE REPORT FORM 1 ***** NS ~~~ QA-10 OAA-WZ 5.6 ~irAX FORTF~AN V5.6 UPD DOC 1 *FS* 36-28231-0? THEF~!zA,L P.~ARCODE LABEL 1 *FS* 99-08545-02 BOOKT~IRAP 1 (UR} AE-JF8?L-TE ~irAX FORTP►AN V5.6 SPD 2 5.16.3 6 1 - t~~ AE-LT36H-TE ~irAX FORTP;AN SSA 2 5.16.3 6 -A 1 SDP ) AE -1~tA,5 OA- TK SOFTWARE W TY ADDENDUM 1 tUR~ AV-N672V-TE V'AX FORTP►AN V5.6 PAD FIRS T 1 EN-02512-05 C~3LANGE OF ADDRESS CARD ilk.~ r~~i~li~ilpirfi~~ra~~reis~-~-~~~------~----~~~~ t~ii~~l~+~r~~~-~~~--~--~.r~.~ i Txso c~t Dc~ 5 SPD / LETTER FC~R : AV-PF4FA- TK October, 1990 d 9 Dear Service Customer, Enclosed is a software product update/maintenance release supplied as part of your software maintenance agreement. As part of its planned License Management Zbols program, Digital has initiated replacement of all Service Update PAKs (SUPs) for licensed software product with License Product Authorization Keys (PAKs). -
Validated Processor List
NISTIR 4557 Programming Languages and Database Language SQL VALIDATED PROCESSOR UST Including GOSIP Conformance Testing Registers Judy B. Kailey Editor U.S. DEPARTMENT OF COMMERCE National Institute of Standards and Technology National Computer Systems Laboratory Software Standards Validation Group Gaithersburg, MD 20899 April 1991 (Supersedes January 1991 Issue) U.S. DEPARTMENT OF COMMERCE Robert A. Mosbacher, Secretary NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY John W. Lyons, Director NIST > NISTIR 4557 Programming Languages and Database Language SQL VALIDATED PROCESSOR LIST Including GOSIP Conformance Testing Registers Judy B. Kailey Editor U.S. DEPARTMENT OF COMMERCE National Institute of Standards and Technology National Computer Systems Laboratory Software Standards Validation Group Gaithersburg, MD 20899 April 1991 (Supersedes January 1991 Issue) U.S. DEPARTMENT OF COMMERCE Robert A. Mosbacher, Secretary NATIONAL INSTITUTE OF STANDARDS AND TECHNOLOGY John W. Lyons, Director lib t TABLE OF CONTENTS 1. INTRODUCTION 1 1.1 Purpose 1 1.2 Document Organization 1 1.2.1 Language Processors 1 1.2.2 Contributors to the VPL 2 1.2.3 Other FIPS Conformance Testing Products 2 1.2.4 GOSIP Registers 2 1.3 FIPS Programming and Database Language Standards 3 1.4 Validation of Processors 3 1.4.1 Validation Requirements 3 1.4.2 Placement in the List 4 1.4.3 Removal from the List 4 1.4.4 Validation Procedures 4 1.5 Certificate of Validation 4 1.6 Registered Report 4 1.7 Processor Validation Suites 5 2. COBOL PROCESSORS 7 3. FORTRAN PROCESSORS 13 4. Ada PROCESSORS 21 5. Pascal PROCESSORS 35 6. SQL PROCESSORS 37 APPENDIX A CONTRIBUTORS TO THE LIST A-1 APPENDIX B OTHER FIPS CONFORMANCE TESTING B-1 APPENDIX C REGISTER OF GOSIP ABSTRACT TEST SUITES C-1 APPENDIX D REGISTER OF GOSIP MEANS OF TESTING D-1 APPENDIX E REGISTER OF GOSIP CONFORMANCE TESTING LABORATORIES E-1 . -
Avaya Aura® Communication Manager Hardware Description and Reference
Avaya Aura® Communication Manager Hardware Description and Reference Release 7.0.1 555-245-207 Issue 2 May 2016 © 2015-2016, Avaya, Inc. Link disclaimer All Rights Reserved. Avaya is not responsible for the contents or reliability of any linked Notice websites referenced within this site or Documentation provided by Avaya. Avaya is not responsible for the accuracy of any information, While reasonable efforts have been made to ensure that the statement or content provided on these sites and does not information in this document is complete and accurate at the time of necessarily endorse the products, services, or information described printing, Avaya assumes no liability for any errors. Avaya reserves or offered within them. Avaya does not guarantee that these links will the right to make changes and corrections to the information in this work all the time and has no control over the availability of the linked document without the obligation to notify any person or organization pages. of such changes. Licenses Warranty THE SOFTWARE LICENSE TERMS AVAILABLE ON THE AVAYA Avaya provides a limited warranty on Avaya hardware and software. WEBSITE, HTTPS://SUPPORT.AVAYA.COM/LICENSEINFO, Refer to your sales agreement to establish the terms of the limited UNDER THE LINK “AVAYA SOFTWARE LICENSE TERMS (Avaya warranty. In addition, Avaya’s standard warranty language, as well as Products)” OR SUCH SUCCESSOR SITE AS DESIGNATED BY information regarding support for this product while under warranty is AVAYA, ARE APPLICABLE TO ANYONE WHO DOWNLOADS, available to Avaya customers and other parties through the Avaya USES AND/OR INSTALLS AVAYA SOFTWARE, PURCHASED Support website: https://support.avaya.com/helpcenter/ FROM AVAYA INC., ANY AVAYA AFFILIATE, OR AN AVAYA getGenericDetails?detailId=C20091120112456651010 under the link CHANNEL PARTNER (AS APPLICABLE) UNDER A COMMERCIAL “Warranty & Product Lifecycle” or such successor site as designated AGREEMENT WITH AVAYA OR AN AVAYA CHANNEL PARTNER. -
Alpha and VAX Comparison Based on Industry-Standard Benchmark
Alpha and VAX Comparison based on Industry-standard Benchmark Results Digital Equipment Corporation December 1994 EC-N3909-10 Version 3.0 December 1994 The information in this document is subject to change without notice and should not be construed as a commitment by Digital Equipment Corporation. Digital Equipment Corporation assumes no responsibility for any errors that may appear in this document. Digital conducts its business in a manner that conserves the environment and protects the safety and health of its employees, customers, and the community. Restricted Rights: Use, duplication, or disclosure by the U.S. Government is subject to restrictions as set forth in subparagraph (c) (1 )(ii) of the Rights in Technical Data and Computer Software clause at DFARS 252.227 7013. Copyright© 1994 Digital Equipment Corporation All rights reserved. Printed in U.S.A. The following are trademarks of Digital Equipment Corporation: AlphaServer, AlphaStation, AlphaGeneration, DEC, OpenVMS, VMS, ULTRIX, and the DIGITAL logo. The following are third-party trademarks: MIPS is a trademark of MIPS Computer Systems, Inc. TPC-A is a trademark of the Transaction Processing Performance Council. INFORMIX is a registered trademark of lnformix Software, Inc. OSF/1 is a registered trademark of the Open Software Foundation, Inc. ORACLE is a registered trademark of Oracle Corporation. SPEC, SPECfp92, and SPECratio are trademarks of Standard Performance Evaluation Corporation. MIPS is a trademark of MIPS Computer Systems, Inc. All other trademarks and registered -
Reverse Engineering X86 Processor Microcode
Reverse Engineering x86 Processor Microcode Philipp Koppe, Benjamin Kollenda, Marc Fyrbiak, Christian Kison, Robert Gawlik, Christof Paar, and Thorsten Holz, Ruhr-University Bochum https://www.usenix.org/conference/usenixsecurity17/technical-sessions/presentation/koppe This paper is included in the Proceedings of the 26th USENIX Security Symposium August 16–18, 2017 • Vancouver, BC, Canada ISBN 978-1-931971-40-9 Open access to the Proceedings of the 26th USENIX Security Symposium is sponsored by USENIX Reverse Engineering x86 Processor Microcode Philipp Koppe, Benjamin Kollenda, Marc Fyrbiak, Christian Kison, Robert Gawlik, Christof Paar, and Thorsten Holz Ruhr-Universitat¨ Bochum Abstract hardware modifications [48]. Dedicated hardware units to counter bugs are imperfect [36, 49] and involve non- Microcode is an abstraction layer on top of the phys- negligible hardware costs [8]. The infamous Pentium fdiv ical components of a CPU and present in most general- bug [62] illustrated a clear economic need for field up- purpose CPUs today. In addition to facilitate complex and dates after deployment in order to turn off defective parts vast instruction sets, it also provides an update mechanism and patch erroneous behavior. Note that the implementa- that allows CPUs to be patched in-place without requiring tion of a modern processor involves millions of lines of any special hardware. While it is well-known that CPUs HDL code [55] and verification of functional correctness are regularly updated with this mechanism, very little is for such processors is still an unsolved problem [4, 29]. known about its inner workings given that microcode and the update mechanism are proprietary and have not been Since the 1970s, x86 processor manufacturers have throughly analyzed yet. -
Digital Technical Journal, Volume 6, Number 4: RAID Array Controllers
RAID Away Controllers Workflvw Models PC LAN and System Management Tools Digital Technical Journal Digital Equipment Corporation Editorial Advisory Board Jane C. Blake, Managing Editor Samuel H. Fuller, Chairman Kathleen M. Stetson, Editor Richard W Beane Helen L. Patterson, Editor Donald 2. Harbert Circulation William R. Hawe Catherine M. Phillips, Administrator RichardJ. Hollingsworth Dorothea B. Cassady, Secretary Richard E Lary Alan G. Nemeth Production Jean A. Proulx Terri Autieri, Production Editor Robert M. Supnik Anne S. Katzeff, Typographer Gayn B. Winters Peter R. Woodbury, Illustrator The Digital TechnicalJournal is a refereed journal published quarterly by Digital Equipment Corporation, 30 Porter Road LJ02/D10, Littleton, Massachusetts 01460. Subscriptionsto the Journal are $40.00 (non-U.S. $60) for four issues and $75.00 (non-U.S. $115) for eight issues and must be prepaid in U.S. funds. University and college professors and Ph.D. students in the electrical engineering and computer science fields receive complimentary subscriptions upon request. Orders, inquiries, and address changes should be sent to the Digital TechnicalJournal at the published- by address. Inquiries can also be sent electronically to [email protected] copies and back issues are available for $16.00 each by calling DECdirect at 1-800-DIGITAL (1-800-344-4825). Recent back issues of the Journal are also available on the Internet at http://www.digital.com/info/DTJ/home.html. Complete Digital Internet listings can be obtained by sending an electronic mail message to [email protected]. Digital employees may order subscriptions through Readers Choice by entering VTX PROFILE at the system prompt. -
Computer Architectures an Overview
Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements. -
Modern Processor Design: Fundamentals of Superscalar
Fundamentals of Superscalar Processors John Paul Shen Intel Corporation Mikko H. Lipasti University of Wisconsin WAVELAND PRESS, INC. Long Grove, Illinois To Our parents: Paul and Sue Shen Tarja and Simo Lipasti Our spouses: Amy C. Shen Erica Ann Lipasti Our children: Priscilla S. Shen, Rachael S. Shen, and Valentia C. Shen Emma Kristiina Lipasti and Elias Joel Lipasti For information about this book, contact: Waveland Press, Inc. 4180 IL Route 83, Suite 101 Long Grove, IL 60047-9580 (847) 634-0081 info @ waveland.com www.waveland.com Copyright © 2005 by John Paul Shen and Mikko H. Lipasti 2013 reissued by Waveland Press, Inc. 10-digit ISBN 1-4786-0783-1 13-digit ISBN 978-1-4786-0783-0 All rights reserved. No part of this book may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without permission in writing from the publisher. Printed in the United States of America 7 6 5 4 3 2 1 Table of Contents PrefaceAbout the Authors x ix 1 Processor Design 1 1.1 The Evolution of Microprocessors 2 1.21.2.1 Instruction Digital Set Systems Processor Design Design 44 1.2.2 Architecture,Realization Implementation, and 5 1.2.3 Instruction Set Architecture 6 1.2.4 Dynamic-Static Interface 8 1.3 Principles of Processor Performance 10 1.3.1 Processor Performance Equation 10 1.3.2 Processor Performance Optimizations 11 1.3.3 Performance Evaluation Method 13 1.4 Instruction-Level Parallel Processing 16 1.4.1 From Scalar to Superscalar 16 1.4.2 Limits of Instruction-Level Parallelism 24 1.51.4.3 Machines Summary for Instruction-Level