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I960 CA/CF Microprocessor User's Manual

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I960 CA/CF Microprocessor User's Manual i960® CA/CF Microprocessor User’s Manual March 1994 Order Number: 270710-003 Intel Corporation makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein. Intel retains the right to make changes to these specifications at any time, without notice. Contact your local Intel sales office or your distributor to obtain the latest specifications before placing your product order. MDS is an ordering code only and is not used as a product name or trademark of Intel Corporation. Intel Corporation and Intel's FASTPATH are not affiliated with Kinetics, a division of Excelan, Inc. or its FASTPATH trademark or products. *Other brands and names are the property of their respective owners. Additional copies of this document or other Intel literature may be obtained from: Intel Corporation Literature Sales P.O. Box 7641 Mt. Prospect, IL 60056-7641 or call 1-800-879-4683 © INTEL CORPORATION 1994 CONTENTS CHAPTER 1 INTRODUCTION 1.1 i960® MICROPROCESSOR ARCHITECTURE ............................................................ 1-1 1.1.1 Parallel Instruction Execution .................................................................................. 1-1 1.1.2 Full Procedure Call Model ....................................................................................... 1-3 1.1.3 Versatile Instruction Set and Addressing ................................................................ 1-3 1.1.4 Integrated Priority Interrupt Model ........................................................................... 1-3 1.1.5 Complete Fault Handling and Debug Capabilities ................................................... 1-4 1.2 SYSTEM INTEGRATION.............................................................................................. 1-4 1.2.1 Pipelined Burst Bus Control Unit ............................................................................. 1-4 1.2.2 Flexible DMA Controller .......................................................................................... 1-4 1.2.3 Priority Interrupt Controller ...................................................................................... 1-5 1.3 ABOUT THIS MANUAL................................................................................................. 1-5 1.4 NOTATION AND TERMINOLOGY................................................................................ 1-6 1.4.1 Reserved and Preserved ......................................................................................... 1-6 1.4.2 Specifying Bit and Signal Values ............................................................................. 1-7 1.4.3 Representing Numbers ........................................................................................... 1-7 1.4.4 Register Names ....................................................................................................... 1-7 CHAPTER 2 PROGRAMMING ENVIRONMENT 2.1 OVERVIEW................................................................................................................... 2-1 2.2 REGISTERS AND LITERALS AS INSTRUCTION OPERANDS .................................. 2-1 2.2.1 Global Registers ...................................................................................................... 2-2 2.2.2 Local Registers ........................................................................................................ 2-3 2.2.3 Special Function Registers (SFRs) ......................................................................... 2-4 2.2.4 Register Scoreboarding ........................................................................................... 2-4 2.2.5 Literals ..................................................................................................................... 2-5 2.2.6 Register and Literal Addressing and Alignment ...................................................... 2-5 2.3 CONTROL REGISTERS............................................................................................... 2-6 2.4 ARCHITECTURE-DEFINED DATA STRUCTURES ..................................................... 2-8 2.5 MEMORY ADDRESS SPACE....................................................................................... 2-9 2.5.1 Memory Requirements .......................................................................................... 2-10 2.5.2 Data and Instruction Alignment in the Address Space .......................................... 2-11 2.5.3 Byte, Word and Bit Addressing ............................................................................. 2-11 2.5.4 Internal Data RAM ................................................................................................. 2-12 2.5.5 Instruction Cache .................................................................................................. 2-13 2.5.6 Data Cache (80960CF Only) ................................................................................. 2-14 2.6 PROCESSOR-STATE REGISTERS........................................................................... 2-14 2.6.1 Instruction Pointer (IP) Register ............................................................................ 2-15 2.6.2 Arithmetic Controls (AC) Register ......................................................................... 2-15 2.6.2.1 Initializing and Modifying the AC Register ...................................................... 2-16 2.6.2.2 Condition Code .............................................................................................. 2-16 iii CONTENTS 2.6.3 Process Controls (PC) Register ............................................................................. 2-17 2.6.3.1 Initializing and Modifying the PC Register ...................................................... 2-19 2.6.4 Trace Controls (TC) Register ................................................................................. 2-20 2.7 USER SUPERVISOR PROTECTION MODEL............................................................ 2-20 2.7.1 Supervisor Mode Resources ................................................................................. 2-20 2.7.2 Using the User-Supervisor Protection Model ......................................................... 2-21 CHAPTER 3 DATA TYPES AND MEMORY ADDRESSING MODES 3.1 DATA TYPES ................................................................................................................ 3-1 3.1.1 Integers .................................................................................................................... 3-2 3.1.2 Ordinals ................................................................................................................... 3-3 3.1.3 Bits and Bit Fields .................................................................................................... 3-3 3.1.4 Triple and Quad Words ........................................................................................... 3-4 3.1.5 Data Alignment ........................................................................................................ 3-4 3.2 BYTE ORDERING......................................................................................................... 3-4 3.3 MEMORY ADDRESSING MODES ............................................................................... 3-5 3.3.1 Absolute ................................................................................................................... 3-6 3.3.2 Register Indirect ...................................................................................................... 3-6 3.3.3 Index with Displacement .......................................................................................... 3-7 3.3.4 IP with Displacement ............................................................................................... 3-7 3.3.5 Addressing Mode Examples .................................................................................... 3-7 CHAPTER 4 INSTRUCTION SET SUMMARY 4.1 INSTRUCTION FORMATS ........................................................................................... 4-1 4.1.1 Assembly Language Format .................................................................................... 4-1 4.1.2 Branch Prediction .................................................................................................... 4-2 4.1.3 Instruction Encoding Formats .................................................................................. 4-2 4.1.4 Instruction Operands ............................................................................................... 4-3 4.2 INSTRUCTION GROUPS ............................................................................................. 4-4 4.2.1 Data Movement ....................................................................................................... 4-5 4.2.1.1 Load and Store Instructions ............................................................................. 4-5 4.2.1.2 Move ................................................................................................................. 4-6 4.2.1.3 Load Address ................................................................................................... 4-6 4.2.2 Arithmetic ................................................................................................................. 4-6 4.2.2.1 Add, Subtract, Multiply and Divide ................................................................... 4-7 4.2.2.2 Extended Arithmetic
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