DOCSLIB.ORG

Covering the Spectrum of Intel Communications Products

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text

Load more

NOTE: PLEASE ADJUST SPINE TO PROPER WIDTH The Communications and Embedded Products Source Book Source The Communications and Embedded Products The Communications Intel Corporation United States and Canada Intel Corporation Robert Noyce Building and Embedded Products 2200 Mission College Boulevard P.O. Box 58119 Santa Clara, CA 95052-8119 Source Book 2004 USA Phone: (408) 765-8080 Europe Intel Corporation (UK) Ltd. Pipers Way Swindon Wiltshire SN3 1RJ UK Phone: England (44) 1793 403 000 France (33) 1 4694 7171 Germany (49) 89 99143 0 Italy (39) 02 575 441 Israel (972) 2 589 7111 Netherlands (31) 20 659 1800 Asia Pacific Intel Semiconductor Ltd. 32/F Two Pacific Place 88 Queensway, Central Hong Kong SAR Phone: (852) 2844-4555 Japan Intel Kabushiki Kaisha P.O. Box 300-8603 Tsukuba-gakuen May 2004 5-6 Tokodai, Tsukuba-shi Ibaraki-ken 300-2635 Japan Phone: (81) 298-47-8511 South America Intel Semicondutores do Brasil Av. Dr Chucri Zaidan, 940- 10th floor Market Place Tower II 04583-906 Sao Paulo-SP-Brasil Phone: (55) 11 3365 5500 Copyright © 2004 Intel Corporation Intel, and the Intel logo are registered trademarks of Intel Corporation. * Other names and brands may be claimed as the property of others. Printed in USA/2004/10K/MD/HP Covering the spectrum Order No. 272676-012 of Intel communications products Communications and Embedded Products Source Book elcome to The Intel Communications and Embedded Products Sourcebook—2004, your Wcomplete reference guide for Intel’s Communications and Embedded products. As you look through this sourcebook, you will note that all of the sections have been updated to include the latest released products. As this sourcebook will only be updated once a year,. we recommend you look on www.developer.intel.com website to get the very latest product information. Table of Contents PROCESSORS AND CHIPSETS Embedded Intel® Architecture Overview . 1 Intel® Personal Internet Client Architecture . .20 Embedded PXA Processor Overview . .35 Intel XScale® Microarchitecture . .38 INTEL® FLASH MEMORY FOR WIRELESS APPLICATIONS Intel® Stacked Chip Scale Packaging Products . .41 1.8 Volt Intel StrataFlash® Wireless Memory (L18/L30) . .44 1.8 Volt Intel® Wireless Flash Memory (W18/W30) . .44 Intel® Flash Memory Software . .46 INTEL® FLASH MEMORY FOR EMBEDDED APPLICATIONS 3 Volt Intel StrataFlash® Memory (J3 Family) . .49 Intel® Advanced+ Boot Block Flash Memory (C3/B3 Family) . .50 3 Volt Synchronous Intel StrataFlash® Memory (K3/K18 Family) . .50 Intel® Flash Memory Development Tools . .51 I/O PRODUCTS Intel’s I/O Processors (IOP) . .55 NETWORK PROCESSORS Intel® IXP2xxx Network Processor Product Line . .61 Intel® IXP4xx Network Processor Product Line . .67 NETWORKING PRODUCTS Workgroup and Enterprise Solutions . .73 ADVANCED ETHERNET CONTROLLERS—PCI BASED Intel’s 10/100/1000 Ethernet Controllers (MAC/Phy) . .81 Intel’s 10/100 Ethernet Controllers (MAC/Phy) . .83 OPTICAL PRODUCTS Optical Products . .85 TELECOM PRODUCTS Silicon Transmission Products . .111 Telecom Boards and Platforms . .117 Telecom Boards . .121 Telecom Platforms . .146 Telecom Software . .152 BRIDGE PRODUCTS Transparent PCI-to-PCI Bridges . .163 Transparent PCI-X Bridge . .164 Non-transparent PCI-to-PCI Bridges . .165 PCI-X Serial ATA Host Disk Controller . .166 MICROCONTROLLERS MCS® 96 Microcontrollers . .167 MCS® 251 Microcontrollers . .174 MCS® 51 Microcontrollers . .177 Interconnect Devices . .179 SOFTWARE Software for EID Products . .181 Intel® Embedded Chipset Device Driver support matrix . .186 COMMUNICATIONS AND EMBEDDED DEVELOPER’S NETWORKS Intel® Communications Alliance . .193 Intel™ Personal Client Architecture Developer Network . .194 DEVELOPMENT TOOLS AND SUPPORT Comprehensive Support for Embedded Products . .195 DISTRIBUTOR AND MANUFACTURING REPRESENTATIVES Distributor and Manufacturing Representatives . 203 developer.intel.com/design/intarch Processors and Chipsets 1 Embedded Intel® Architecture mbedded Intel® Architecture (IA) enables embedded system designers to choose from multiple levels of integration, Eranging from Intel® processors and chipsets to validated reference designs and highly integrated modular platforms. Whatever level of integration you choose, Intel and its world-class ecosystem provide the building blocks and tools you need to make your embedded solutions run better, faster and further. ■ Based on emerging industry standards, IA processors are compatible with leading operating systems and supported by a broad third-party ecosystem. Modularity, scalability and standards-based design help customers accelerate time-to-market and reduce cost. ■ Embedded Intel® Architecture chipsets provide a reliable platform for high-performance connected embedded applications with the performance, stability, and reliability customers require for embedded computing applications. Intel® chipsets and drivers can help reduce support costs, validation costs, and offer a variety of sell-up opportunities while still providing flexibility and performance at value pricing. ■ Embedded IA reference designs and configurations support developers in a variety of market segments including communications, digital security surveillance, interactive clients, storage, learning solutions and print imaging. They may be used off-the-shelf as a market-ready design, or further customized to support additional value-added features. ■ Intel provides a wide selection of development kits designed to minimize customers’ development efforts and facilitate quick time-to-market. Kits include supporting documents and evaluation software from independent software vendors. ■ Intel provides developers with software resources and tools to accelerate the successful development and delivery of IA-based solutions. Intel® Embedded Graphics Drivers specifically target the needs of embedded platform developers, offering an alternative to drivers designed for the desktop and mobile market segments. ■ Implementation-ready boards and systems from Intel and third-party vendors are also available to meet your most stringent time-to-market requirements: www.intel.com/info/eia. Intel® Xeon™ Processor he Intel® Xeon™ processor with 512 KB L2 cache and the Low Voltage Intel® Xeon™ processor are the solutions for Tapplications that demand the highest levels of performance in the communications market segment. The Low Voltage Intel Xeon processor has the additional benefit of lower thermal design power, making it ideal for thermally-sensitive, space- constrained environments. Based on the Intel NetBurst® microarchitecture, they feature a 400 MHz and 533MHz system bus, 512KB L2 cache, dual-processor capability, and Hyper-Threading Technology which allows a single physical processor to process two threads of data simultaneously. Support for the Intel Xeon processor with 512 KB L2 cache includes 2.0, 2.4 and 2.8 GHz and 1.6, 2.0 and 2.4 GHz for the Low Voltage Intel Xeon processor. The Intel Xeon processor with 512 KB L2 cache and the Low Voltage Intel Xeon processor are validated with the Intel® E7500 and the Intel® E7501 chipsets. These chipset designs deliver maximized system bus, memory, and I/O bandwidth to enhance performance, scalability, and end-user productivity. INTEL® XEON™ PROCESSOR WITH 512KB L2 CACHE CORE SPEED EXTERNAL L2 THERMAL DESIGN PRODUCT NUMBER (GHz) BUS SPEED (MHz) CACHE POWER VOLTAGE TCAS PACKAGE RK80532KE072512 2.8 533 512K 74.0W 1.5V 75°C 604-pin FC-mPGA-2p RK80532KE056512 2.4 533 512K 65.0W 1.5V 74°C 604-pin FC-mPGA-2p RN80532KC041512 2.0 400 512K 58.0W 1.5V 70°C 603-pinINT3 LOW VOLTAGE INTEL® XEON™ PROCESSOR CORE SPEED EXTERNAL L2 THERMAL DESIGN PRODUCT NUMBER (GHz) BUS SPEED (MHz) CACHE POWER VOLTAGE TCASE PACKAGE RK80532EE056512 2.4 533 512K 40.0W 1.3V 81°C 604-pin FC-mPGA-2p RK80532EC041512 2.0 400 512K 35.0W 1.3V 83°C 604-pin FC-mPGA-2p RK80532EC025512 1.6 400 512K 30.0W 1.3V 81°C 604-pin FC-mPGA-2p 2 Processors and Chipsets developer.intel.com/design/intarch Intel® Pentium® 4 Processor, Intel® Pentium® 4 Processor with Hyper-Threading (HT) Technology, and Intel® Pentium® 4 processor - M he Intel® Pentium® 4 processor family, with Intel NetBurst® microarchitecture, delivers performance to meet the growing Tdemands of a new generation of leading-edge products, with scalability that helps minimize your total cost-of-ownership. These embedded processors provide the performance headroom needed to meet the heavy application demands of networking, communications and storage appliances, sophisticated interactive clients, industrial automation solutions, digital security surveillance platforms, and imaging devices. For reliable embedded platform designs, the Intel Pentium 4 processor is validated with the Intel® 845 chipset, the Intel® 845E chipset, the Intel® 845GV chipset, the Intel® 852GME chipset, and the Intel® 875P chipset. The Intel Pentium 4 processor - M is validated with the Intel 845E chipset. The Intel® Pentium® 4 Processor with HT Technology is validated with the Intel 875P chipset. Intel Pentium 4 processor-based platforms include integrated graphics, and support the high- bandwidth I/O performance of USB 2.0 and Gigabit Ethernet networking. Rapid platform development is supported by the latest operating systems, applications and Intel® Architecture development tools, as well as a variety of validated reference designs from Intel. While incorporating Intel’s most advanced embedded processor technologies, these processors are software-compatible with previous Intel® Architecture processors. INTEL® PENTIUM® 4 PROCESSOR WITH HYPER-THREADING TECHNOLOGY
Recommended publications
  • Reviving the Development of Openchrome

    Reviving the Development of Openchrome

    Reviving the Development of OpenChrome Kevin Brace OpenChrome Project Maintainer / Developer XDC2017 September 21st, 2017 Outline ● About Me ● My Personal Story Behind OpenChrome ● Background on VIA Chrome Hardware ● The History of OpenChrome Project ● Past Releases ● Observations about Standby Resume ● Developmental Philosophy ● Developmental Challenges ● Strategies for Further Development ● Future Plans 09/21/2017 XDC2017 2 About Me ● EE (Electrical Engineering) background (B.S.E.E.) who specialized in digital design / computer architecture in college (pretty much the only undergraduate student “still” doing this stuff where I attended college) ● Graduated recently ● First time conference presenter ● Very experienced with Xilinx FPGA (Spartan-II through 7 Series FPGA) ● Fluent in Verilog / VHDL design and verification ● Interest / design experience with external communication interfaces (PCI / PCIe) and external memory interfaces (SDRAM / DDR3 SDRAM) ● Developed a simple DMA engine for PCI I/F validation w/Windows WDM (Windows Driver Model) kernel device driver ● Almost all the knowledge I have is self taught (university engineering classes were not very useful) 09/21/2017 XDC2017 3 Motivations Behind My Work ● General difficulty in obtaining meaningful employment in the digital hardware design field (too many students in the field, difficulty obtaining internship, etc.) ● Collects and repairs abandoned computer hardware (It’s like rescuing puppies!) ● Owns 100+ desktop computers and 20+ laptop computers (mostly abandoned old stuff I
  • THINC: a Virtual and Remote Display Architecture for Desktop Computing and Mobile Devices

    THINC: a Virtual and Remote Display Architecture for Desktop Computing and Mobile Devices

    THINC: A Virtual and Remote Display Architecture for Desktop Computing and Mobile Devices Ricardo A. Baratto Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in the Graduate School of Arts and Sciences COLUMBIA UNIVERSITY 2011 c 2011 Ricardo A. Baratto This work may be used in accordance with Creative Commons, Attribution-NonCommercial-NoDerivs License. For more information about that license, see http://creativecommons.org/licenses/by-nc-nd/3.0/. For other uses, please contact the author. ABSTRACT THINC: A Virtual and Remote Display Architecture for Desktop Computing and Mobile Devices Ricardo A. Baratto THINC is a new virtual and remote display architecture for desktop computing. It has been designed to address the limitations and performance shortcomings of existing remote display technology, and to provide a building block around which novel desktop architectures can be built. THINC is architected around the notion of a virtual display device driver, a software-only component that behaves like a traditional device driver, but instead of managing specific hardware, enables desktop input and output to be intercepted, manipulated, and redirected at will. On top of this architecture, THINC introduces a simple, low-level, device-independent representation of display changes, and a number of novel optimizations and techniques to perform efficient interception and redirection of display output. This dissertation presents the design and implementation of THINC. It also intro- duces a number of novel systems which build upon THINC's architecture to provide new and improved desktop computing services. The contributions of this dissertation are as follows: • A high performance remote display system for LAN and WAN environments.
  • Wearable Mixed Reality System in Less Than 1 Pound

    Wearable Mixed Reality System in Less Than 1 Pound

    Eurographics Symposium on Virtual Environments (2006) Roger Hubbold and Ming Lin (Editors) Wearable Mixed Reality System In Less Than 1 Pound Achille Peternier,1 Frédéric Vexo1 and Daniel Thalmann1 1Virtual Reality Laboratory (VRLab), École Polytechnique Fédérale de Lausanne (EPFL), 1015 Lausanne, Switzerland Abstract We have designed a wearable Mixed Reality (MR) framework which allows to real-time render game-like 3D scenes on see-through head-mounted displays (see through HMDs) and to localize the user position within a known internet wireless area. Our equipment weights less than 1 Pound (0.45 Kilos). The information visualized on the mobile device could be sent on-demand from a remote server and realtime rendered onboard. We present our PDA-based platform as a valid alternative to use in wearable MR contexts under less mobility and encumbering constraints: our approach eliminates the typical backpack with a laptop, a GPS antenna and a heavy HMD usually required in this cases. A discussion about our results and user experiences with our approach using a handheld for 3D rendering is presented as well. 1. Introduction also few minutes to put on or remove the whole system. Ad- ditionally, a second person is required to help him/her in- The goal of wearable Mixed Reality is to give more infor- stalling the framework for the first time. Gleue and Daehne mation to users by mixing it with the real world in the less pointed the encumbering, even if limited, of their platform invasive way. Users need to move freely and comfortably and the need of a skilled technician for the maintenance of when wear such systems, in order to improve their expe- their system [GD01].
  • Ece585 Lec2.Pdf

    Ece585 Lec2.Pdf

    ECE 485/585 Microprocessor System Design Lecture 2: Memory Addressing 8086 Basics and Bus Timing Asynchronous I/O Signaling Zeshan Chishti Electrical and Computer Engineering Dept Maseeh College of Engineering and Computer Science Source: Lecture based on materials provided by Mark F. Basic I/O – Part I ECE 485/585 Outline for next few lectures Simple model of computation Memory Addressing (Alignment, Byte Order) 8088/8086 Bus Asynchronous I/O Signaling Review of Basic I/O How is I/O performed Dedicated/Isolated /Direct I/O Ports Memory Mapped I/O How do we tell when I/O device is ready or command complete? Polling Interrupts How do we transfer data? Programmed I/O DMA ECE 485/585 Simplified Model of a Computer Control Control Data, Address, Memory Data Path Microprocessor Keyboard Mouse [Fetch] Video display [Decode] Printer [Execute] I/O Device Hard disk drive Audio card Ethernet WiFi CD R/W DVD ECE 485/585 Memory Addressing Size of operands Bytes, words, long/double words, quadwords 16-bit half word (Intel: word) 32-bit word (Intel: doubleword, dword) 0x107 64-bit double word (Intel: quadword, qword) 0x106 Note: names are non-standard 0x105 SUN Sparc word is 32-bits, double is 64-bits 0x104 0x103 Alignment 0x102 Can multi-byte operands begin at any byte address? 0x101 Yes: non-aligned 0x100 No: aligned. Low order address bit(s) will be zero ECE 485/585 Memory Operand Alignment …Intel IA speak (i.e. word = 16-bits = 2 bytes) 0x107 0x106 0x105 0x104 0x103 0x102 0x101 0x100 Aligned Unaligned Aligned Unaligned Aligned Unaligned word word Double Double Quad Quad address address word word word word -----0 address address address address -----00 ----000 ECE 485/585 Memory Operand Alignment Why do we care? Unaligned memory references Can cause multiple memory bus cycles for a single operand May also span cache lines Requiring multiple evictions, multiple cache line fills Complicates memory system and cache controller design Some architectures restrict addresses to be aligned Even in architectures without alignment restrictions (e.g.
  • Avaya Aura® Communication Manager Hardware Description and Reference

    Avaya Aura® Communication Manager Hardware Description and Reference

    Avaya Aura® Communication Manager Hardware Description and Reference Release 7.0.1 555-245-207 Issue 2 May 2016 © 2015-2016, Avaya, Inc. Link disclaimer All Rights Reserved. Avaya is not responsible for the contents or reliability of any linked Notice websites referenced within this site or Documentation provided by Avaya. Avaya is not responsible for the accuracy of any information, While reasonable efforts have been made to ensure that the statement or content provided on these sites and does not information in this document is complete and accurate at the time of necessarily endorse the products, services, or information described printing, Avaya assumes no liability for any errors. Avaya reserves or offered within them. Avaya does not guarantee that these links will the right to make changes and corrections to the information in this work all the time and has no control over the availability of the linked document without the obligation to notify any person or organization pages. of such changes. Licenses Warranty THE SOFTWARE LICENSE TERMS AVAILABLE ON THE AVAYA Avaya provides a limited warranty on Avaya hardware and software. WEBSITE, HTTPS://SUPPORT.AVAYA.COM/LICENSEINFO, Refer to your sales agreement to establish the terms of the limited UNDER THE LINK “AVAYA SOFTWARE LICENSE TERMS (Avaya warranty. In addition, Avaya’s standard warranty language, as well as Products)” OR SUCH SUCCESSOR SITE AS DESIGNATED BY information regarding support for this product while under warranty is AVAYA, ARE APPLICABLE TO ANYONE WHO DOWNLOADS, available to Avaya customers and other parties through the Avaya USES AND/OR INSTALLS AVAYA SOFTWARE, PURCHASED Support website: https://support.avaya.com/helpcenter/ FROM AVAYA INC., ANY AVAYA AFFILIATE, OR AN AVAYA getGenericDetails?detailId=C20091120112456651010 under the link CHANNEL PARTNER (AS APPLICABLE) UNDER A COMMERCIAL “Warranty & Product Lifecycle” or such successor site as designated AGREEMENT WITH AVAYA OR AN AVAYA CHANNEL PARTNER.
  • Leveraging Integrated Cryptographic Service Facility

    Leveraging Integrated Cryptographic Service Facility

    Front cover Leveraging Integrated Cryptographic Service Facility Lydia Parziale Redpaper International Technical Support Organization Leveraging Integrated Cryptographic Service Facility January 2018 REDP-5431-00 Note: Before using this information and the product it supports, read the information in “Notices” on page v. First Edition (January 2018) This edition applies to Version 2 Release 3 of IBM z/OS (product number 5650-ZOS). © Copyright International Business Machines Corporation 2018. All rights reserved. Note to U.S. Government Users Restricted Rights -- Use, duplication or disclosure restricted by GSA ADP Schedule Contract with IBM Corp. Contents Notices . .v Trademarks . vi Preface . vii Authors. vii Now you can become a published author, too! . vii Comments welcome. viii Stay connected to IBM Redbooks . viii Chapter 1. Overview . 1 1.1 The need for cryptography . 2 1.2 Cryptographic architectures . 3 1.2.1 PKCS #11 . 3 1.2.2 IBM Common Cryptographic Architecture. 3 1.3 System Authorization Facility . 4 1.4 What ICSF is . 5 1.4.1 ICSF services . 5 1.4.2 ICSF options . 6 1.4.3 SAF-protecting ICSF services and IBM CCA Keys. 8 Chapter 2. IBM Z hardware cryptography implementation . 9 2.1 CP Assist for Cryptographic Functions . 10 2.2 The IBM Cryptographic Coprocessor . 10 2.3 The Trusted Key Entry workstation . 12 2.3.1 Clear key versus secure key versus protected key. 12 2.3.2 TKE and the benefits of using ICSF and protected keys . 14 Chapter 3. Auditing . 15 3.1 ICSF: Enhanced logging for PCI audit requirements . 16 3.2 ICSF and SMF .
  • Reverse Engineering X86 Processor Microcode

    Reverse Engineering X86 Processor Microcode

    Reverse Engineering x86 Processor Microcode Philipp Koppe, Benjamin Kollenda, Marc Fyrbiak, Christian Kison, Robert Gawlik, Christof Paar, and Thorsten Holz, Ruhr-University Bochum https://www.usenix.org/conference/usenixsecurity17/technical-sessions/presentation/koppe This paper is included in the Proceedings of the 26th USENIX Security Symposium August 16–18, 2017 • Vancouver, BC, Canada ISBN 978-1-931971-40-9 Open access to the Proceedings of the 26th USENIX Security Symposium is sponsored by USENIX Reverse Engineering x86 Processor Microcode Philipp Koppe, Benjamin Kollenda, Marc Fyrbiak, Christian Kison, Robert Gawlik, Christof Paar, and Thorsten Holz Ruhr-Universitat¨ Bochum Abstract hardware modifications [48]. Dedicated hardware units to counter bugs are imperfect [36, 49] and involve non- Microcode is an abstraction layer on top of the phys- negligible hardware costs [8]. The infamous Pentium fdiv ical components of a CPU and present in most general- bug [62] illustrated a clear economic need for field up- purpose CPUs today. In addition to facilitate complex and dates after deployment in order to turn off defective parts vast instruction sets, it also provides an update mechanism and patch erroneous behavior. Note that the implementa- that allows CPUs to be patched in-place without requiring tion of a modern processor involves millions of lines of any special hardware. While it is well-known that CPUs HDL code [55] and verification of functional correctness are regularly updated with this mechanism, very little is for such processors is still an unsolved problem [4, 29]. known about its inner workings given that microcode and the update mechanism are proprietary and have not been Since the 1970s, x86 processor manufacturers have throughly analyzed yet.
  • Linux Hardware Compatibility HOWTO

    Linux Hardware Compatibility HOWTO

    Linux Hardware Compatibility HOWTO Steven Pritchard Southern Illinois Linux Users Group [email protected] 3.1.5 Copyright © 2001−2002 by Steven Pritchard Copyright © 1997−1999 by Patrick Reijnen 2002−03−28 This document attempts to list most of the hardware known to be either supported or unsupported under Linux. Linux Hardware Compatibility HOWTO Table of Contents 1. Introduction.....................................................................................................................................................1 1.1. Notes on binary−only drivers...........................................................................................................1 1.2. Notes on commercial drivers............................................................................................................1 1.3. System architectures.........................................................................................................................1 1.4. Related sources of information.........................................................................................................2 1.5. Known problems with this document...............................................................................................2 1.6. New versions of this document.........................................................................................................2 1.7. Feedback and corrections..................................................................................................................3 1.8. Acknowledgments.............................................................................................................................3
  • (12) United States Patent (10) Patent No.: US 9,129,043 B2 Pandya (45) Date of Patent: Sep

    (12) United States Patent (10) Patent No.: US 9,129,043 B2 Pandya (45) Date of Patent: Sep

    USOO9129043B2 (12) United States Patent (10) Patent No.: US 9,129,043 B2 Pandya (45) Date of Patent: Sep. 8, 2015 (54) 1OOGBPS SECURITY AND SEARCH (56) References Cited ARCHITECTURE USING PROGRAMMABLE INTELLIGENT SEARCH MEMORY U.S. PATENT DOCUMENTS 5, 187,800 A 2f1993 Sutherland (76) Inventor: Ashish A. Pandya, El Dorado Hills, CA 5,640,525 A 6/1997 Yumoto et al. 5,872,972 A 2f1999 Boland et al. (US) 5,968,176 A 10, 1999 Nessett et al. 6,018,779 A 1/2000 Blumenau 6,018,799 A 1/2000 Wallace et al. (*) Notice: Subject to any disclaimer, the term of this 6,021,490 A 2/2000 Vorbach et al. patent is extended or adjusted under 35 6,130,892 A 10/2000 Short et al. U.S.C. 154(b) by 0 days. 6,147,976 A 11/2000 Shand et al. 6,205,537 B1 3/2001 Albonesi 6,237,029 B1 5, 2001 Master et al. (21) Appl. No.: 13/472,042 6,304,973 B1 10/2001 Williams 6.421,742 B1 7, 2002 Tillier (22) Filed: May 15, 2012 6.427,170 B1 7/2002 Sitaraman et al. (Continued) (65) Prior Publication Data FOREIGN PATENT DOCUMENTS US 2013/OO18835A1 Jan. 17, 2013 JP 2002-63060 2, 2002 WO WO 98.54644 12/1998 Related U.S. Application Data (Continued) OTHER PUBLICATIONS (63) Continuation of application No. 13/172.276, filed on Jun. 29, 2011, now Pat. No. 8,200,599, which is a International Search Report Issued in PCT/US2007/86785, mailed continuation of application No.
  • Computer Architectures an Overview

    Computer Architectures an Overview

    Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements.
  • Modern Processor Design: Fundamentals of Superscalar

    Modern Processor Design: Fundamentals of Superscalar

    Fundamentals of Superscalar Processors John Paul Shen Intel Corporation Mikko H. Lipasti University of Wisconsin WAVELAND PRESS, INC. Long Grove, Illinois To Our parents: Paul and Sue Shen Tarja and Simo Lipasti Our spouses: Amy C. Shen Erica Ann Lipasti Our children: Priscilla S. Shen, Rachael S. Shen, and Valentia C. Shen Emma Kristiina Lipasti and Elias Joel Lipasti For information about this book, contact: Waveland Press, Inc. 4180 IL Route 83, Suite 101 Long Grove, IL 60047-9580 (847) 634-0081 info @ waveland.com www.waveland.com Copyright © 2005 by John Paul Shen and Mikko H. Lipasti 2013 reissued by Waveland Press, Inc. 10-digit ISBN 1-4786-0783-1 13-digit ISBN 978-1-4786-0783-0 All rights reserved. No part of this book may be reproduced, stored in a retrieval system, or transmitted in any form or by any means without permission in writing from the publisher. Printed in the United States of America 7 6 5 4 3 2 1 Table of Contents PrefaceAbout the Authors x ix 1 Processor Design 1 1.1 The Evolution of Microprocessors 2 1.21.2.1 Instruction Digital Set Systems Processor Design Design 44 1.2.2 Architecture,Realization Implementation, and 5 1.2.3 Instruction Set Architecture 6 1.2.4 Dynamic-Static Interface 8 1.3 Principles of Processor Performance 10 1.3.1 Processor Performance Equation 10 1.3.2 Processor Performance Optimizations 11 1.3.3 Performance Evaluation Method 13 1.4 Instruction-Level Parallel Processing 16 1.4.1 From Scalar to Superscalar 16 1.4.2 Limits of Instruction-Level Parallelism 24 1.51.4.3 Machines Summary for Instruction-Level
  • A Hybrid Client-Server Based Technique for Navigation in Large Terrains Using Mobile Devices

    A Hybrid Client-Server Based Technique for Navigation in Large Terrains Using Mobile Devices

    A Hybrid Client-Server Based Technique for Navigation in Large Terrains Using Mobile Devices Jos´eM. Noguera, Rafael J. Segura, Carlos J. Og´ayar Grupo de Gr´aficos y Geom´atica Universidad de Ja´en Robert Joan-Arinyo Grup d’Inform`atica a l’Enginyeria Universitat Polit`ecnica de Catalunya January 29, 2010 Abstract We describe a hybrid client-server technique for remote adaptive streaming and render- ing of large terrains in resource-limited mobile devices. The technique has been designed to achieve an interactive rendering performance on a mobile device connected to a low- bandwidth wireless network. The rendering workload is split between the client and the server. The terrain area close to the viewer is rendered in real-time by the client using a hierarchical multiresolution scheme. The terrain located far from the viewer is portrayed as view-dependent impostors, rendered by the server on demand and, then sent to the client. The hybrid technique provides tools to dynamically balance the rendering work- load according to the resources available at the client side and to the saturation of the network and server. A prototype has been built and an exhaustive set of experiments covering several platforms, wireless networks and a wide range of viewer velocities has been conducted. Results show that the approach is feasible, effective and robust. Keywords: Terrain navigation, Terrain rendering, Mobile computing, 3D graphics, Soft- ware Portability, Adaptive streaming. 1 Introduction Nowadays, mobile devices with computational capabilities like mobile phones and Personal Digital Assistants (PDA) are ubiquitous. Following the general framework depicted in Fig- ure 1, they are used as interactive guides to real environments, offer features such as Global Positioning Systems (GPS), access to location-based data and, visualization of maps and, terrain rendering.