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Intel 80960RM I/O Processor Intel® 80960RM I/O Processor ■ Complies with PCI Local Bus Specification, Revision 2.2 ■ Universal (5 V and 3.3 V) PCI Signalling Environment (C-stepping only) Data Sheet Product Features ■ High Performance Intel® 80960JT Core ■ Two Address Translation Units —Sustained One Instruction/Clock Execution —Connects Internal Bus to 32-bit PCI Buses —16 Kbyte, Two-Way Set-Associative —Inbound/Outbound Address Translation Instruction Cache Support —4 Kbyte, Direct-Mapped Data Cache —Direct Outbound Addressing Support —Sixteen 32-Bit Global Registers ■ DMA Controller —Sixteen 32-Bit Local Registers —Three Independent Channels —1 Kbyte, Internal Data RAM —PCI Memory Controller Interface —Local Register Cache —64-Bit Internal and PCI Bus Addressing (Eight Available Stack Frames) —Independent Interface to 32-bit Primary —Two 32-Bit On-Chip Timer Units and Secondary PCI Buses ■ PCI-to-PCI Bridge Unit —132 Mbyte/sec Burst Transfers to PCI and —Eight Delayed Read/Write Buffers Local Buses HoldinguptoeightTransactions —Direct Addressing to/from PCI Buses —Primary and Secondary 32-bit PCI —Unaligned Transfers Supported in Interfaces Hardware —TwoPostingBuffersHoldingupto12 — Two Channels Dedicated to Primary PCI Bus Transactions — One Channel Dedicated to Secondary PCI Bus —Delayed and Posted Transaction Support ■ I2C Bus Interface Unit —Forwards Memory, I/O, Configuration —SerialBus Commands from PCI Bus to PCI Bus —Master/Slave Capabilities ■ I O Messaging Unit 2 —System Management Functions —Four Message Registers ■ Secondary PCI Arbitration Unit — Two Doorbell Registers —Supports Six Secondary PCI Devices —Four Circular Queues —Multi-priority Arbitration Algorithm —1004 Index Registers ■ Private PCI Device Support ■ Memory Controller ■ Perimeter Land Grid Array Package —128 Mbytes of 64-Bit SDRAM or —540-pin 64 Mbytes of 32-Bit SDRAM ■ Application Accelerator —ECC Single-Bit error correction, —Built-in hardware XOR engine Double-Bit error detection ■ Performance Monitoring —Two Independent Banks for SRAM / ROM/Flash(8Mbytes/Bank;8-Bit) —Ninety-eight events monitored on-chip Order Number: 273156-008 June, 2002 Intel® 80960RM I/O Processor Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Intel products are not intended for use in medical, life saving, or life sustaining applications. Intel may make changes to specifications and product descriptions at any time, without notice. Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. The Intel® 80960RM I/O Processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. Copyright © Intel Corporation, 2002 Intel, Intel Solutions960 and Intel i960 are registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Data Sheet Intel® 80960RM I/O Processor Contents 1.0 About this Document................................................................................................7 1.1 Intel® Solutions960® Program...............................................................................7 1.2 Terminology...........................................................................................................7 1.3 Additional Information Sources .............................................................................7 2.0 Functional Overview .................................................................................................8 2.1 Key Functional Units .............................................................................................9 2.1.1 PCI-to-PCI Bridge Unit .............................................................................9 2.1.2 Private PCI Device Support......................................................................9 2.1.3 DMA Controller.........................................................................................9 2.1.4 Address Translation Unit ..........................................................................9 2.1.5 Messaging Unit.........................................................................................9 2.1.6 Memory Controller Unit ..........................................................................10 2.1.7 I2C Bus Interface Unit ............................................................................10 2.1.8 Secondary PCI Arbitration Unit ..............................................................10 2.1.9 Application Accelerator Unit ...................................................................10 2.1.10 Performance Monitor Unit ......................................................................10 2.1.11 Bus Interface Unit...................................................................................10 2.2 Intel® i960® Core Features (Intel® 80960JT).......................................................11 2.2.1 Burst Bus................................................................................................12 2.2.2 Timer Unit...............................................................................................12 2.2.3 Priority Interrupt Controller .....................................................................12 2.2.4 Faults and Debugging ............................................................................12 2.2.5 On-Chip Cache and Data RAM ..............................................................12 2.2.6 Local Register Cache .............................................................................13 2.2.7 Test Features .........................................................................................13 2.2.8 Memory-Mapped Control Registers .......................................................13 2.2.9 Instructions, Data Types and Memory Addressing Modes.....................13 3.0 Package Information...............................................................................................15 3.1 Package Introduction...........................................................................................15 3.1.1 Functional Signal Definitions ..................................................................15 3.1.1.1 Signal Pin Descriptions .............................................................16 3.1.2 540-Lead H-PBGA Package ..................................................................25 3.2 Package Thermal Specifications .........................................................................37 3.2.1 Thermal Specifications ...........................................................................37 3.2.1.1 Ambient Temperature................................................................37 3.2.1.2 Case Temperature ....................................................................37 3.2.1.3 Thermal Resistance ..................................................................38 3.2.2 Thermal Analysis....................................................................................38 3.3 Heat Sink Information..........................................................................................39 3.4 Vendor Information..............................................................................................39 3.4.1 Socket-Header Vendor...........................................................................39 3.4.2 Burn-in Socket Vendor ...........................................................................39 3.4.3 Shipping Tray Vendor.............................................................................40 3.4.4 Logic Analyzer Interposer Vendor ..........................................................40 3.4.5 JTAG Emulator Vendor ..........................................................................40 3.5 ............................................................................................................................40 Data Sheet 3 Intel® 80960RM I/O Processor 4.0 Electrical Specifications........................................................................................41 4.1 Absolute Maximum Ratings ................................................................................41 4.2 VCC5REF Pin Requirements (VDIFF).....................................................................42 4.3 VCCPLL Pin Requirements ...................................................................................42 4.4 Targeted DC Specifications ................................................................................43
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