DOCSLIB.ORG

Database Integration

Total Page：16

File Type：pdf, Size：1020Kb

Download full-text PDF Read full-text
Database Integration I DATABASE INTEGRATION ALPHA SERVERS & WORKSTATIONS Digital ALPHA 21164 CPU Technical Journal Editorial The Digital TechnicalJournal is a refereed Cyrix is a trademark of Cyrix Corporation. Jane C. Blake, Managing Editor journal published quarterly by Digital dBASE is a trademark and Paradox is Helen L. Patterson, Editor Equipment Corporation, 30 Porter Road a registered trademark of Borland Kathleen M. Stetson, Editor LJ02/D10, Littleton, Massachusetts 01460. International, Inc. Subscriptionsto the Journal are $40.00 Circulation (non-U.S. $60) for four issues and $75.00 EDA/SQL is a trademark of Information Catherine M. Phillips, Administrator (non-U.S. $115) for eight issues and must Builders, Inc. Dorothea B. Cassady, Secretary be prepaid in U.S. funds. University and Encina is a registered trademark of Transarc college professors and Ph.D. students in Corporation. Production the electrical engineering and computer Excel and Microsoft are registered pde- Terri Autieri, Production Editor science fields receive complimentary sub- marks and Windows and Windows NT are Anne S. Katzeff, Typographer scriptions upon request. Orders, inquiries, trademarks of Microsoft Corporation. Joanne Murphy, Typographer and address changes should be sent to the Peter R Woodbury, Illustrator Digital TechnicalJournal at the published- Hewlett-Packard and HP-UX are registered by address. Inquiries can also be sent elec- trademarks of Hewlett-Packard Company. Advisory Board tronically to [email protected]. Single copies INGRES is a registered trademark of Ingres Samuel H. Fuller, Chairman and back issues are available for $16.00 each Corporation. Richard W. Beane by calling DECdirect at 1-800-DIGITAL Donald Z. Harbert (1-800-344-4825). Recent back issues of the INFORMIX is a registered trademark of William R Hawe Journal are also available on the Internet at Informix Software, Inc. Richard J. Hollingworth http://www.digital.com/info/D~/home. Inte1486, Intel, and Pentium are trademarks Richard F. Lary hunl. Complete Digital Internet listings can of Intel Corporation. be obtained by sending an electronic mail Alan G. Nemeth Kerberos is a trademark of Massachusetts message to [email protected]. Jean A. Proulx Institute of Technology. Robert M. Supnik Digital employees may order subscriptions MIPS R4000 is a trademark of MIPS Gayn B. Winters through Readers Choice by entering VTX Computer Systems, Inc. PROFILE at the system prompt. Motif, OSF, and OSF/1 are registered trade- Comments on the content of any paper marks of the Open Software Foundation, are welcomed and may be sent to the Inc. managing editor at the published-by or network address. Novell is a registered trademark of Novell, Inc. Copyright O 1995 Digital Equipment Corporation. Copying without fee is per- ORACLE is a registered trademark of Oracle mitted provided that such copies are made Corporation. for use in educational institutions by faculty POSIX is a registered trademark of the members and are not distributed for com- Institute of Electrical and Electronics mercial advantage. Abstracting with credit Engineers, Inc. of Digital Equipment Corporation's author- ship is permitted. All rights reserved. SCO is a registered trademark of The Santa Cruz Operation, Inc. The information in the Journal is subject to change without notice and should not SequeLink is a registered trademark of be construed as a commitment by Digital TechGnosis, Inc. Equipment Corporation or by the compa- Solaris and Sun are registered trade- nies herein represented. Digital Equipment marks and SunOS is a trademark of Sun Corporation assumes no responsibility for Microsystems, Inc. any errors that may appear in the Journal. SPARC is a registered trademark of SPARC ISSN 0898-90113 International, Inc. Documentation Number EY-T135E-TJ SPEC, SPEC@, SPECint, SPECfp92, Book production was done by Quantic SPECint92, SPECmark, SPECrate-@92, Communications, Inc. and SPECrate-int92 are trademarks of the Standard Performance Evaluation Council. The following are trademarks of Digital Equipment Corporation: ACMS, SPICE is a trademark of the University of ACMS Desktop, ACMSxp, Alphasewer, California at Berkeley. Alphastation, DEC, DEC OSF/l, DECchip, SPX/IPX is a trademark of Novell, Inc. DECnet, DECdtm, DECnet, Digital, the SYBASE is a registered trademark of Sybase, DIGITAL logo, ObjectBroker, OpenVMS, Inc. PATHWORKS, ULTRIX, VAX, and VMS. Tuxedo is a registered trademark of Unix ADABAS is a registered trademark of Systems Laboratories, Inc. Software AG of North America, Inc. UNIX is a registered trademark in the Cover Design AIX, IBM, OS/2, and RISC System/6000 United States and other counmes, licensed Key to the remarkable performance of the are registered trademarks and AS/400, CICS, exclusively through X/Open Company Ltd. Alphaserver 8400/8200 systems is Digital's and DB2 are trademarks of International new 300-MHz, &-bit Alpha 21 164 micro- Business Machines Corporation. X/Open is a trademark of X/Open Company Ltd. processor. Both subjects are featured in this AppleTalk and Macintosh are registered tenth anniversary issue of the Journal and trademarks of Apple Computer, Inc. are represented on the cover in the forms AT&T is a registered trademark of American of a photograph of the microprocessor and Telephone and Telegraph Company. an illustration of the Alphaserver system topology. BT is a registered trademark of British The cover was designed by Mario Telecommunications plc. Furtado of Furtado Communication Challenge is a trademark of Silicon Design. Graphics, Inc. Contents Foreword Richard L. Sires DATABASE INTEGRATION DB Integrator: Open Middleware for Data Access Ilichard Plcdcrcder, Vishu lirishnamitrthy, 1Michacl G.~gnon, and Mayank Vadodaria ACMSxp Open Distributed Transaction Processing Robert K. B;lati, J. Ian Carrtc, Wtlliam B. I)r~~ry, 'inti Oren L. Wicslcr An Open, Distributable, Three-tier, Client-Server Norman G,l)cplcdge, William A. Turner, c~nti Architecture with Transaction Semantics Alesandm Woog ALPHA SERVERS & WORKSTATIONS The AlphaServer 8000 Series: High-end Server lhvid M. Fcn\vick, Denis J. t'ole); Willian~I<. G~st, Platform Development Stcplien R. V;i~ilnDoren,and 1)anicl Wisscll Digital's High-performance CMOS ASIC ]can H. Basm~ji,IGy R. Fisher, Frank W. Gatulis, Herbert R. Kolk, and Jamcs F. Rosenct-a~is The Second-generation Processor Module for Nitin D. Godi\\,aln and Barry A. maska as AlphaServer 2100 Systems The Design and Verification of the Alphastation John H. Zurawski, John E. Murray, and Pat11J. Lrmrnon 600 5-series Workstation ALPHA 21 164 CPU Circuit Implementation of a 300-MHz 64-bit William J. Bo\vllill, Shane L. ]',ell, Rradley J. Bcnschncidcr, 100 Second-generation CMOS Alpha CPU Andrew J. Black, Sharon M. Britrotl, Rubcn W. (:astclino, L>alc R. Donch~n,John H. Edmondson, Harry I<. F.l~r,Ill, Paul E. Grono\\,ski, hi1I<. Jain, Ptltricin L. IO-ocscn, Marc E:.. Lanicrc, 13rucc J. L.oughlin, Shskhar Mehra, l<obcrt 0. Mucllcr, I<onald P. Preston, Sribalan Santhanam, Ti~norli!.A. Shedti, Michael J. S~nitll,.lnd Stcphcn C:. Thie~.,iut' Internal Organization of the Alpha 21 164, John H.Edmondson, Paul I,liubinfeld, Pctcr J. Ikmnon, 119 a 300-MHz 64-bit Quad-issue CMOS RlSC Rradley J. Benschncider, Dchra Bernsrcin, Ruhcn W. Microprocessor C~lstelino,Elizabeth M. Coopcr, Diiniel E. L)c\*cr, Dale H. I)onchin, Timotliy C. Fjsclicr, Anil K. Jnin, Slickh.ir Mchr.1, Jc~nneE. lMcycr, Ronald P. Preston, Vidya IC~jagopalan, Chandrasckhara Sornanathan, Scott A. Taylor, and Gilbcrt M. Wolrich Functional Verification of a Multiple-issue, I\/licll.acII(a~ltro\\lit~ and Lisa M. Noack Pipelined, Superscalar Alpha Processor - the Alpha 21 164 CPU Chip l)igi~.~lTechnical Jottrn.~l \id. 7 No. 1 1995 In Memoriam This tenth 'in~livcrs,~ryissue of tlic I)i,:,i/nl 7i~ch11ic~11,Jri1~1-11~11is dedicated to the memory of l'ctcr E'. Conklin, (:orporatc <:onsulti~igEngineer, who passed ,1\\,ay in April 1995. Pctcr\iro~.ltcdat Di~it'ilh)r 26 ye.1rs. Hc \rr.is one of the pio- nccrs of the DE(:s!,stcm-10 sofi\\,.~rcgro~~p, contrilx~ting its first b~tchand 1.i~- t~r~ilmcmol-!, subs\,stcms. Hc \\,,15 a key contl-ibutor ill the clcsign of the VAS ;~rcliitccturc,ind ~tslanguage .ind run-time cn\.i~-onments.Hc \\rorlted in the Pl)l'-11 and 'Terminals and Pl.i~ltcrsgroups, helping to dc\/clop tlicir tec1inic:il and b~~sinessstl-atcgics in rapidly cli,inging cn\iro~imcnts.Anci lie \\,as a PI-inic mo\.cr of the Alpli,~program, o\,c~-seejngf rst tl~csofk\\~arc dc\.clopment and tlicli all ofthc c~~gi~iccrinp,as \\>ell ,IS cre,itilig its ~~nicl~lcc~~lt~~r.il and man,iscl.i,il app~-oachto cro>>-org,lni/,dtio~i,~ldc\rclopmcnt. lkyond his oi~tstnndingtcclinical and bi~sincsscontributions, Pctcr espouscd dnd represented ,111 tli,it \\.as podill Digital's cult~~rc-respect ~OI-and focils oli pu'plc; doing tlic rigl~tthing for customers and collcag~lcs;dri\~i~ig for concrete results .ind \\~ork,lblcproccsscs. Hc clianipioncci tlic role of \\,omen and minor- tic3 ,is Inanagcrs and contrib~~tors.Hc helped set LIPtlic i~itcrnalNotes systcm to ful-tlicr ope11 co~ii~ii~lnic~~tionsamong e~nployccs,and bcn\~ccncriiployccs and m,inagclnent. And lie ad\~oc,~tcd,lnd modclcd tlic uses of training and de\lclop- mcnt to impro\.c pc1.5onal and ors.~~iizatio~idpcrforma~icc at '111 Ic\,cls. l'ctcr's \\rork is \\.o\.cn tlirougli the f'ibric of lligital's Iiistol-\, liltc a bright, ~~nbrc,iltrlblethl-cad. Hc \\,ill bc sorely liiisscd. Editor's Introduction The Di'qilal 7i.chr~icnI~/o~~r~~zwlmarks addition to discussions of three Alpha server architecture niade up of three its tenth anni\lcrsary \vith thc publica- hardware designs and the new micro- ticrs: desktop, middleware (founded tion of this issue. Since 1985, tlie processor, this issue presents papers on the ACMSsp monitor and Digital's ./ol,~n.ralhas chronicled Digital's engi- on database sohvare technologies.
Load more

Recommended publications
  • The Design and Verification of the Alphastation 600 5-Series Workstation by John H
    The Design and Verification of the AlphaStation 600 5-series Workstation by John H. Zurawski, John E. Murray, and Paul J. Lemmon ABSTRACT The AlphaStation 600 5-series workstation is a high-performance, uniprocessor design based on the Alpha 21164 microprocessor and on the PCI bus. Six CMOS ASICs provide high-bandwidth, low-latency interconnects between the CPU, the main memory, and the I/O subsystem. The verification effort used directed, pseudorandom testing on a VERILOG software model. A hardware-based verification technique provided a test throughput that resulted in a significant improvement over software tests. This technique currently involves the use of graphics cards to emulate generic DMA devices. A PCI hardware demon is under development to further enhance the capability of the hardware-based verification. INTRODUCTION The high-performance AlphaStation 600 5-series workstation is based on the fastest Alpha microprocessor to date -- the Alpha 21164.[1] The I/O subsystem uses the 64-bit version of the Peripheral Component Interconnect (PCI) and the Extended Industry Standard Architecture (EISA) bus. The AlphaStation 600 supports three operating systems: Digital UNIX (formerly DEC OSF/1), OpenVMS, and Microsoft's Windows NT. This workstation series uses the DECchip 21171 chip set designed and built by Digital. These chips provide high-bandwidth, low-latency interconnects between the CPU, the main memory, and the PCI bus. This paper describes the architecture and features of the AlphaStation 600 5-series workstation and the DECchip 21171 chip set. The system overview is first presented, followed by a detailed discussion of the chip set. The paper then describes the cache and memory designs, detailing how the memory design evolved from the workstation's requirements.
    [Show full text]
  • Computer Organization EECC 550 • Introduction: Modern Computer Design Levels, Components, Technology Trends, Register Transfer Week 1 Notation (RTN)
    Computer Organization EECC 550 • Introduction: Modern Computer Design Levels, Components, Technology Trends, Register Transfer Week 1 Notation (RTN). [Chapters 1, 2] • Instruction Set Architecture (ISA) Characteristics and Classifications: CISC Vs. RISC. [Chapter 2] Week 2 • MIPS: An Example RISC ISA. Syntax, Instruction Formats, Addressing Modes, Encoding & Examples. [Chapter 2] • Central Processor Unit (CPU) & Computer System Performance Measures. [Chapter 4] Week 3 • CPU Organization: Datapath & Control Unit Design. [Chapter 5] Week 4 – MIPS Single Cycle Datapath & Control Unit Design. – MIPS Multicycle Datapath and Finite State Machine Control Unit Design. Week 5 • Microprogrammed Control Unit Design. [Chapter 5] – Microprogramming Project Week 6 • Midterm Review and Midterm Exam Week 7 • CPU Pipelining. [Chapter 6] • The Memory Hierarchy: Cache Design & Performance. [Chapter 7] Week 8 • The Memory Hierarchy: Main & Virtual Memory. [Chapter 7] Week 9 • Input/Output Organization & System Performance Evaluation. [Chapter 8] Week 10 • Computer Arithmetic & ALU Design. [Chapter 3] If time permits. Week 11 • Final Exam. EECC550 - Shaaban #1 Lec # 1 Winter 2005 11-29-2005 Computing System History/Trends + Instruction Set Architecture (ISA) Fundamentals • Computing Element Choices: – Computing Element Programmability – Spatial vs. Temporal Computing – Main Processor Types/Applications • General Purpose Processor Generations • The Von Neumann Computer Model • CPU Organization (Design) • Recent Trends in Computer Design/performance • Hierarchy
    [Show full text]
  • Computer Architectures an Overview
    Computer Architectures An Overview PDF generated using the open source mwlib toolkit. See http://code.pediapress.com/ for more information. PDF generated at: Sat, 25 Feb 2012 22:35:32 UTC Contents Articles Microarchitecture 1 x86 7 PowerPC 23 IBM POWER 33 MIPS architecture 39 SPARC 57 ARM architecture 65 DEC Alpha 80 AlphaStation 92 AlphaServer 95 Very long instruction word 103 Instruction-level parallelism 107 Explicitly parallel instruction computing 108 References Article Sources and Contributors 111 Image Sources, Licenses and Contributors 113 Article Licenses License 114 Microarchitecture 1 Microarchitecture In computer engineering, microarchitecture (sometimes abbreviated to µarch or uarch), also called computer organization, is the way a given instruction set architecture (ISA) is implemented on a processor. A given ISA may be implemented with different microarchitectures.[1] Implementations might vary due to different goals of a given design or due to shifts in technology.[2] Computer architecture is the combination of microarchitecture and instruction set design. Relation to instruction set architecture The ISA is roughly the same as the programming model of a processor as seen by an assembly language programmer or compiler writer. The ISA includes the execution model, processor registers, address and data formats among other things. The Intel Core microarchitecture microarchitecture includes the constituent parts of the processor and how these interconnect and interoperate to implement the ISA. The microarchitecture of a machine is usually represented as (more or less detailed) diagrams that describe the interconnections of the various microarchitectural elements of the machine, which may be everything from single gates and registers, to complete arithmetic logic units (ALU)s and even larger elements.
    [Show full text]
  • VAX VMS at 20
    1977–1997... and beyond Nothing Stops It! Of all the winning attributes of the OpenVMS operating system, perhaps its key success factor is its evolutionary spirit. Some would say OpenVMS was revolutionary. But I would prefer to call it evolutionary because its transition has been peaceful and constructive. Over a 20-year period, OpenVMS has experienced evolution in five arenas. First, it evolved from a system running on some 20 printed circuit boards to a single chip. Second, it evolved from being proprietary to open. Third, it evolved from running on CISC-based VAX to RISC-based Alpha systems. Fourth, VMS evolved from being primarily a technical oper- ating system, to a commercial operat- ing system, to a high availability mission-critical commercial operating system. And fifth, VMS evolved from time-sharing to a workstation environment, to a client/server computing style environment. The hardware has experienced a similar evolution. Just as the 16-bit PDP systems laid the groundwork for the VAX platform, VAX laid the groundwork for Alpha—the industry’s leading 64-bit systems. While the platforms have grown and changed, the success continues. Today, OpenVMS is the most flexible and adaptable operating system on the planet. What start- ed out as the concept of ‘Starlet’ in 1975 is moving into ‘Galaxy’ for the 21st century. And like the universe, there is no end in sight. —Jesse Lipcon Vice President of UNIX and OpenVMS Systems Business Unit TABLE OF CONTENTS CHAPTER I Changing the Face of Computing 4 CHAPTER II Setting the Stage 6 CHAPTER
    [Show full text]
  • The Alphaserver 4100 Cached Processor Module Maurice B
    I' UI* Qi .H I1 0 &, hi 1, 7 : I . - * -1 ALPHASERVER 4100 SYSTEM -. ORACLE AND SYBASE DATABASE PRODUCTS - - 1 FORVLM .& Digital . &&' *-I INSTRUCTION EXECUTION ON ALPHA PROCESSORS 663***01 c: c: "' ~echn ica l 3 Journal i ri. i . - ,.i;' F ,. ! , 14 )-? ".,' & I-, 1 *,< .- , ',,I"',., , '*a, ,...,- csa y -p~ iic Editorial The Digital TechnicalJournalis a refereed The following are trademarks of Digital Jane C. Blake, Managing Editor journal published quarterly by Digital Equipment Corporation: AlphaServer, Kathleen M. Stetson, Editor Equipment Corporation, 50 Nagog Park, Alphastation, DEC, DECnet, DIGITAL, Helen L. Patterson, Editor AK02-3/B3, Acton, MA 01720-9843. the DIGITAL logo, VAX, VMS, and Hard-copy subscriptions can be ordered by ULTRIX. Circulation sending a check in U.S. hds(made payable AIM is a trademark ofAIM Technology, Inc. Catherine M. Phillips, Administrator to Digital Equipment Corporation) to the CCT is a registered trademark of Cooper Dorothea B. Cassady, Secretary published-by address. General subscription and Chyan Technologies, Inc. CHALLENGE rates are $40.00 (non-U.S. $60) for four and Silicon Graphics are registered trademarks Production issues and $75.00 (non-U.S. $115) for and POWER CHALLENGE is a trademark Christa W. Jessico, Production Editor eight issues. University and college profes- of Silicon Graphics, Inc. Compaq is a regis- Anne S. Katzeff, Typographer sors and Ph.D. students in the electrical tered trademark and ProLiant is a trademark Peter R. Woodbury, Illustrator engineering and computer science fields of Compaq Computer Corporation. HP is receive complimentary subscriptions upon a registered trademark of Hewlett-Packard Advisory Board request.
    [Show full text]
  • Data Caches for Superscalar Processors*
    Data Caches for Superscalar Processors* Toni Juan Juan J. Navarro Olivier Temam antoniojQx.upc.es juanjoQac.upc.es [email protected] Dept. Arquitectura de Computadors - Barcelona PRiSM [Jniversitat Politecnica de Catalunya Versailles University Spain FlWlCe Abstract are more difficult to design because load/store requests sent in parallel share no obvious locality properties. The diffi- As the number of instructions executed in parallel increases, culty is to propose a design that can cope with increasing superscalar processors will require higher bandwidth from degree of instruction parallelism. The solutions presently data caches. Because of the high cost of true multi-ported implemented in processors can be classified as: caches, alternative cache designs must be evaluated. The l True multi-porting. With respect to performance true purpose of this study is to examine the data cache band- multi-porting is clearly an ideal solution, but its chip area width requirements of high-degree superscalar processors, cost is high. Cost can be partly reduced by accepting a and investigate alternative solutions. The designs studied certain degradation of cache access time that would reduce range from classic solutions like multi-banked caches to more the performance. complex solutions recently proposed in the literature. The . Multiple Cache Copies. For n accesses, the cache must performance tradeoffs of these different cache designs are be replicated n times with no benefit to storage space. More- examined in details. Then, using a chip area cost model, over, store requests are sent simultaneously to all cache all solutions are compared with respect to both cost and copies for coherence and thus no other cache request can performance.
    [Show full text]
  • Zarka Cvetanovic and R.E. Kessler Compaq Computer Corporation
    PERFORMANCE ANALYSIS OF THE ALPHA 21264-BASED COMPAQ ES40 SYSTEM Zarka Cvetanovic and R.E. Kessler Compaq Computer Corporation Abstract SPEC95 1-CPU 90 This paper evaluates performance characteristics of the Compaq ES40/21264 667MHz Compaq ES40 shared memory multiprocessor. The ES40 80 HP PA-8500 440MHz system contains up to four Alpha 21264 CPU’s together IBM Power3 375MHz with a high-performance memory system. We qualitatively 70 SUN USPARC-II 450MHz describe architectural features included in the 21264 Intel Pentium-III 800MHz microprocessor and the surrounding system chipset. We 60 further quantitatively show the performance effects of these features using benchmark results and profiling data 50 collected from industry-standard commercial and technical workloads. The profile data includes basic performance 40 information – such as instructions per cycle, branch mispredicts, and cache misses – as well as other data that 30 specifically characterizes the 21264. Wherever possible, we compare and contrast the ES40 to the AlphaServer 4100 – a 20 previous-generation Alpha system containing four Alpha 21164 microprocessors – to highlight the architectural 10 advances in the ES40. We find that the Compaq ES40 often provides 2 to 3 times the performance of the AlphaServer 0 4100 at similar clock frequencies. We also find that the SPECint95 SPECfp95 ES40 memory system has about five times the memory bandwidth of the 4100. These performance improvements Figure 1 - SPEC95 Comparison come from numerous microprocessor and platform enhancements, including out-of-order execution, branch SPECfp_rate95 prediction, functional units, and the memory system. 3000 Compaq ES40/21264 667MHz 1. INTRODUCTION HP PA-8500 440MHz 2500 SUN USparc-II 400MHz The Compaq ES40 is a shared memory multiprocessor Intel Pentium-III 800MHz containing up to four third-generation Alpha 21264 2000 microprocessors [1][2].
    [Show full text]
  • Thesis May Never Have Been Completed
    UvA-DARE (Digital Academic Repository) Digital Equipment Corporation (DEC): A case study of indecision, innovation and company failure Goodwin, D.T. Publication date 2016 Document Version Final published version Link to publication Citation for published version (APA): Goodwin, D. T. (2016). Digital Equipment Corporation (DEC): A case study of indecision, innovation and company failure. General rights It is not permitted to download or to forward/distribute the text or part of it without the consent of the author(s) and/or copyright holder(s), other than for strictly personal, individual use, unless the work is under an open content license (like Creative Commons). Disclaimer/Complaints regulations If you believe that digital publication of certain material infringes any of your rights or (privacy) interests, please let the Library know, stating your reasons. In case of a legitimate complaint, the Library will make the material inaccessible and/or remove it from the website. Please Ask the Library: https://uba.uva.nl/en/contact, or a letter to: Library of the University of Amsterdam, Secretariat, Singel 425, 1012 WP Amsterdam, The Netherlands. You will be contacted as soon as possible. UvA-DARE is a service provided by the library of the University of Amsterdam (https://dare.uva.nl) Download date:26 Sep 2021 Digital Equipment Corporation (DEC) (DEC) Corporation Digital Equipment David Thomas David Goodwin Digital Equipment Corporation (DEC): A Case Study of Indecision, Innovation and Company Failure David Thomas Goodwin Digital Equipment Corporation (DEC): A Case Study of Indecision, Innovation and Company Failure David Thomas Goodwin 1 Digital Equipment Corporation (DEC): A Case Study of Indecision, Innovation and Company Failure ACADEMISCH PROEFSCHRIFT ter verkrijging van de graad van doctor aan de Universiteit van Amsterdam op gezag van de Rector Magnificus prof.
    [Show full text]
  • MICROPROCESSOR EVALUATIONS for SAFETY-CRITICAL, REAL-TIME February 2009 APPLICATIONS: AUTHORITY for EXPENDITURE NO
    DOT/FAA/AR-08/55 Microprocessor Evaluations for Air Traffic Organization Operations Planning Safety-Critical, Real-Time Office of Aviation Research and Development Applications: Authority for Washington, DC 20591 Expenditure No. 43 Phase 3 Report February 2009 Final Report This document is available to the U.S. public through the National Technical Information Services (NTIS), Springfield, Virginia 22161. U.S. Department of Transportation Federal Aviation Administration NOTICE This document is disseminated under the sponsorship of the U.S. Department of Transportation in the interest of information exchange. The United States Government assumes no liability for the contents or use thereof. The United States Government does not endorse products or manufacturers. Trade or manufacturer's names appear herein solely because they are considered essential to the objective of this report. This document does not constitute FAA certification policy. Consult your local FAA aircraft certification office as to its use. This report is available at the Federal Aviation Administration William J. Hughes Technical Center’s Full-Text Technical Reports page: actlibrary.act.faa.gov in Adobe Acrobat portable document format (PDF). Technical Report Documentation Page 1. Report No. 2. Government Accession No. 3. Recipient's Catalog No. DOT/FAA/AR-08/55 4. Title and Subtitle 5. Report Date MICROPROCESSOR EVALUATIONS FOR SAFETY-CRITICAL, REAL-TIME February 2009 APPLICATIONS: AUTHORITY FOR EXPENDITURE NO. 43 PHASE 3 REPORT 6. Performing Organization Code 7. Author(s) 8. Performing Organization Report No. TAMU-CS-AVSI-72005 Rabi N. Mahapatra, Praveen Bhojwani, Jason Lee, and Yoonjin Kim 9. Performing Organization Name and Address 10. Work Unit No.
    [Show full text]
  • The Design of the VAX 4000 Model 100 and Microvax 3100 Model 90 Desktop Systems by Jonathan C. Crowell and David W. Maruska
    The Design of the VAX 4000 Model 100 and MicroVAX 3100 Model 90 Desktop Systems By Jonathan C. Crowell and David W. Maruska 1 Abstract The MicroVAX 3100 Model 90 and VAX 4000 Model 100 systems were designed to meet the growing demand for low-cost, high-performance desktop servers and timesharing systems. Both systems are based on the NVAX CPU chip and a set of VLSI support chips, which provide outstanding CPU and I/O performance. Housed in like desktop enclosures, the two systems provide 24 times the CPU performance of the original VAX-11/780 computer. With over 2.5 gigabytes of disk storage and 128 megabytes of main memory, the complete base system fits in less than one cubic foot of space. The system design was highly leveraged from existing designs to help meet an aggressive schedule. 2 Introduction The demand for low-cost, high-performance desktop servers and timesharing systems is increasing rapidly. The MicroVAX 3100 Model 90 and VAX 4000 Model 100 systems were designed to meet this demand. Both systems are based on the NVAX CPU chip and a set of very large-scale integration (VLSI) support chips, which provide outstanding CPU and I/O performance.[1] Each member of the MicroVAX 3100 family of systems constitutes a low- cost, general-purpose, multiuser VAX system in an enclosure that fits on the desktop. This enclosure supports all the required components of a typical system, including the main memory, synchronous and asynchronous communication lines, thick-wire and ThinWire Ethernet, and up to five small computer system interface (SCSI)-based storage devices.
    [Show full text]
  • The Computer History Simulation Project
    The Computer History Simulation Project The Computer History Simulation Project The Computer History Simulation Project is a loose Internet-based collective of people interested in restoring historically significant computer hardware and software systems by simulation. The goal of the project is to create highly portable system simulators and to publish them as freeware on the Internet, with freely available copies of significant or representative software. Simulators SIMH is a highly portable, multi-system simulator. ● Download the latest sources for SIMH (V3.5-1 updated 15-Oct-2005 - see change log). ● Download a zip file containing Windows executables for all the SIMH simulators. The VAX and PDP-11 are compiled without Ethernet support. Versions with Ethernet support are available here. If you download the executables, you should download the source archive as well, as it contains the documentation and other supporting files. ● If your host system is Alpha/VMS, and you want Ethernet support, you need to download the VMS Pcap library and execlet here. SIMH implements simulators for: ● Data General Nova, Eclipse ● Digital Equipment Corporation PDP-1, PDP-4, PDP-7, PDP-8, PDP-9, PDP-10, PDP-11, PDP- 15, VAX ● GRI Corporation GRI-909 ● IBM 1401, 1620, 1130, System 3 ● Interdata (Perkin-Elmer) 16b and 32b systems ● Hewlett-Packard 2116, 2100, 21MX ● Honeywell H316/H516 ● MITS Altair 8800, with both 8080 and Z80 ● Royal-Mcbee LGP-30, LGP-21 ● Scientific Data Systems SDS 940 Also available is a collection of tools for manipulating simulator file formats and for cross- assembling code for the PDP-1, PDP-7, PDP-8, and PDP-11.
    [Show full text]
  • Digital Semiconductor Alpha 21164 Microprocessor Product Brief
    Digital Semiconductor Alpha 21164 Microprocessor Product Brief March 1995 Description The Alpha 21164 microprocessor is a high-performance implementation of Digi- tal’s Alpha architecture designed for application servers and high-performance clients. It has a superscalar design capable of issuing four instructions every clock cycle. The integration of an instruction cache, data cache, and second-level cache offers unrivaled microprocessor performance. The 21164 uses a high-performance interface to access main memory, data buses, and an optional board-level cache. Features • Fully pipelined 64-bit advanced RISC • Onchip, 96KB, 3-way, set-associative (reduced instruction set computing) write-back L2 unified instruction and architecture supports multiple operat- data cache ing systems, including: • Onchip write buffer with six fully - Microsoft Windows NT associative 32-byte entries - Digital UNIX • High-performance interface - OpenVMS - 128-bit memory data path • Best-in-class performance - Selectable error correction code - 266 through 300 MHz operation (ECC) or parity protection on data - 290 through 330 SPECint (est.) - 40-bit addressing - 440 through 500 SPECfp (est.) - Programmable interface timing - Superscalar (4-way instruction issue) - Two outstanding load instructions - Peak instruction execution rate of - Control for optional offchip L3 over 1200 million instructions per cache second - Synchronous/asynchronous RAM - 0.50 µm CMOS technology support • Pipelined (9-stage) floating-point unit - Programmable cache block size - IEEE
    [Show full text]