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Clock Distribution Lecture 25 Clock Distribution Power Distribution EE141 EE141-Spring 2006 Digital Integrated Circuits Clock Distribution Lecture 25 Clock Distribution Power Distribution 1 4 EECS141EE141 EECS141EE141 Clock Distribution Administrative Stuff Homework #9 due this Thursday Visit to Intel, April 21 Signup sheet H-tree Friday lab - project ph. 4 starts after we get back Project phase 4 Posted In lab April 21-April 27 CLK Hardware lab this week Friday section on April 28 Clock is distributed in a tree-like fashion 2 5 EECS141EE141 EECS141EE141 Class Material More realistic H-tree Last lecture Timing Today’s lecture Clock distribution Power distribution Reading Chapter 10, 9 (pp. 453-462, 469-475, 508- 515) [Restle98] 3 6 EECS141EE141 EECS141EE141 1 EE141 The Grid System GCLK Driver Driver GCLK GCLK Clock Drivers Dri ver •No rc-matching •Large power Driver GCLK 7 10 EECS141EE141 EECS141EE141 Example: DEC Alpha 21164 Clock Skew in Alpha Processor Clock Frequency: 300 MHz - 9.3 Million Transistors Total Clock Load: 3.75 nF Power in Clock Distribution network : 20 W (out of 50) Uses Two Level Clock Distribution: • Single 6-stage driver at center of chip • Secondary buffers drive left and right side clock grid in Metal3 and Metal4 Total driver size: 58 cm! 8 11 EECS141EE141 EECS141EE141 EV6 (Alpha 21264) Clocking 21164 Clocking 600 MHz – 0.35 micron CMOS tcycle= 3.3ns 2 phase single wire clock, tcycle= 1.67ns distributed globally trise = 0.35ns tskew = 150ps 2 distributed driver channels trise = 0.35ns tskew = 50ps Clock waveform Global clock waveform Reduced RC delay/skew final drivers Improved thermal distribution 2 Phase, with multiple conditional 3.75nF clock load buffered clocks 58 cm final driver width 2.8 nF clock load Local inverters for latching 40 cm final driver width Local clocks can be gated “off” to Conditional clocks in caches to save power reduce power Reduced load/skew pre-driver More complex race checking Reduced thermal issues Device variation Location of clock Multiple clocks complicate race driver on die PLL checking 9 12 EECS141EE141 EECS141EE141 2 EE141 21264 Clocking Clock Animations By Phillip Restle (IBM) http://www.research.ibm.com/people/r/restle/Animations /DAC01top.html 13 16 EECS141EE141 EECS141EE141 EV6 Clock Results ps ps 5 300 10 305 15 310 20 315 25 320 30 325 I/O Design 35 330 40 335 45 340 50 345 GCLK Skew GCLK Rise Times (at Vdd/2 Crossings) (20% to 80% Extrapolated to 0% to 100%) 14 17 EECS141EE141 EECS141EE141 EV7 Clock Hierarchy Bonding Pad Design Active Skew Management and Multiple Clock Domains Bonding Pad GND + widely dispersed NCLK (Mem Ctrl) drivers 100 + DLLs compensate μ m DLL static and low- DLL DLL frequency variation + divides design and verification effort Out PLL - DLL design and GCLK verification is added L2L_CLK L2R_CLK (L2 Cache) (CPU Core) (L2 Cache) work V SYSCLK + tailored clocks DD In GND Out 15 18 EECS141EE141 EECS141EE141 3 EE141 Pad Frame ESD Protection Layout Die Photo When a chip is connected to a board, there is unknown (potentially large) static voltage difference Equalizing potentials requires (large) charge flow through the pads Diodes sink this charge into the substrate – need guard rings to pick it up. 19 22 EECS141EE141 EECS141EE141 ESD Protection Chip Packaging VDD An alternative is ‘flip- chip’: R D1 PAD X Pads are distributed D2 around the chip The soldering balls are C placed on pads Diode The chip is ‘flipped’ onto the package Can have many more pads 20 23 EECS141EE141 EECS141EE141 Chip Packaging Bonding wire •Bond wires (~25μm) are used to connect the package to the chip Chip L Mounting Power cavity • Pads are arranged in a frame around the chip Lead L´ Distribution frame • Pads are relatively large (~100μm in 0.25μm technology), with large pitch (100μm) Pin •Many chips areas are ‘pad limited’ 21 24 EECS141EE141 EECS141EE141 4 EE141 Impact of Resistance Power Distribution We have already learned how to drive RC Low-level distribution is in Metal 1 interconnect Power has to be ‘strapped’ in higher layers of Impact of resistance is commonly seen in metal. power supply distribution: IR drop The spacing is set by IR drop, Voltage variations electromigration, inductive effects Power supply is distributed to minimize the IR Always use multiple contacts on straps drop and the change in current due to switching of gates 25 28 EECS141EE141 EECS141EE141 RI Introduced Noise Power and Ground Distribution VDD GND VDD I Logic Logic ␾pre V Ϫ⌬VЈ RЈ DD VDD VDD X I ⌬ M1 V ⌬V R GND GND (a) Finger-shaped network (b) Network with multiple supply pins 26 29 EECS141EE141 EECS141EE141 Resistance and the Power 3 Metal Layer Approach (EV4) Distribution Problem After 3rd “coarse and thick” metal layer added to the Before technology for EV4 design Power supplied from two sides of the die via 3rd metal layer 2nd metal layer used to form power grid 90% of 3rd metal layer used for power/clock routing Metal 3 Metal 2 • Requires fast and accurate peak current prediction Metal 1 • Heavily influenced by packaging technology 27 30 EECS141EE141 Source: Cadence EECS141EE141 Courtesy Compaq 5 EE141 4 Metal Layers Approach (EV5) 4th “coarse and thick” metal layer added to the Decoupling Capacitors technology for EV5 design Power supplied from four sides of the die Grid strapping done all in coarse metal Under the die 90% of 3rd and 4th metals used for power/clock routing Metal 4 Metal 3 Metal 2 Metal 1 31 34 EECS141EE141 Courtesy Compaq EECS141EE141 6 Metal Layer Approach – EV6 6 Metal Layer Approach – EV6 Next Lecture 2 reference plane metal layers added to the technology for EV6 design Solid planes dedicated to Vdd/Vss Adder design Significantly lowers resistance of grid Lowers on-chip inductance RP2/Vdd Metal 4 Metal 3 RP1/Vss Metal 2 Metal 1 32 35 EECS141EE141 Courtesy Compaq EECS141EE141 Decoupling Capacitors Board Bonding ϩ wiring wire SUPPLY Cd CHIP Ϫ Decoupling capacitor Decoupling capacitors are added: On the board (right under the supply pins) On the chip (under the supply straps, near large buffers) 33 EECS141EE141 6.
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