Understanding MOSFET Parameters: Do We Need Even More Footnotes in MOSFET Datasheets?

APEC – 2013 Professional Education Seminar

Leo Sheftelevich Vishay Siliconix® Product Applications (Siliconix divisional FAE) Acknowledgements

. I have learned a lot about MOSFETs from a number of

Vishay Siliconix® MOSFET experts and several have reviewed this material. My special gratitude goes to the following colleagues (listed alphabetically): • Dave MacDonald, Sr. Manager, MOSFET Technical Marketing • Hawk (Oh J.) Lee, Sr. Manager, MOSFET Business Development • Kandarp Pandya, Sr. Staff Applications Engineer, MOSFETs • Sanjay Havanur, Sr. Manager, MOSFET Applications Engineering

APEC-2013 2 Educational Professional Seminar Disclaimers

. MOSFET part numbers are not shown here in order to avoid any

marketing loading of the material . Datasheets of several MOSFET vendors are used for illustration purposes, not only Vishay Siliconix® MOSFET datasheets . Discussed topics mostly apply to “switchmode power MOSFETs” . Presented facts are believed to be accurate and have been reviewed by a number of MOSFET experts, but any comments and suggestions are welcome during the Q&A session or via email address found at the end of the presentation . All technical illustrations other than datasheet specs used in this material are from various Vishay application notes and other Vishay sources

APEC-2013 3 Educational Professional Seminar MOSFET datasheet interpretive “challenges”

. “Product Summary” and “Key Parameters” tables . Figure Of Merit (FOM): N-ch vs. P-ch . What is guaranteed in the datasheets . Absolute Maximum Ratings . Thermal Resistance Ratings . Static Parameters . Dynamic Parameters . HV MOSFET specific parameters . Typical Characteristics – general . Output Characteristics

APEC-2013 4 Educational Professional Seminar MOSFET datasheet interpretive “challenges” (Cont.)

. Transfer Characteristics

. RDS(on) vs. VGS plot . Safe Operating Area plot . Single Pulse Power vs. Time curves . Power de-rating curves “Power vs. Temperature” . Normalized Thermal Transient Impedance, JA plots . Normalized Thermal Transient Impedance, JC plots . Packages: some issues when crossing MOSFETs . N-ch vs. P-ch MOSFET load switch applications . Automotive MOSFET specifics . PCB layout recommendations for MOSFETs

APEC-2013 5 Educational Professional Seminar

PRODUCT SUMMARY AND FIGURE OF MERIT (FOM)

APEC-2013 6 Educational Professional Seminar Product Summary and Key Parameters

. QUESTION: Which MOSFET has a lower R ? DS(on)

APEC-2013 7 Educational Professional Seminar Product Summary and Key Parameters (cont.)

. ANSWER: MOSFET “A” has the lower R DS(on).

APEC-2013 8 Educational Professional Seminar Product Summary and Key Parameters (cont.)

. This is how it is done now: showing “Max” notations

. Most MOSFET datasheets do not guarantee RDS(on) Min. • MOSFETs are mostly specified as “switches,” with

RDS(on) Max limits

• RDS(on) current sensing is not accurate without calibration and/or temperature correlation

APEC-2013 9 Educational Professional Seminar Product Summary and Key Parameters (cont.)

. Pay attention to Qg “Test Conditions”:

. For faster MOSFET switching a lower rated - VGS MOSFET can be used:

APEC-2013 10 Educational Professional Seminar MOSFET Figure Of Merit (FOM)

. FOM is a quick way to estimate N-ch MOSFETs’ relative

performance in switch mode power supplies (SMPS)

. FOM = RDS(on) x Qg : the lower the FOM – the better the MOSFET typically performs in SMPS, but it does not always guarantee better performance, because other factors matter

. For FOM comparisons one has to use the same test (operating)

conditions and values (VDS, VGS, ID, Typ or Max), but it’s better to compare MOSFETs in the same circuit

. When comparing MOSFETs in the same circuit the driver may

need to be optimized, i.e. external RG or RBOOT resistor, or snubber values might need to be adjusted

APEC-2013 11 Educational Professional Seminar

MOSFET Figure Of Merit (cont.)

. In LV MOSFET FOMs typically the V = 4.5 V is used GS

. In HV MOSFET FOMs typically the VGS = 10 V is used . For the 30 V MOSFET discussed earlier :

• FOM (typ, 4.5 VGS) = 1.1 mΩ x 66 nC ~= 72.6 mΩ*nC

. Higher Qg MOSFET may save you an external resistor or a snubber if the driver is too strong => total solution optimization

. See Vishay AN-605 “Power MOSFET Basics: Understanding MOSFET Characteristics Associated with the Figure of Merit”

APEC-2013 12 Educational Professional Seminar N-ch vs. P-ch MOSFET specifications

. P-ch MOSFETs are rarely used in switching power

supplies for control MOSFETs or rectifier MOSFETs,

because typically for the same RDS(on) they have larger Qg; so usually FOM is not used for P-ch MOSFETs selection

. As an example, compare 1.9 mΩ max N-ch and P-ch MOSFETs in 5x6 mm PowerPAK SO-8 packages (some

other Qg variations are possible due to various MOSFET technologies used)

APEC-2013 13 Educational Professional Seminar

ABSOLUTE MAXIMUM RATINGS

APEC-2013 14 Educational Professional Seminar What is guaranteed in the datasheets

. Guaranteed by design or through production testing: • All specification limits located in Min. and Max. columns at test conditions stated in the datasheet

(e.g. TA = 25 ºC, TC = 25 ºC, etc.) • Pinout and package dimensions . NOT guaranteed: • All specification values located in Typ. columns

• “Typical Characteristics” (mostly at TJ = 25 ºC), e.g. SOA, Output Characteristics, etc.

APEC-2013 15 Educational Professional Seminar What is guaranteed in the datasheets (cont.)

. Typical values are design targets adjusted for production

distribution, while Min and Max limits cover worst case scenarios with certain margins

. Design decisions cannot be made based on typical values without additional research and testing

. Search MOSFET datasheets for the word “guaranteed”:

APEC-2013 16 Educational Professional Seminar VDS and VGS ratings

. These ratings are “DC + AC” at 25 ºC

. Temperature coefficients: VDS tempco increases VDS breakdown voltage at higher TJ, while the Vgs(th) tempco does not help to decide if the VGS max is OK over temp

QUESTION: What is the absolute maximum VGD rating? (trick question, it is not in the datasheets…)

APEC-2013 17 Educational Professional Seminar High Voltage (HV) MOSFET VDS

. For HV MOSFETs it might be harder to achieve V DS margins required by the design rules used at some design companies . Since normally the HV high-power MOSFETs run hot while

sitting on heatsinks, the VDS positive tempco can help establishing a reasonable margin for the application

APEC-2013 18 Educational Professional Seminar HV MOSFET dV/dt specifications

. There are 2 cases of dV/dt induced MOSFET turn-on (other than UIS): see Vishay appnote AN601 “UIS Rugged MOSFETs ….” . The first is the activation and subsequent secondary breakdown of the parasitic bipolar transistor

. Also, for HV MOSFETs, typically with VDS ≥ 400 V, the VDS turn-off voltage transition ranges are naturally much higher than their respective Vgs(th) voltages, and therefore, the dV/dt injected spikes are potentially larger . The dV/dt is not a typical spec for LV MOSFETs, but it is for HV MOSFETs due to the difference in the internal structures

APEC-2013 19 Educational Professional Seminar Marketing or Engineering?

QUESTION: What is a realistic maximum current of this

5x6 mm leadless 0.8 mΩ Typ. MOSFET? . No other Max current footnotes or package-limited current ratings are found in this datasheet

APEC-2013 20 Educational Professional Seminar Marketing or Engineering? (cont.)

. One more way to show useful silicon current limits, even at TC = 25 ºC: • These specs illustrate that the silicon in this DPAK MOSFET is robust

. Some MOSFET vendors place a footnote similar to the note d. above on other pages of the datasheet, as in this TO-220 MOSFET datasheet

APEC-2013 21 Educational Professional Seminar ID and PD ratings

. All absolute maximum current and power numbers are real and are

measured during MOSFET characterization…. but not all of them are practical, as shown for this 1 mΩ max, 5x6 mm MOSFET … •

QUESTION:

What is an estimated continuous PD limit?

APEC-2013 22 Educational Professional Seminar ID and PD ratings (cont.)

. P = 4 W max at T = 70 ºC for T = 10 s D A . PowerPAK SO-8 5x6 mm leadless package is tested on 1” x 1” PCB

. How is the continuous PD limit at TA = 70 ºC estimated?

ANSWER: at TA = 70 ºC the PD is estimated as 4 W / 3 ~= 1.33 W max continuous for TJ = 150 ºC… and it is ~ 6.25 W / 3 ~= 2 W at TA = 25 ºC

APEC-2013 23 Educational Professional Seminar Calculating PD

QUESTION: How is the P = 104 W limit obtained? D

. TJ - TC = PD x RthJC . PD = (TJ - TC) / RthJC = (150 – 25) / 1.2 ~= 104 W

APEC-2013 24 Educational Professional Seminar Calculating PD (cont.)

QUESTION: What is the PD Max. level at Max. rated current?

. 60A is a package-limited current

2 . PD_Max = I x RDS(on)_Max 2 . PD = 60 x 1.5 x 0.001 = 5.4 W Max

APEC-2013 25 Educational Professional Seminar Pulsed drain current IDM ratings

QUESTION: What is the I pulse width on p. 1 of this older DM datasheet?

ANSWER: See note a. on page 2 of the datasheet. Why? A factory expert told me so…

Page 2:

APEC-2013 26 Educational Professional Seminar Pulsed drain current IDM ratings (cont.)

. Today’s datasheets typically have:

• either a pulse width

• or a reference to the SOA

APEC-2013 27 Educational Professional Seminar Source-Drain diode current IS ratings

QUESTION: Why are I and I limits the same at T = 25 ºC but D S C are ~10x different at TA = 25 ºC?

ANSWER: Which scenario is more practical? (Yes, it’s the answer…)

APEC -2013 28 Educational Professional Seminar Avalanche ratings IAS and EAS

. Unclamped Inductive Switching (UIS) and Avalanche limits

. The inductor value matters, so for “apples to apples” comparisons use same inductor values or recalculate per respective appnotes • See “Power MOSFET Avalanche Design Guidelines” appnote AN-1005 at http://www.vishay.com/docs/90160/an1005.pdf

APEC-2013 29 Educational Professional Seminar Avalanche ratings IAS and EAS (cont.)

. Some datasheets contain “avalanche current vs. time”

curves, which are easier to use than avalanche energy ratings

APEC-2013 30 Educational Professional Seminar Dual MOSFET ratings

. Maximum current and power at TA (!) are given for one MOSFET while the 2nd MOSFET is OFF . Same ratings

given at TC are not very practical…

APEC-2013 31 Educational Professional Seminar Thermal Resistance Ratings

. R is a design parameter thJC . RthJA is PCB design dependent . A typical test PCB is based on 1” x 1” FR-4 material with double sided 2 oz (0.076 mm) copper on both sides: 100% copper with slit separation for drain, source, and gate . Variations of the thermal resistance specs:

APEC-2013 32 Educational Professional Seminar Thermal Resistance Ratings (cont.)

10 s is not “continuous,” 10 min IS for this MOSFET…

APEC-2013 33 Educational Professional Seminar TJ and Tsoldering ratings

. MOSFET Max Operating Junction Temperatures are:

• 150 ºC for most commercial MOSFETs • 175 ºC for some commercial MOSFETs • 175 ºC for all automotive MOSFETs . Soldering temperature is higher and it is time-limited per published solder reflow profile . “Vishay Siliconix. Reliability Information” http://www.vishay.com/docs/73257/73257.pdf

. It is better reworking boards with hot air and PCB pre-heater, rather than with soldering iron or tweezer soldering iron

APEC-2013 34 Educational Professional Seminar TJ and Tsoldering ratings (cont.)

APEC-2013 35 Educational Professional Seminar TJ and Tsoldering ratings (cont.)

. MICRO FOOT® BGA MOSFETs are more sensitive to the reflow temperature and time accuracy

APEC -2013 36 Educational Professional Seminar

STATIC PARAMETERS

APEC-2013 37 Educational Professional Seminar Static Parameters: VDS

. Definition: “Drain-Source Breakdown Voltage without avalanche with VGS short-circuited”

. Symbols “VDS” or “BVDSS” or “V(BR)DSS”

. VDS is specified at TJ = 25 ºC

. Due to VDS tempco for a +100 ºC delta, at +125 ºC it is a 1.5V or 5% increase to 31.5 V, and for -75 ºC delta, at -50 ºC it is a -1.125 V or 3.75% decrease to 28.875 V . These variations would affect the design margin

APEC-2013 38 Educational Professional Seminar Static Parameters: IGSS and IDSS

. Max. limits are set based on the characterization testing

data with large margins (sometimes up to 10x) making it easier to perform go/no-go production testing

. IGSS does not vary with temperature too much . For batteries with very low self-discharge currents

comparable with 1 µA, using higher-VDS MOSFETs would reduce the IDSS leakage thru turned off MOSFETs

APEC-2013 39 Educational Professional Seminar Static Parameters: RDS(on)

. R is “Drain-Source On-State Resistance” DS(on) . Guaranteed only at VGS at which it is rated: can be rated at one voltage or at up to 5 voltages

. Typically, MOSFETs are rated as “switches”: typical and maximum resistances, but no minimum resistance . Maximum limits can be 20%, 50% and even 100% above respective typical values

APEC-2013 40 Educational Professional Seminar Static Parameters: RDS(on) (cont.)

. With additional up to 30-150% R increase at maximum operating DS(on) temperature the RDS(on) current sense is not a very accurate current sensing method

. For RDS(on) < 10 mΩ the PCB solder might become a substantial error contributor for the RDS(on) current sensing, esp. for smaller packages with relatively small source pad area . The PCB solder also increases conduction losses above the levels

expected from low- RDS(on) MOSFETs

APEC-2013 41 Educational Professional Seminar Static Parameters: VGS(th)

. At VGS(th) the MOSFET just starts conducting at 250 µA current level, i.e. this is a “turn-off” spec rather than a “turn-on” spec . The production testing is go/no-go (to reduce the test time):

• at VGS = 1.1 V the ID ≥ 250 µA parts are rejected: must be OFF

• at VGS = 2.2 V the ID ≤ 250 µA parts are rejected: must be ON

. MOSFETs are guaranteed to be fully ON when VGS ≥ VGS_MIN_RATED, i.e. for a MOSFET with RDS(on) rated at 10VGS and 4.5VGS, the VGS must be ≥ 4.5 V

. Knowing the VGS(th) is useful to a design engineer who uses the MOSFET, but the VGS_MIN_RATED = 4.5 V is the ”design parameter” here

QUESTION: What must VGS_MIN_RATED be for a MOSFET driven by a µcontroller powered with 3.3 V and why?

APEC-2013 42 Educational Professional Seminar

Linear operation failures

. VGS < VGS_MIN_RATED => “Linear Operating Mode” (LOM) . Known LOM failure mechanism includes hot spots and thermal runaway while operating well within advertised SOA adjusted for

an elevated TA or TC temperature

. Definitions: RDS(on) is a D-S resistance at VGS ≥ VGS_MIN_RATED, while RDS is a D-S resistance at VGS < VGS_MIN_RATED

. LOM failures are explained by the RDS tempco being negative, while in a fully-ON MOSFET the RDS(on) tempco is positive

. When fully ON at VGS ≥ VGS_MIN_RATED the MOSFET cells share the current well

. In the LOM at VGS < VGS_MIN_RATED the MOSFET cells DO NOT share the current well

APEC-2013 43 Educational Professional Seminar Linear operation failures (cont.)

. The inflection point is also a Zero Temperature Coefficient

(ZTC) point

APEC-2013 44 Educational Professional Seminar Linear operation failures (cont.)

. MOSFET linear operating mode failures are well known in the industry and are possible in both trench and planar MOSFETs . Linear Operating Mode scenarios include: • Linear voltage and current regulators using external MOSFETs • Slewrate-controlled load switches and hot-swap control circuits • Any ON/OFF switch applications with too low gate drive voltages

with VGS < VGS_MIN_RATED • Secondary-side SR MOSFETs during the driver power rail turn

on/off might be driven with VGS ≤ VGS_MIN_RATED pulses • Secondary-side synchronous rectification MOSFETs after the driver is turned off completely might have floating gates (with no

external RGS or with high-value RGS pull-downs) and can discharge Cout while being in a linear region, so can fail . Beware of curve tracers run in millisecond ranges…. . Successful designs use substantially derated currents in the LOM

APEC-2013 45 Educational Professional Seminar LOM failures in load switch MOSFETs

. Example of a slewrate-controlled load switch: slower than

several microsecond turn-on or turn-off times might require substantial current derating

APEC-2013 46 Educational Professional Seminar Floating gate failures in buck converters

. Floating gate is a design problem in itself, but if the gate

floats below VGS_MIN_RATED then it is the LOM as well

. If VDC is asserted fast while VDD is still OFF, the MOSFET gates are not controlled (driven) by the drivers, and therefore, might float due to the gate charge injected via the Miller

CGD capacitances. Use gate pull-downs.

APEC-2013 47 Educational Professional Seminar Floating gate failures in secondary side synchronous rectifier MOSFETs

. Synchronous rectifier MOSFETs can get blown if there is no a gate pull-down resistor or its value is too high (R4)

. Failure conditions: there is no driver power after turn-off, COUT is still pre-charged, there is a leakage pass from COUT to the gate of M1 due to the driver components, PCB contamination, and/or humidity . Use 5.1 k – 10 k gate pull-downs . The example shows a simplified schematic for an actual application support effort with a too high R4 value . Temperature cycling testing in an environmental chamber has lead to M1 MOSFET failures

APEC-2013 48 Educational Professional Seminar

DYNAMIC PARAMETERS

APEC-2013 49 Educational Professional Seminar Dynamic Parameters: Qxx

. Q is rated at different V levels, such as 10 V and 4.5 V g GS GS GS . Qg affects switching loses

. Qgd /Qgs ratio < 0.5 improves immunity to Cdv/dt gate coupling

. Qoss matters for some high-FSW switching power supplies

. See Vishay Siliconix AN-608 “Power MOSFET Basics: Understanding gate Charge and Using It To Assess Switching Performance”

APEC-2013 50 Educational Professional Seminar Dynamic Parameters: Ciss, Coss, Crss

. The capacitances are rated at V = 0 V and are “MOSFET design GS parameters” that vary with VDS

. Coss might be critical in some high-FSW ZVC applications

. Lower Crss-eff/Ciss ratio supports a better gate spike immunity for the spike injected via Miller capacitance, esp. in low-side MOSFET buck applications

. Crss-eff = CGD-eff is calculated based on VDS

and QGD as C = Q/V

APEC-2013 51 Educational Professional Seminar Dynamic Parameters: Co(er) and Co(tr) . Relatively new specs in HV MOSFET datasheets: help estimating power losses and resonant converter timing

APEC-2013 52 Educational Professional Seminar Dynamic Parameters: Rg, ON and OFF timing

. R is a parasitic parameter: resistance of gate runners g . Time constant Rg * Ciss affects the MOSFET turn-on & turn-off

. With Rg = 1.35 Ω typ using MOSFET drivers with 2x lower output resistance, e.g. 0.5 Ω instead of 1 Ω, would produce only fractional turn-on time improvement of ~20% typ.

APEC-2013 53 Educational Professional Seminar Dynamic Parameters: Rg, ON and OFF timing (cont.)

. R MOSFET parameter and R shown in the Test g g Conditions are different here! • See Vishay AN-957 “Measuring Power MOSFET Characteristics”

APEC-2013 54 Educational Professional Seminar Drain-Source Body Diode Characteristics

. For this 1.5 mΩ max MOSFET the 60 A and 100 A body diode

Max. specs are the same as the MOSFET’s maximum current

specs given at TC = 25 ºC and TA = 25 ºC respectively

. IS test condition and the pulse duration matter for the VSD spec

. IF test condition matters for trr and Qrr specs: the higher IF the larger the numbers

APEC-2013 55 Educational Professional Seminar

TYPICAL CHARACTERISTICS

APEC-2013 56 Educational Professional Seminar Typical Characteristics – general

. “Typical Characteristics” are typical, i.e. do not guarantee

any performance parameters, and are provided to aid the MOSFET users

. “Typical Characteristics” are provided at TJ = 25 ºC unless otherwise specified on the plots

. A lot of useful information can be derived from the typical curves and plots, particularly parameter variations vs.

temperature, vs. time, and vs. control signal VGS . Sometimes typical characteristics are not explained in the datasheets well enough to make using them easier to designers

APEC-2013 57 Educational Professional Seminar RDS(on) vs. VGS

APEC-2013 58 Educational Professional Seminar VGS(th) Variance and RDS(on) vs. Temperature plots

. QUESTION: How useful are “Output Characteristics” ID vs. VDS ?

APEC-2013 59 Educational Professional Seminar Output Characteristics

. For a 10 V rated MOSFET its operation is not guaranteed GS below 10 VGS, i.e. characterizing a MOSFET by a customer at 6 VGS might lead to hard-to-recover situation when a year after the product release a MOSFET batch would come with characteristics outside of the expected range. . Using closed-loop control is the best solution for accurate control systems assuming the currents are limited to safe levels

ANSWER: Probably, not a lot….

APEC-2013 60 Educational Professional Seminar Transfer Characteristics

. Analyzing typical transfer characteristics might help finding

MOSFETs with lower negative RDS tempco: see 3x vs. 4x RDS change (not RDS(on) !)

APEC-2013 61 Educational Professional Seminar Safe Operating Area (SOA) plots

. SOA plots are typically shown either for T = 25 ºC (“junction-to-case”) C or for TA = 25 ºC (“junction-to-ambient”), and in all cases for TJ_MAX that typically is 150 ºC or 175 ºC . Example 1: 1 mΩ MOSFET “X” in a 5x6 mm leadless thermally- enhanced package

QUESTION: Can a SOA plot be used “as is”?

APEC-2013 62 Educational Professional Seminar 62 SOA plot “Junction-to-Case”

MOSFET “X” ANSWER: Not always

. SOA plots in datasheets are based on best-case thermal scenarios and need to be adjusted

. PD = VDS x ID, so for PD = const1 the function is ID = const1 / VDS (reciprocal function + Log scale => straight line) . The DC operation 2.5 W margin (Red) is well below the “thermal stability limit” black “DC” line

APEC-2013 63 Educational Professional Seminar SOA plot “Junction-to-Ambient”

. Example 2: a 1 mΩ MOSFET “Y” in a 5 x 6 mm leadless

thermally-enhanced package

APEC-2013 64 Educational Professional Seminar SOA plot “Junction-to-Ambient” (cont.)

. The “2.5 W DC” thermal limit is shown on this SOA plot with the

maximum corresponding to “RDS(on) limited” current of 35 A . MOSFET “Y” SOA is closer to a practical application scenario than MOSFET “X” SOA for a standalone MOSFET on a PCB . Both practical SOA estimates require additional power derating for design margins

APEC-2013 65 Educational Professional Seminar Single Pulse Power, J-A

. Some MOSFET datasheets contain Single Pulse Power plots

. This is another 1 mΩ max MOSFET typical plot example . Critical: this power pulse is

estimated at VGS ≥ VGS_MIN_RATED and typically at the highest rated

VGS = 10 V, but not 4.5 V, i.e. this is not a LOM power pulse

APEC-2013 66 Educational Professional Seminar Power derating, J-C and J-A

. These plots illustrate 2 application scenarios: nearly

perfect thermal solution and practical PCB based solution . Neither of the scenarios include design margins

APEC-2013 67 Educational Professional Seminar Using Normalized Thermal Transient Impedance

. Absolute maximum “Pulsed Drain Current” IDM is specified in a couple of possible different ways in the datasheets MOSFET A

- OR -

MOSFET B

QUESTION: How to estimate a realistic maximum drain current pulse using Normalized Thermal Transient Impedance plots?

APEC-2013 68 Educational Professional Seminar Using Normalized Thermal Transient Impedance, J-C

. Estimating maximum I for a 300 µs pulse on a PCB at T = DM PCB 100 ºC for the MOSFET “A” with the following specs at VGS = 10 V:

. At TJ ≈ 150 ºC the RDS(ON)_Typ increases ~ 50%, so RDS(ON)_Max_150 = 1.5 mΩ

APEC-2013 69 Educational Professional Seminar Using Normalized Thermal Transient Impedance J-C (cont.)

. The junction temperature T = T + P • k • R , where J C D thJC “k” is a normalization coefficient of RthJC . For a single 300 µs pulse the coefficient k ≈ 0.11

APEC-2013 70 Educational Professional Seminar Using Normalized Thermal Transient Impedance, J-C (cont.)

. Maximum T rise above max expected T ≈ T temperature J C PCB • TJ –TC = PD_Max • k • RthJC

. For TJ_Max = 135 ºC (with 10% margin to 150 ºC) and TC = 100 ºC:

• PD_Max = (TJ –TC) / (k • RthJC) = (135 – 100) / (0.11 • 1.2) = 265 W 2 o PD_Max = I DM • RDS(ON)_Max_150 2 -3 • I DM = PD_Max / RDS(ON)_Max_150 = 265 / (1.5 • 10 ) = 176667

• IDM = √ 176667 = 420 A, which is much higher than 120 A at 25 ºC

MOSFET “A” can withstand estimated 420 A current pulse for 300 µs with

TC = 100 ºC and TJ = 135 ºC (with 10% margin to 150 ºC max operating temperature, i.e. a conservative estimate)

APEC-2013 71 Educational Professional Seminar Using Normalized Thermal Transient Impedance, J-C (cont.)

The QUESTION was:

. How to estimate a realistic maximum drain current pulse using Normalized Thermal Transient Impedance plots?

The ANSWER: . In some cases realistic maximum drain current levels are hard to measure due to limitations of MOSFET testers used for characterization. . It can be shown that the 120 A maximum current of

MOSFET “A” at TA = 25 ºC would increase the TJ by less than 12 ºC

APEC-2013 72 Educational Professional Seminar Using Normalized Thermal Transient Impedance, J-A

. Verifying the 120 A at T = 25 ºC rating for the MOSFET “A”: A

APEC-2013 73 Educational Professional Seminar Using Normalized Thermal Transient Impedance, J-A (cont.)

. The junction temperature T = T + P • k • R , where “k” is a J A D thJA normalization coefficient of RthJA

. For a single 300 µs pulse at TA = 25 ºC the coefficient k < 0.01 , so for a conservative first-step estimate we can use k = 0.01

. Maximum TJ rise above TA = 25 ºC is TJ –TA = PD_Max • k • RthJA

. RthJA is found here: . For 120A current and assuming (for a conservative estimate!) the

worst case RDS(ON) increase of ~ 50% to RDS(ON)_Max_150 = 1.5 mΩ 2 (as if at TJ ≈ 150 ºC): PD = 120 * 0.0015 = 21.6 W

. TJ –TA = PD_Max • k • RthJA = 21.6 * 0.01 * 54 ≈ 11.66 ºC

APEC-2013 74 Educational Professional Seminar

TYPICAL MOSFET APPLICATIONS

APEC-2013 75 Educational Professional Seminar Using N-ch and P-ch MOSFETs as load switches

. “P” stands for “positive” and “N” stands for “negative”…. in MOSFET load switch applications as well, thus defining on what side of the load what MOSFET to use . Naturally, it is relatively straight-forward using P-ch MOSFETs on the positive side of the loads and using N-ch MOSFETs on the negative side of the loads, but N-ch MOSFETs can also be used as high-side load switches: QUESTION: VGSN ≥ VDD + VGS_MIN_RATED and VGSP ≤ VDD - VGS_MIN_RATED Why?

VGSN

VGSP

APEC-2013 76 Educational Professional Seminar Using N-ch and P-ch MOSFETs as load switches (cont.)

. Using N-ch MOSFETs on the positive side of the loads is justified

when the lowest possible RDS(on) is required in the given package, an additional power rail is available, and some extra cost in the design is acceptable for a buffer N-ch MOSFET between a µController and the switch MOSFET

QUESTION: Can the 1.8V-rated NMOS here be driven directly by the 3.3V µController?

APEC-2013 77 Educational Professional Seminar Using N-ch and P-ch MOSFETs as load switches (cont.)

. The lowest-V N-ch and P-ch MOSFETs available are GS rated at 1.2 V . In some cases N-ch MOSFETs can be used as high-side load switches while being driven by µControllers directly without use of N-ch MOSFET buffers

QUESTION: Can a 2.5 V-rated NMOS be used here?

APEC-2013 78 Educational Professional Seminar

MOSFET PACKAGES

APEC-2013 79 Educational Professional Seminar ® ® PowerPAK SO8L PowerPAK 8x8L ® Conventional TOxxx Packages Single and Dual Single and Dual PowerPAK 8x8 (Auto) (Auto) (HVM) High Power Power Density Lower Rds(on) High Current Long Lead TO247AC

PowerPAIR® PowerPAIR® Vin Thermal Improvement

Multiple Die & GND PowerPAIR® Performance Enhanced SO8, 1212 6 x 3.7 3 x 3 6 x 5 Vout

Power MICRO FOOT®

•Trench and LDMOS PolarPAK® layouts under review. PowerPAK® SO-8 •Pilot samples produced ChipFET® SC70 SC75 0.8 x 0.6 1212-8

1212-8S. 20% larger die

CSP Package MICRO FOOT®

1.6x1.6x0.65mm 1x1.5x0.6mm 1x1x0.6mm 0.8x0.8x0.4mm APEC-2013 80 Educational Professional Seminar MOSFET 5 x 6 mm packages: similarities and differences

. Sometimes drop-in replacement packages do not look

exactly the same in the respective datasheets . “MOSFET A” datasheet illustrations:

. “MOSFET B” datasheet illustrations:

APEC-2013 81 Educational Professional Seminar MOSFET 5 x 6 mm packages (cont.)

. Sometimes drop-in replacement packages do not look

exactly the same on the respective package drawings . “MOSFET A” drawing:

. “MOSFET B” drawing:

APEC-2013 82 Educational Professional Seminar Smaller packages – same performance

. Smaller thermally enhanced packages with latest MOSFET

technologies enabling lower than 1 mΩ and single mΩ

RDS(on) values can deliver a performance achievable with much larger packages just several years ago

. Lower RDS(on) => smaller packages

. An estimate of the SMT package power with elevated TA and TC • 4 mΩ max and 30 A => 3.6 W => D2PAK • 1.5 mΩ max and 30 A => 1.35 W => PowerPAK SO-8 5x6

. Same RDS(on) in a thermally enhanced packages => smaller packages

APEC-2013 83 Educational Professional Seminar Smaller packages – same performance (example)

. Industry-standard leadless 3 x 3 mm thermally-enhanced package is probably available from every MOSFET company . It delivers a thermal performance comparable with SO-8, and is better than SO-8 with the HF noise level in switching power supplies . PowerPAK®1212-8 can reduce area consumed on PCB by 63%

APEC-2013 84 Educational Professional Seminar Smaller packages – same performance (example) (cont.)

. The 3 x 3 mm PPAK1212 MOSFETs run cooler than SO-8

MOSFETs in typical DC/DC buck applications for high-side and low-side MOSFETs

APEC-2013 85 Educational Professional Seminar Even smaller packages: 2 x 2 mm PowerPAK® SC-70

. Latest Trench MOSFET technologies developed by multiple

MOSFET vendors enabled 2x2 mm MOSFETs with parameters available only in 3x3 mm and 5x6 mm packages just several years ago

APEC-2013 86 Educational Professional Seminar

AUTOMOTIVE-MEDICAL- HiREL_COTS MOSFETS

APEC-2013 87 Educational Professional Seminar Automotive = Medical ~ = HiRel COTS

. In 2012: “Medical Approved Process Flow and Devices for Implantable Applications” (SQxxx automotive grade MOSFETs) http://www.vishay.com/docs/49970/49970_pl0469.pdf

. In the 1990s military and government contractors started using regular commercial parts and called them “COTS” (Commercial Off The Shelf); there were various costly failures and problems with the systems designed using these COTS parts (that are mentioned in several places on the Web)

. As of today, typically, “COTS” means “commercial parts that were tested for higher reliability, but not at the levels of mil test specs”, i.e. not just “any commercial part”

APEC-2013 88 Educational Professional Seminar Automotive ~ = HiRel COTS (cont.)

. As of today, regular commercial MOSFETs should not be called “COTS” for the purpose of being used by HiRel customers, but the automotive MOSFETs have higher reliability levels and are what could be consider COTS . In many cases automotive MOSFETs have longer production lives than commercial parts . While we do not specifically promote either commercial or automotive MOSFETs for HiRel applications, we support customers with the selection and designing in, if the customers make that decision

APEC-2013 89 Educational Professional Seminar Automotive MOSFETs

. Higher reliability in challenging applications that “push” the

MOSFETs . AEQ-101 qualified part numbers begin with SQ, not with Si, etc. – Q = “AEC Q-101 qualified” . Automotive SQ MOSFETs enhancements compared to Commercial • Silicon uses more conservative design rules and is designed for ruggedness • Packaging is also optimized using different materials to achieve more ruggedness • Specific process flow for automotive in fab and assembly • State of the art statistical tools are used including dynamic PAT • 100% stress testing is utilized for some key characteristics

APEC-2013 90 Educational Professional Seminar Automotive MOSFETs (cont.)

SQ Rugged D2PAK Package

PACKAGE DESIGN SILICON DESIGN •Thicker gauge lead frame •Known wafer process •Higher quality mold o Utilize commercial compound experience o Improved mold lock and •Conservative design rules adhesion •Design FMEA methodology •Larger diameter wire bond (Failure Mode and Effect Analysis)

MANUFACTURING TESTING QUALIFICATION •State of the art equipment •Wafer and package level •AEC Q101 and statistical controls methodology •Safe launch •Automotive specific •Conservative ratings process flow in fab and o Utilize Dynamic PAT assembly (Parts Average Testing) •100% stress screening

APEC-2013 91 Educational Professional Seminar Automotive MOSFETs (cont.)

. The 5x6 mm leadless PowerPAK® SO-8 is not automotive qualified, while the 5x6 mm leaded PowerPAK SO-8L is

. The 3x3 mm leadless PowerPAK-1212 is automotive qualified

PPAK SO-8L PPAK-1212

APEC-2013 92 Educational Professional Seminar

PCB DESIGN FOR HIGH-POWER MOSFETS

APEC-2013 93 Educational Professional Seminar MOSFET related PCB layout hints

. Use larger copper area and thermal vias for higher power

dissipation . Known thermal via drill diameter range is 0.2 mm to 0.33 mm: max diameter is limited to minimize solder wicking . Various app notes are available from various vendors discussing thermal via design for MOSFET and IC packages with thermal pads

APEC-2013 94 Educational Professional Seminar MOSFET related PCB layout hints (cont.)

. In SMPS applications place MOSFETs as close to the drivers as possible . Route gate drive traces as differential pairs with the return pass traces or copper planes: the traces are routed next to each other within 10-20 mil . Use Kelvin connection for the driver return when possible . In high-current non-isolated DC-DC converters consider having footprints for simple RC snubbers at SW nodes . In isolated DC-DC converters consider having footprints for both clamps and snubbers to protect MOSFETs

APEC-2013 95 Educational Professional Seminar Recommended reading

. Vishay Siliconix MOSFET application notes at http://www.vishay.com/mosfets/related/#appnot . Estimating Junction Temperature by Top Surface Temperature in Power MOSFETs, Vishay AN-834. . MOSFET Thermal Characterization in the Application, Vishay AN-819. . ThermaSim Thermal Simulation Tool, http://www.vishay.com/mosfets/thermasim/ . G. Breglio, F. Frisina, A. Magri, P. Spirito. Electro-Thermal Instability in Low Voltage Power MOS: Experimental Characterization. 1999, IEEE, 0-7803-5290-4/99. . Power MOSFET Thermal Instability Operation Characterization Support, NASA/TM-2010-216684. 2010. . Tony Kordyban. Hot Air Rises and Heat Sinks: Everything You Know About Cooling Electronics Is Wrong. ASME Press, 1998.

APEC-2013 96 Educational Professional Seminar Summary

“Engineers like to solve problems. If there are no problems handily available, they will create their own problems”

- Scott Adams, cartoonist, creator of Dilbert

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This material is intended to help avoid some design problems.

APEC-2013 97 Educational Professional Seminar Please feel free contacting me directly with FAE support requests for MOSFETs and ICs if you are on my FAE territory

APEC-2013 98 Educational Professional Seminar

THANK YOU!

APEC-2013 99 Educational Professional Seminar