Computationally Efficient Design

COMPUTATIONALLY EFFICIENT DESIGN

AND IMPLEMENTATION OF SIC

MOSFET MODELS IN SPICE

BLAKE W NELSON

ANDREW LEMMON, COMMITTEE CHAIR MITHAT KISACIKOGLU KRAIG OLEJNICZAK AARON BROVONT TODD FREEBORN

A DISSERTATION

Submitted in partial fulfillment of the requirements for the degree of Doctor of Philosophy in in the Department of Electrical and Computer Engineering in the Graduate School of The University of Alabama

TUSCALOOSA, ALABAMA

2020

ABSTRACT

Transient simulation of complex converter topologies is a challenging problem,

especially in detailed analysis tools like SPICE. Much of the recent literature on SPICE transistor

modeling ignores the requirements of application designers and instead emphasizes detail,

physical accuracy, and complexity. While these advancements greatly improve model fidelity,

they also serve to increase computational complexity, making the resulting models less attractive

to application designers. This is in part because transistor models presented for SPICE are

generally evaluated by accuracy alone, without consideration for the computational cost of

model elements. Models designers tend to optimize toward the metrics by which their work is

judged; with little precedent for disclosing computation time in addition to accuracy, the natural

outcome is a plethora of highly accurate, detailed models which are less than ideal for complex

application simulations.

In order to optimize models for such simulations, this dissertation quantifies the relative

computational performance of modeling approaches and contextualizes the results with regard to

accuracy. This required the development of a new methodology for quantifying model computational performance. An extensive review of the relevant literature is undertaken to select candidate SiC MOSFET models likely to fare well in complex application simulations. By

analyzing the accuracy and computational performance tradeoffs of these candidates, new

insights into transistor model design and optimization are identified. These insights inform a new

SiC MOSFET model synthesized and optimized from the best-of-breed model elements

identified. By focusing on retaining high accuracy while making critical performance optimizations, the new model is ideally suited for complex converter simulations.

iii

LIST OF ABBREVIATIONS AND SYMBOLS

EV Electric Vehicle

EMC Electromagnetic Compatibility

EMI Electromagnetic Interference

DPT Double Pulse Test

GaN Gallium Nitride

GO Global Optimization

HEMT High Electron Mobility Transistor

HIL Hardware-in-the-Loop

LUT Lookup Table

MOSFET Metal Oxide Silicon Field Effect Transistor

MCPM Multichip Power Module

NPC Neutral Point Clamped

NLM Nonlinear Mapping Implementation (Variable Capacitors)

QDC Charge-Defined Capacitor Implementation (Variable Capacitors)

SOA Safe operating area

SiC Silicon-Carbide

SDI Simple Derivate Implementation (Variable Capacitors)

SPICE Simulation Program with Integrated Circuit Emphasis

TCAD Technology Computer Aided Design

WBG Wide Bandgap

ACKNOWLEDGEMENTS

Dr. Lemmon, as I review the progress that we have made in the last five years, I see

growth that is exponential, not linear. I am proud of what we have accomplished together, and I

am astonished by how much I’ve learned under your mentorship. I appreciate your willingness to

listen to feedback and your positivity when I felt frustration. You pushed me past what I thought

I was capable of and, even though it was a lot of work, I’m glad to have done so.

To my coworkers – Ali, Brian, Chris, Dylan, Jamie, Jared, Jin, Marshal, Sergio – thanks for being my friends and compatriots. Because of you, our lab has a fun and productive atmosphere. Chris, we both know that your hard work has been instrumental in making the lab what it is today, and I can’t imagine what it would be without you. Ali, thanks for carving the path the rest of us can follow. Brian, you’ve always been an excellent source of feedback and input. Jamie, even following your graduation your positivity has somehow stuck around. Jared, thank you for being the math guy, so the rest of us don’t have to. Jin, thanks for bringing your perspective, it has always expanded our horizons. Marshal, please don’t forget to put a resistor in series with your batteries. And finally, Sergio, thank you for your great attitude; it has always been a pleasure to work with you.

To my parents, thank you for inspiring me and always encouraging my curiosity. To my brothers, thank you for challenging me and providing models of excellence I hope I can live up to. Finally, and most importantly, I need to thank my wife, Brittany. I am confident that without your support I would not have finished this endeavor. For every encouraging word, thoughtful act, and bit of kindness, thank you. This one’s for you, hon.

CONTENTS

ABSTRACT ...... ii

LIST OF ABBREVIATIONS AND SYMBOLS ...... iv

ACKNOWLEDGEMENTS ...... v

LIST OF TABLES ...... ix

LIST OF FIGURES ...... x

CHAPTER 1: INTRODUCTION ...... 1

1.1. The Significance of Wide Bandgap Semiconductors ...... 1

1.2. Anatomy of SiC MOSFET Models...... 3

1.2.1. Numerical MOSFET Models ...... 4

1.2.2. Circuit-Level MOSFET Models ...... 4

1.2.3. Analytical MOSFET Models ...... 5

1.3. Application Space for MOSFET SPICE Models ...... 7

1.3.1. EMI Analysis ...... 7

1.3.2. Monte Carlo Analysis ...... 8

1.3.3. Dynamic Current Sharing Analysis ...... 8

1.3.4. Voltage Overshoot Prediction ...... 9

1.3.5. Short-Circuit Analysis ...... 9

1.4. Design Criteria for Application Focused MOSFET Models ...... 10

1.5. Conclusion ...... 11

CHAPTER 2: LITERATURE REVIEW ...... 13

2.1. SiC MOSFET Models ...... 13

2.1.1. Physics SiC MOSFET Models ...... 13

2.1.2. Semi-Physics SiC MOSFET Models ...... 16

2.1.3. Behavioral SiC MOSFET Models ...... 19

2.2. Notable Work on SiC MOSFET Interelectrode Capacitances ...... 21

2.2.1. Drain to Gate Capacitance ...... 22

2.2.2. Drain to Source Capacitance ...... 24

2.2.3. Gate to Source Capacitance ...... 26

2.2.4. Implementing Voltage Dependent Capacitance in SPICE ...... 27

2.3. SPICE Solver Parameters and Convergence...... 30

CHAPTER 3: MODELING MOSFET STATIC BEHAVIOR ...... 36

3.1. Introduction ...... 36

3.2. STATIC DOMAIN MODEL PERFORMANCE ...... 40

3.2.1. Fit Approaches and Challenges ...... 40

3.2.1. Fit Performance Comparison ...... 43

3.3. Computational Trade Study ...... 48

3.3.1. Overview of Simulation Study...... 48

3.3.2. Results of Simulation Study...... 54

3.4. Convergence Study ...... 58

3.5. Conclusion ...... 60

CHAPTER 4: MODELING DYNAMIC MOSFET BEHAVIOR ...... 62

4.1. Introduction ...... 62

4.2. Modeling a Discrete SiC MOSFET ...... 65

vii

4.2.1. Capacitance Measurements ...... 65

4.2.1. Small Signal Accuracy of Capacitance Models ...... 68

4.3. Empirical Setup ...... 70

4.4. Accuracy Analysis of Dynamic Models ...... 73

4.4.1. Accuracy Impact of Implementation Selection ...... 74

4.4.1.1. SDI Implementation Accuracy ...... 74

4.4.1.2. NLM vs QDC Implementations ...... 75

4.4.2. Accuracy Impact of Model Selection ...... 77

4.4.2.1. Influence of VGS Dependence ...... 77

4.4.2.2. Accuracy of Capacitance Models ...... 78

4.4.2.3. Accuracy of Charge Models ...... 79

4.4.2.4. Switching Loss Predictions ...... 80

4.5. Computational Analysis of Dynamic Models ...... 81

4.6. Conclusion ...... 87

CHAPTER 5: APPLICATION-FOCUSED SIC MOSFET MODEL ...... 89

5.1. Introduction ...... 89

5.2. Static Model Optimization ...... 89

5.3. Dynamic Model Optimization ...... 95

5.4. Final Model ...... 100

5.5. Conclusion ...... 107

CHAPTER 6: CONCLUSION AND FUTURE WORK ...... 109

REFERENCES ...... 111

APPENDIX ...... 125

viii

LIST OF TABLES

Overview Physics based SiC MOSFET Models ...... 14

Overview Semi-Physics based SiC MOSFET Models ...... 17

Overview Behavioral based SiC MOSFET Models ...... 19

CDG Models for SiC Power MOSFETs ...... 23

CDS Models for SiC Power MOSFETs ...... 25

CGS Models for SiC Power MOSFETs ...... 26

Models Selected for Trade Study ...... 39

SPICE Solver Parameters ...... 54

Convergence Study, Multi-Level DPT ...... 59

Models Selected for Trade Study ...... 65

Test Stand Parameter and Parasitic Values ...... 72

Parameter ...... 72

Value ...... 72

Study Conclusions: Model Speed vs. Accuracy ...... 87

Models Elements Selected for Synthesis ...... 100

LIST OF FIGURES

1. Application space for major semiconductor technologies, adapted from [8] ...... 2

2. Illustration of total and local capacitance adapted from [119] ...... 28

3. Five implementations of voltage-dependent capacitance suited for interelectrode capacitances, (a) nonlinear mapping implementation with external capacitor [37], [119], (a) nonlinear mapping implementation with in-line capacitor [38], (c) simple derivative implementation with capacitance definition [119], (d) simple derivative implementation with charge definition [94], (e) charge-defined capacitor implementation [117] ...... 29

4. Static domain model overlay at 25 °C ...... 44

5. RMS error at each temperature ...... 46

6. Equivalent RMS error for (a) forward, (b) transfer, and (c) mean over temperature ...... 48

7. Schematic template, double pulse test (DPT) ...... 50

8. Schematic template, buck converter ...... 50

9. Schematic template, neutral point clamped (NPC) inverter ...... 51

10. MCPM package model ...... 52

11. Multi-level MPCM package model ...... 53

12. Mean Run-time ...... 55

13. Mean run-time for each model and application with 32 die per switch position ...... 57

14. NPC Simulation complexity, run-time versus matrix size...... 58

15. Comparison between published models and experimental data for = 10 , = 600 V, = 75 A, = 25 °C, (a) behavior as published in the literature, and (b) altered to have identical interelectrode capacitance models 𝑅𝑅𝑅𝑅...... Ω ...... 63 𝑉𝑉𝑉𝑉𝑉𝑉 𝐼𝐼𝐼𝐼 𝑇𝑇𝑇𝑇 16. Measured interelectrode capacitance versus drain to source voltage ...... 66

17. Measured input capacitance versus gate to source voltage, denoted CGG ...... 67

18. Model comparison to experimental interelectrode capacitance data ...... 69

19. Equivalent RMS error for the interelectrode capacitance models against the four experimental datasets ...... 70

20. Empirical setup, DPT stand, gate drivers, and device under test (mounted to bottom of PCB) ...... 71

21. DPT system schematic, components, and metrology ...... 72

22. Comparison of NLM and SDI implementations with maximum solver timestep of (a) 1 ns, (b) 50 ps, (c) 10 ps ...... 75

23. Comparison of implementations with table functions ...... 76

24. Comparison of models to experimental DPT data, lookup table (LUT) including CGG, LUT with static CGS ...... 77

25. Models comparison to experimental DPT data, lookup table (LUT), composite function, arctangent model ...... 79

26. Models comparison to experimental DPT data, lookup table (LUT), Charge LUT, Charge Equation ...... 80

27. Switching loss comparison of models to experimental DPT data (all models include CGG) .. 81

28. Run-time of implementation for CGG cs Static CGS, using buck converter simulation with single die per switch-position ...... 83

29. Run-time of implementation vs die per switch-position, using capacitance-defined LUT model and buck converter simulation ...... 84

30. Run-time of model vs die per switch-position, using buck converter simulation ...... 85

31. Run-time of model vs die-per-switch position, buck converter ...... 86

32. Model prediction of experimental data, Forward and Transfer, TJ = 150 °C ...... 91

33. Run-time comparison between thermal models in DPT, for non-segmented core ...... 92

34. Non-segmented conduction model with three thermal model variants ...... 93

35. New thermal model prediction of experimental data, Forward and Transfer, TJ = 150 °C .... 93

36. Equivalent RMS error of thermal models at 150 °C for the three thermal models with non-segmented conduction model ...... 94

37. Run-Time in DPT of new thermal model versus prior art ...... 94

38. Small signal prediction of the charge composite function ...... 97

39. Comparison to other accurate capacitance models ...... 97

40. Time domain accuracy of charge composite ...... 98

41. Run-time of charge composite, for buck converter ...... 99

42. Final proposed SiC MOSFET model, combining all prior elements ...... 101

43. Final variant of proposed model, static validation ...... 103

44. Final variant of proposed model, dynamic validation, = 10 ...... 104

45. Final variant of proposed model, dynamic validation, 𝑅𝑅𝑅𝑅 = 4.7 Ω ...... 105

46. Final variant of proposed model, dynamic validation, 𝑅𝑅𝑅𝑅 = 2 ...... Ω ...... 106

47. Final variant of proposed model, switching loss prediction𝑅𝑅𝑅𝑅 ...... Ω ...... 107

48. spicebench: Analysis of LTspice simulation run-time using MATLAB ...... 127

49. PC Comparison ...... 129

50. Package inductance vs frequency ...... 130

51. Test stand impedance ...... 131

xii

CHAPTER 1:

INTRODUCTION

1.1. The Significance of Wide Bandgap Semiconductors

Power electronics is a categoric description of systems which actively interpose between

electrical sources and loads for the purpose of conversion, control, or isolation. Power electronics is an enabling technology for modern consumer electronics, renewable energy, electric vehicles, and many other industries; in total it represents a $16B market [1]. Approximately 40% of US energy consumption is accounted for by electric loads [2], and by 2030, up to 80% of this energy consumption will require power electronics in its path to delivery [3]. For at least the last 50

years, silicon (Si) transistors have shaped the power electronics application space as the primary

enabling technology [4], but the technical advantages of wide bandgap (WBG) semiconductors

have led to the displacement of Si in several key application areas [1].

The technical advantages of WBG semiconductors such as silicon-carbide (SiC) and

gallium-nitride (GaN) transistors are derived from their superior material properties [4]. Their

increased bandgap energy and breakdown field strength, for example, enable reduced on-state

resistance for a given size of active area [5]. This reduction in scale reduces the device intrinsic

capacitances, which leads to higher switching speeds, especially when coupled with the higher

saturation velocity of WBG semiconductors [6]. Therefore, for a given blocking voltage, WBG

semiconductors can achieve reduced conduction and switching losses compared to Si devices

[4]. Similarly, the high thermal conductivity and melting point of SiC [6] make it especially suitable for operation at very high temperature [7].

( W ) SiC MOSFET 103 IGBT

102 Thyristor Region of Competition 101 GaN 0 Si Bipolar 10 MOSFET Switching Power Power Switching 103 104 105 106 Operating Frequency (Hz)

Figure 1. Application space for major semiconductor technologies, adapted from [8] Figure 1 shows the general application space for the major semiconductor technologies, as identified by [8]. Because of performance advantages, cost differences, and technology limitations, each device type is best suited for a specific subset of power electronics applications.

Si IGBTs, for example, have lower conduction losses for a given blocking voltage than

MOSFETs (assuming equal device size). However, the lower switching losses of MOSFETs make them preferred for applications operating at high frequency [9]. Similarly, GaN devices exhibit lower switching losses than Si MOSFETs, but the higher cost of GaN over Si limits its market to applications with power levels and frequencies not serviced by Si MOSFETs [8]. The

SiC MOSFET, which will be the focus of this dissertation, is best leveraged in moderate to high power systems with relatively high operating frequency (above a few kHz).

An important corollary to operating frequency is power density, as the size of passive components, a large contributor to system size and weight, is dependent on operating frequency.

This, coupled with lower losses and higher blocking voltages, make SiC MOSFETs ideal for many applications that prioritize small volume and/or weight. In datacenters, for example, inter- rack distribution is increasing to 480 V and beyond [1], and the improved volumetric power density possible with SiC converters is critical due to the premium on space [2]. Similarly, the

gravimetric power density of SiC systems from 1.7 to 6.5 kV is well suited for light rail traction inverters [10]. Additionally, the high efficiency of SiC converters is especially desirable in the renewably energy sector [1]. The high efficiency, power density, operating temperature, and switching frequency are all contributors to SiC suitability for electric vehicle (EV) traction inverters and fast charging applications [1]. EVs represent a rapidly growing market for SiC, and the automotive market for SiC MOSFETs is estimated to reach $1B worldwide by 2024 [11].

System models are a vital tool in the development of these power electronic applications.

Such models can reduce the number of hardware iterations [12], [13], reducing development costs and time to market. Additionally, system models facilitate optimization of system performance [14] and can inform critical design requirements [15]. Finally, they can be used to mitigate risk related to electromagnetic interference (EMI) [16], controller instability [17], and device failure [18].

1.2. Anatomy of SiC MOSFET Models

SiC MOSFET models can be divided into three primary archetypes: numerical, circuit- level, and analytical. Numerical models, which consider the complete physical structure of the semiconductor [19], are the most complex and are best suited for semiconductor device design

[20]. The next archetype is circuit-level MOSFET models (such as SPICE models), which are designed for, although not limited to, electrical transient analysis. The final model archetype is analytical models; rather than attempting so solve for semiconductor behavior at discrete timesteps, these models use arithmetic simplifications [21] or piecewise-linear definitions of switching events [22].

1.2.1. Numerical MOSFET Models

Numerical models are generally created using technology computer aided design (TCAD) software packages [23]. Numerical models are critical in the design of new semiconductor devices as they enable prediction of the transistor behavior prior to the expensive manufacturing process [19]. Unlike the other model types, which employ varying levels of simplification, numeric models can be leveraged for evaluation of performance for preliminary device-level designs [24], [25], detailed analysis of the causes of device failures [26], [27], and optimization

of manufacturing processes [20]. While they are capable of evaluating device characteristics

such as switching losses [25], their high complexity makes them unsuitable for all but the

simplest time domain simulations [23]. While numerical models are a critical piece of the

MOSFET modeling domain, they will not be emphasized in this work due to their lack of

relevance to application design.

1.2.2. Circuit-Level MOSFET Models

Circuit-level MOSFET models are implemented in software packages such as SPICE

[28], SABER [29], and ADS [30]. The defining feature of circuit-level MOSFET models is the

emphasis on electrical domain transient analysis. Circuit-level models are a powerful tool for

expediting product development and have a high rate of adoption in the industry [31] due to a

rich history (which extends at least 45 years [32]), a wide variety of use cases, and substantial

support from semiconductor manufacturers. The application space of circuit-level MOSFET

models is wider than the other archetypes; it not only has significant overlap with numerical

models [33], [34] and analytical models [35], but is also uniquely suited for many simulation

studies of which the other model types are incapable. These applications include EMC analysis,

Monte Carlo simulations, dynamic current sharing analysis, voltage overshoot prediction, and short-circuit analysis. These applications will be discussed in section 1.3.

The design of circuit-level models is heavily influenced by their intended applications.

For example, circuit-level models can be used for device design optimization [36] (similar to

TCAD models). Such models must be carefully constructed from physical descriptions of material properties and device layout so that their performance can be linked back to the device design [33]. This is in stark contrast to models optimized for application design, which often ignore physical phenomena in favor of mathematical descriptions with continuous definitions

[13], [37] or which can be easily fit to experimental data [38]. Other circuit-level models select physically accurate descriptions of the physical domains while avoiding proprietary process details [39]. Finally, circuit-level models can be extended to represent not only the thermally dependent electrical behavior of semiconductors but also the transient junction temperature with package and self-heating models [35].

1.2.3. Analytical MOSFET Models

Many analytical MOSFET models are developed for general mathematic software packages like MATLAB [40] or state-space solvers like Simulink [41]. A popular tool for analytical power electronics modeling is the PLECS software package (which was originally a blockset for Simulink [22]). The popularity of PLECS is partially due to its focus on power electronic system design, but also because it benefits from significant partnerships with major semiconductor vendors such as Cree, Inc. [42], Infineon Technologies [43], and GaN Systems

[44]. These partners provide and support a substantial catalog of device and example system models for application designers to leverage.

PLECS uses an ideal switch model for transistors and dynamically selects integration

timesteps before and after the instantaneous change in transistor resistance. This analysis

approach is a primary contributor to its speed advantage over circuit-level simulations [22].

Because electrical components are idealized, power losses are analytically described (by lookup

table or function) and can match experimental results. When the fast runtime and accurate loss

models are considered together with its mechanical, thermal, and magnetic [45] domain models,

PLECS is recognized as an effective tool for many converter design tasks, such as efficiency prediction [46], controls development [47], or thermal management system design [48].

The design of PLECS also enables hardware-in-the-loop (HIL) testing for real-time simulation, in which the controller is simulated with the physical power stage (Power-HIL) or in which the power stage of the system is simulated for the purpose of controller development

(controller-HIL) [17]. The latter approach gives application engineers the capability to validate their controller hardware and software during the development of the power stage, which can eliminate significant bottlenecks in converter development [49]. The necessity of real-time operation in HIL simulations generally limits this approach to using substantially simplified models. More detailed models, such as those implemented in SPICE, could not be used in real- time simulations without significant optimizations [50]. As standard PLECS models are not optimized for the fixed timestep of real-time simulations, sub-cycle averaged models are leveraged. These models have higher computational efficiency in fixed-timestep solvers by averaging the model behavior between output times. This allows the system to use smaller output timesteps for a given topology and computing hardware platform [17]. The highly specialized nature of HIL applications makes them ideal for an important subset of application design challenges, but this approach is not preferred for many general simulation studies.

1.3. Application Space for MOSFET SPICE Models

While the fundamental simplifications of PLECS make it a valuable tool for many application simulations, there is a broad set of simulations which cannot be evaluated given these idealizations. Specifically, system characteristics which are dependent on edge-rates, certain semiconductor non-idealities, or circuit dynamics cannot be studied with analytical models in

PLECS. On the other hand, the complexity of numeric simulations limits them to basic time domain predictions which do not consider topology, parasitics, or multiple transistors. Any design question which falls between the boundaries of numeric and analytical models requires circuit-level simulations or hardware-level analysis. A small subset of possible examples includes EMC analysis, Monte Carlo simulations, dynamic current sharing analysis, voltage overshoot prediction, and short circuit analysis.

1.3.1. EMI Analysis

A critical challenge introduced by WBG semiconductors is the increase in generated EMI as a consequence of increasing edge rates, switching frequencies, and bus voltages [51]. While specialized analytical models have been presented which can be used to derive mitigation strategies [52], such strategies are more likely to be considered by EMI specialists than power electronics engineers. Instead, trial and error is a common strategy leveraged in passing compliance [53]. This method can be effective, but the EMI challenges of WBG power electronics dramatically increase the time, cost, and technical risk of this approach. These challenges can be reduced through the careful application of SPICE models for the prediction

[54] and mitigation [55] of EMI.

1.3.2. Monte Carlo Analysis

Monte Carlo analysis refers to a broad class of studies which approach numeric results

through repeated random sampling. This class of analysis has long been an important tool in

determining the tolerances of electronic circuit designs [15] and is appropriate in the

development of power electronics [56]. This workflow provides a critical path to approximating

worst-case circuit performance when the circuit complexity obfuscates the worst-case parameter set [15]. For example, Monte Carlo simulations can be used to study the effect of passive component tolerance on filter phase shift or ripple voltage [56]. The parameter tolerances of SiC

MOSFETs can also play a large role in converter performance. Using Monte Carlo analysis, circuit-level models can be used to correlate the variance of device parameters (such as on-state resistance and threshold voltage) with circuit performance (such as power loss distribution) [57].

While the analysis of MOSFET parameter tolerances is generally considered part of the optimization of device manufacturing [36], [58], SiC MOSFETs are a comparatively new technology with larger tolerance ranges compared to Si devices. Therefore, consideration of device tolerance ranges in SiC MOSFET applications can lead to significant performance improvements in module and converter designs [57].

1.3.3. Dynamic Current Sharing Analysis

Designing systems with parallel MOSFETs introduces several design challenges such as dynamic current imbalance. Dynamic current sharing describes the ratio of conducted current between the parallel devices during switching transients. Imbalance in dynamic current creates higher voltage overshoot [59] which can reduce device lifetime [60]. Similarly, steady-state current imbalance can lead to thermal offset and derating of total switch-position current [59]. A single MOSFET failure during operation generally escalates into failure of the entire switch

position. This makes management of current imbalance especially important to module design.

The two primary causes of dynamic current imbalance are mismatched device parameters and unequal circuit parasitics [59]. Circuit-level models can be used to study the effect of variations in device parameters [57], [60], circuit parasitics [60], [61], and junction temperatures [60] on dynamic current sharing between paralleled devices. A primary strategy for balancing current between paralleled devices is the careful selection of per-device gate-drive resistors [62]. Circuit-

level models are an excellent tool for selecting these resistance values.

1.3.4. Voltage Overshoot Prediction

The peak voltage bias applied across the MOSFET drain and source terminals is a critical

device stress which can quickly lead to complete breakdown [63]. Repeated exposure to high

voltages at switching transitions can also reduce mean time to failure [60]. Without external

mitigation strategies, the lowest acceptable gate drive resistance is often determined by the

maximum tolerable overshoot voltage at turn-off [63]. This is because decreasing gate-drive resistance increases MOSFET switching speed, which reduces losses but increases overshoot voltage [64]. Therefore, managing voltage overshoot is critical in high efficiency converter design [65]. Properly designed circuit-level models that include accurate parasitic estimates can be used to predict expected overshoot voltage levels [18], analyze suitable gate drive resistance values [63], and design snubber strategies if necessary [66].

1.3.5. Short-Circuit Analysis

Short-circuit withstand time is an important factor in determining device and system ruggedness [67]. Protection schemes generally attempt to detect short-circuit events and rapidly quench them. For SiC MOSFETs, short-circuit response must occur within a very short window due to the high switching speed of SiC MOSFETs [68] and the relatively thin blocking region

within the device design [34]. By joining an accurate electrical model of MOSFET behavior with

a detailed thermal model, direct prediction of short-circuit current and junction temperature is possible [35]. This type of circuit-level model is suitable for transient thermal analysis of junction temperature in short-circuit events [34] and development of fault protection circuits

[69].

1.4. Design Criteria for Application Focused MOSFET Models

The usefulness of system models for power electronics applications is dependent on their accuracy, convergence reliability, and simulation speed. However, there are significant challenges in achieving all three criteria simultaneously [70], especially when considering the

general increase in simulation complexity for fast switching WBG semiconductors [71] or multi-

level converter topologies [49]. Therefore, application engineers have a need for models which

are optimized for simulation speed and robust convergence while still performing with

acceptable accuracy. This, however, stands in stark contrast with the general trend of increasing

model complexity [72].

The literature is replete with examples of SiC MOSFETs models, some of which are

intended for application simulations [13], [37], [38]. While most papers provide some means of

model validation, they generally do not provide any means to quantify the performance of the

presented model. The most common model validation technique is graphical overlays of

experimental data and simulation predictions, usually for static characterization curves and

double-pulse test (DPT) waveforms. However, without quantitative metrics, comparisons

between papers is challenging. Inclusion of quantitative metrics, such as the root-mean-square

(RMS) error of the forward curve prediction, could improve comparisons between models published by independent groups. Additionally, DPT comparisons provide minimal insight into

model convergence or run-time for larger applications [37], so models intended for such

applications should be evaluated in more complex circuits. This is part of a larger trend in the

literature; computational complexity is rarely addressed, and model accuracy is generally

assessed by qualitative analysis instead of quantitative results.

1.5. Conclusion

This dissertation develops a new circuit-level model for application simulations which is

suitable for use in complex converter topologies. A model which produces inaccurate results is

of minimal value, independent of the time required to achieve those results. Therefore, the focus

of this optimization effort is the selection and development of model features which have the

lowest possible run-time without incurring major penalties in terms of predictive accuracy. This

development is carried out in two stages. First, a comprehensive analysis of state-of-the-art models is considered. In addition to identifying such models, a subset of the models identified is

evaluated to quantify the tradeoffs between simulation performance and model accuracy.

Second, the best elements of the identified models are selected, combined, and further optimized to synthesize a new MOSFET model.

The contributions of this work are as follows. First, this dissertation provides a targeted addition to the thorough survey of SiC MOSFET models presented in [23]. Second, it proposes useful metrics for determining the suitability of MOSFET models for use in application simulations. Third, it identifies, catalogs, and quantifies the accuracy and performance of many recent static and dynamic MOSFET modeling contributions, which would not be possible from inspection of the relevant literature. Fourth, because this requires a detailed analysis of relative run-time performance, a new framework for run-time quantification is proposed. Fifth, from the study outcomes, this dissertation identifies key considerations and tradeoffs which should inform

future model design. Finally, using the developed body of knowledge, this dissertation

synthesizes a new SiC MOSFET model which is uniquely optimized for application design. In

total, this dissertation expands the current understanding of MOSFET modeling through

quantitative analysis.

This dissertation is organized as follows. Chapter 1 discusses the importance of circuit- level SiC MOSFET models and highlights some of the most important applications for such models. Chapter 2 presents a detailed study of the pertinent literature. The subsequent analysis is segmented into two primary domains of MOSFET behavior: static and dynamic. This division of behaviors is well established in the literature [16], [37], [38], [73]–[85], and is used to bisect the scope of this research into two manageable domains. Accurately representing MOSFET static behavior is a necessary, though not sufficient, condition for achieving accurate time domain predictions. This behavior is therefore considered first in chapter 3. MOSFET static behavior describes the dependence of channel current on gate-source voltage, drain-source voltage, and junction temperature [16]. These characteristics are critical for predicting conduction losses in

MOSFETs [86]. Chapter 4 investigates the dynamic behavior of the SiC MOSFET, which is critical for determining transient accuracy and switching losses [73]. Chapter 5 presents the down-selection of model components based on the prior analysis and proposes critical enhancements to address the shortcomings of SiC MOSFET models presented in the literature.

Chapter 5 also presents the newly synthesized SiC MOSFET model and provides a detailed analysis of its accuracy and computational efficiency. Finally, chapter 6 presents the conclusions of this dissertation.

CHAPTER 2:

LITERATURE REVIEW

2.1. SiC MOSFET Models

The prior chapter demonstrates the importance of circuit-level SiC MOSFET models and

highlights critical applications that require such models. It also defines the set of model criteria

to be used in the development of an application-focused MOSFET model. Rather than develop a new model in isolation, this work seeks to build upon the prior art by identifying “best of breed” models and synthesizing an optimal combination of their constituent elements. To support this approach, this chapter presents a detailed evaluation of the most relevant circuit-level MOSFET

models documented in the literature. Additionally, it adopts the organization of [23], [87] which

categorizes circuit-level models into physics, semi-physics, and behavioral categories.

2.1.1. Physics SiC MOSFET Models

Physics-based MOSFET models are developed from descriptions of the semiconductor

physics. Unlike numerical models, which simulate the 2-D interactions of particles and materials,

physics models make simplifying assumptions and typically model domains rather than finite

elements. Despite being relatively complex, physics-based models are generally capable of time-

domain simulation, though suitability for complex application simulations varies between

models. An overview of the physics-based SiC MOSFET models identified in the literature is

shown in Table I.

TABLE I OVERVIEW PHYSICS BASED SIC MOSFET MODELS Sim. First Author Year Primary Contribution Tool 2003, McNutt [88], [89] IMPACT Described channel current as the sum of two physical phenomena 2007 Hasanuzzaman 2003, PSpice New model of drift region with three geometric domains [90], [91] 2006 Resistance network and nonlinear voltage source used to model Fu [92] 2012 PSpice JFET region current distribution 2011, Refined McNutt model to fit parameters using datasheet Mudholkar [39], [93] SABER 2014 exclusively Hossain [94] 2018 LTspice Adapted model [39] for use in SPICE Peng [95] 2016 PSpice 3rd quadrant model derived from ADE by Fourier series Diao [96] 2017 ADS Implements McNutt model with Verilog-A 2016, ANSYS Mukunoki [73], [80] Adjustable channel mobility, CGS & CGD dependence on VGS 2018 Simplorer Not Jouha [97] 2018 Extends [89] via λ and L-M Optimized Parameter Extraction indicated Adapted Angelov GaN HEMT Model for SiC MOSFET, extend Sakairi [16] 2018 ADS static characterization to HVHC region, characterize CV with device gated on Shintani [98] 2018 SIMetrix Model defined by surface potential 2017, Not SPICE model exhaustively defined from process and layout He [33], [36] 2020 indicated parameters

An important group of physics-based models emphasizes descriptive accuracy to a degree that comes at great expense to simulation complexity. For example, Hasanuzzaman et al. present a model of the carrier and drift regions based on a geometric analysis of carrier transport in the vertical double implanted MOSFET (DIMOS). Further, the drift region is considered in three subdomains, (a) the upper accumulation region, (b) the lower domain where cross sectional area is constant, and (c) the domain connecting (a) and (b) where cross section is not constant [90]

[91]. Fu et al. use finite-element analysis of current distribution in the JFET region to develop a resistance network and nonlinear voltage source model [92]. In [33], He a et al. develop a model from process parameters which attempts to avoid any simplifications. This model includes a bsim3v3 model of channel physics, a SPICE JFET model for the epitaxial region, a nonlinear description of the drift region, and a representation of the depletion pinching effects of Miller capacitance. Because the model is based entirely on process and transistor layout parameters, it

not only allows accurate scaling to alternate chip dimensions but also enables device design

optimization by linking time-domain performance to the manufacturing process within SPICE

[36].

Many physics-based models, however, are designed to balance the fidelity of the device description with usability in time-domain simulations. An early model for SiC MOSFETS, which has been revisited and refined in many publications, is presented by McNutt et al. in [88], [89].

This model is a physical description of the channel that considers (a) regions that turn on at lower gate voltages, and (b) the nonuniformity of doping, which leads to enhanced linear-region

transconductance. In addition to increasing model flexibility, this arrangement enables the model

to capture the gradual transition between the linear and saturation regions of MOSFET

conduction behavior. Mudholkar et al. extend McNutt’s model with emphasis on identifying all necessary parameters exclusively using datasheet values [39], [93]. Hossain would later adapt this model to operate in LTspice [94]. An alternate extension of McNutt’s model is presented in

[96] by Diao. This Verilog-A implementation includes estimates of critical system parasitic elements and the associated study emphasizes time-domain validation. Another extension of the

McNutt model is presented by Jouha et al. in [97]. This modified model includes a channel length modulation term (λ) and improves parameter extraction via the Levenberg–Marquardt (L-

M) optimization algorithm.

In addition to the McNutt model and its derivatives, many other compact physics-based models have also been presented. In [95], Peng presents a physics-based 3rd quadrant model for a

SiC MOSFET derived from the ambipolar diffusion equation (ADE) in the drift layer using the

Fourier series. This enables calculation of the carrier distribution in the region, which is used to

model the voltage drop across the device. Mukunoki et al. present a new model with adjustable

channel mobility in [73]. This parameter is used to simplify the computational complexity of the conduction branch without significantly impacting accuracy. Additionally, the model of CGD is expanded in this model by capturing its dependence on VGS via gate-charge measurements under different bias conditions. Mukunoki et al. further expand upon this model in [80] by adding the

VGS dependence of CGS. Sakairi et al. present a modified version of the Angelov-GaN HEMT

model [99] that is suitable for SiC MOSFETs in [16]. They also extend the static characterization

region to the high-voltage, high-current region using analysis of switching transients. This paper

also improves the prediction of dynamic behavior by adjusting the device non-linear

capacitances when the device is gated ON. Finally, Shintani et al. present a SiC MOSFET model

based on surface potential, which considers interface traps, and which is fit over wide I-V, C-V,

and temperature ranges [98].

2.1.2. Semi-Physics SiC MOSFET Models

Semi-physics models have characteristic equations inspired from device physics;

however, liberties are taken to better balance computational complexity against physical realism

[100]. Process parameters and other proprietary details may be eliminated by this approach

[101]. A popular subset of semi-physics models extend physics-based models initially presented

for Si MOSFETS [102], [103] by including additional dependencies to improve fidelity for

modeling SiC power MOSFETs. An overview of the semi-physics-based models identified in the

literature is shown in Table II.

TABLE II OVERVIEW SEMI-PHYSICS BASED SIC MOSFET MODELS Sim. First Author Year Primary Contribution Tool Extends Level 1 model for SiC with the inclusion of temperature Wang [77] 2008 PSpice dependent threshold voltage and channel transconductance Phankong 2009, Not Nth power law MOSFET model adapted [104], [105] 2011 indicated for 1200 V SiC MOSFET Nth power law MOSFET model adapted Cui [76] 2012 PSpice for 1200 V SiC MOSFET 2013, Extend [77] for subzero temperatures Sun [106], [107] PSpice 2014 and bipolar gate driving 2013, Extends [107] with Foster RC network thermal model, improved Yin [108], [79] PSpice 2017 body diode model, and piecewise continuous CDG model Extends Level 1 with temp temperature dependent threshold D’Alessandro [82] 2014 Pspice voltage, channel transconductance, carrier mobility, and avalanche behavior Riccio [58], [81], 2018, Extends [82] with thermally dependent ILEAK, SIMetrix [109] 2019 out-of-SOA, and mobility degradation Adapts Level 1 model for simpler extraction which removes Arribas [101] 2015 LTspice requirement of process parameters Fu [100] 2015 PSpice Introduces simplified description of JFET region Extends Level 1 model to include Zhou [110] 2018 LTspice effects of interface traps

Many SiC models leverage and modify the Shockley lateral MOSFET equations, or derivatives such as the Level 1 MOSFET, for the vertical SiC MOSFET structure. In [77], for example, a modification to the Level 1 model is proposed which includes temperature-dependent threshold voltage and transconductance. Additionally, it considers the reduced carrier mobility within the SiC drift layer and JFET region (as compared to the Si MOSFET described by the

Level 1 model). This model is extended by Sun et al. in [106], [107] to accurately model subzero temperatures and bipolar gate driving. Further additions to Sun’s model are presented in

[108]. In this paper, a more accurate prediction of junction temperature is achieved by modeling self-heating and introducing a Foster thermal network. Additionally, the body diode model is improved through an alternate implementation of the Shockley lateral MOSFET equations.

Further improvement of this model is presented in [79]. In this paper, the switched-capacitance model of CDG is replaced with a piecewise continuous fitting function.

In [82], an extension of the Level 1 model is presented which is similar to [77] in that it also includes thermally controlled threshold voltage and channel resistance. However, it also models the temperature-dependence of carrier mobility and avalanche effects via two additional current sources parallel to the Level 1 core. Riccio et al. extend this work in [82] to include drain-source leakage current over temperature, short-circuit behavior, and mobility degradation dictated by high electric fields [81]. Additionally, these authors demonstrate that this model is suitable for evaluation of process variance from device characteristics dispersion [58]; and they present model validation results at a dc bias of 3.3 kV [109].

Other alterations of the Level 1 model have also been shown in the literature. For example, in [101], Arribas et al. present a version of the Level 1 which benefits from a simplified extraction process by removing reliance on empirical parameters unknown to the end user. In

[100], Fu et al. simplify a model presented in their prior work [92] by representing the JFET region of the SiC MOSFET with a dependent voltage source rather than a resistive network.

Zhou et al. provide a modified Level 1 model that captures the influence of interface traps in

[110]. This contribution is relevant for modeling SiC MOSFETs because interface traps are more prevalent in the SiC/SiO2 interface than in Si/SiO2.

In addition to the Level 1 model, the nth power law MOSFET model, introduced by

Sakurai and Newton [103] for short-channel CMOS devices, is commonly used as a basis for vertical SiC MOSFET models due to its low computational complexity and fast parameter extraction. In [104], [105], Phankong et al. adapt the nth power law model for 1200 V SiC power MOSFETs by altering its equations to describe the physical structure of SiC MOSFETs.

Cui provides an alternate adaptation of the nth power law MOSFET model in [76] which includes additional consideration for the thermal dependence of SiC MOSFET behavior.

2.1.3. Behavioral SiC MOSFET Models

Behavioral models generally ignore any physical mechanism driving device operation, instead favoring arithmetic fitting methods and mathematic descriptions that best produce the desired behavior. While this leads to parameters devoid of physical meaning, behavioral models can be both simpler to implement and more computationally efficient than their physically defined counterparts. An overview of the behavioral models identified in the literature is shown in Table III.

TABLE III OVERVIEW BEHAVIORAL BASED SIC MOSFET MODELS Sim. First Author Year Primary Contribution Tool Extend Si EKV model for SiC by modeling soft saturation in Pushpakaran [111] 2015 LTspice conduction equation Behavioral fitting functions defined in piecewise segments to Duan [78] 2018 LTspice better match static characteristics ANSYS Mukunoki [83] 2018 Expanded output characterization to include VDS of 200 to 800 V Simplorer Not SPICE model with continuous and widely defined equations for Sochor [13] 2019 indicated ID and interelectrode capacitances Li [35], [37] 2019 Pspice Continuous model definition across all domains Universal FET model defined by simple equations and parameter Endruschat [38] 2019 LTspice tables 2018, Extension of [38] with emphasis on Sellers [112], [113] LTspice 2020 algorithmic time domain tuning Not Thermo-electric SPICE model defined by sum of temperature Rizzo [114], [115] 2020 indicated dependent current sources

Behavioral models are often developed to optimize computational complexity, minimize

run-time, and produce robust convergence. For example, Mukunoki et al. replace the physics- based conduction model of [73], [80] with a behavioral description in order to improve the run- time performance and remove proprietary geometric data from the modeling process in [83].

Additionally, this paper extends the static characterization of the model to include VDS

dependence from 200 to 800 V via load-short-circuit waveforms. In [111], Pushpakaran extend a fast and lightweight Si model called the EKV model [116] to represent SiC MOSFETs by altering the conduction characteristic equation to include channel length modulation in the

saturation region. In [114], Rizzo et al. demonstrate a behavioral model for SiC MOSFETs that

is defined by the summation of individual current sources for modeling the linear/saturation,

breakdown, and reverse conduction regimes. This model is extended by Raffa in [115] with

provisions for modeling self-heating and with inclusion of a fourth-order Foster thermal network

to accurately predict transient junction temperature. Duan et al. present a low-complexity

behavioral model which uses piecewise definitions to segment the conduction behavior into

linear and saturation regions. The interelectrode capacitance model of CDG is similarly

segmented in this model [78].

In the field of behavioral device modeling, several authors emphasize that continuous

definitions are a critical requirement for fast, convergent models. For example, in [13], Sochor et

al. present a continuous behavioral model which is defined with a large number of parameters

and fitting equations. This model predicts drain current with a hyperbolic tangent multiplied by a

polynomial definition of saturation current. Additionally, this model employs a summation of

multiple exponentials and hyperbolic tangents to define the interelectrode capacitances

continuously and accurately. Similarly, Li et al. develop a behavioral model that is continuously

defined across all operating conditions, avoiding segmentation between domains [37]. These authors also propose a novel approach to model thermal dependence, in which VGS and VDS are

scaled and shifted as a function of temperature before calculating drain current. In [35], the

authors extended this model to accurately predict short-circuit behavior through the addition of a

thermal impedance network and by including provisions for modeling device self-heating.

An alternate approach to complex continuous functions is parameter-mapped lookup tables. In [38], Endruschat et al. present a modified version of the Curtice model, originally published in [84], that is sufficiently flexible to accurately represent the behavior of GaN

HEMTs or SiC MOSFETs. This model is implemented with simple analytical equations and parameters defined across operating conditions via lookup tables, which the authors recommend for fast simulation characteristics. Sellers et al. present an extension of this model in [113] using a model tuning strategy which determines fitting parameters from time-domain accuracy metrics.

Additionally, this model uses charge-defined lookup tables for capacitance.

2.2. Notable Work on SiC MOSFET Interelectrode Capacitances

The physical structure of the MOSFET leads to charge accumulation regions which are highly sensitive to change in voltage bias. These regions can be described by interelectrode capacitances which are dependent on the applied voltage bias [89]. These capacitances are the critical determinant of dynamic behavior in hard switching events [83]. Because of the critical nature of interelectrode capacitances in determining time-domain behavior, this section provides an in-depth treatment of papers that present unique and notable contributions to the modeling of these structures. This analysis is necessary to provide a suitable foundation for determining which candidate models are best suited for evaluation in the later phases of this study.

There are two fundamental questions that must be answered when developing a model of the intrinsic capacitances of the SiC MOSFET structure. The first question concerns the voltage bias dependencies of the intrinsic capacitance profile that are to be represented by the model. It is widely recognized that the drain-gate capacitance (CDG) and the drain-source capacitance

(CDS) are strongly dependent on the MOSFET drain-source voltage (VDS) bias [89], and the

majority of MOSFET models include these sensitivities. Additionally, while gate-source

capacitance (CGS) has a modest dependence on VDS [13], many SiC MOSFET models neglect

this dependence in favor of a fixed linear capacitor for the implementation of CGS [37], [39],

[79], [81], [89], [98], [110], [114], [117]. More recent studies [16], [38], [83] extend these

models by demonstrating that CGS is strongly dependent on the gate-source voltage (VGS) bias.

Finally, a few models also consider the sensitivity of CDG on VGS bias [16], [80]. The present

study evaluates the three sensitivities most commonly considered in the literature. Specifically,

the VDS sensitivity of CDG and CDS are considered, along with the VGS sensitivity of CGS.

However, the VGS sensitivity of CDG is neglected in this work to keep the analysis tractable.

The second question concerns the model utilized to describe the relationship between the

intrinsic capacitances and the applied voltage biases. SiC MOSFET models in the literature

address this question in a number of ways, but the approaches can generally be grouped into two

categories. The first approach defines capacitance via a lookup table [38], [73], [114], [117],

and the second approach defines capacitance using a mathematical fitting function that is tuned

to approximate the voltage dependency [13], [16], [37], [39]. The present study evaluates these

approaches by creating five unique candidate models of interelectrode capacitance which broadly

span the relevant types of models published in the literature.

2.2.1. Drain to Gate Capacitance

The drain to gate capacitance, often called the Miller capacitance, is considered the most crucial of the interelectrode capacitors in determining the transient behavior of the SiC MOSFET

[83]. Table IV lists many of the different models of CDG presented in the literature. From the evaluation of the literature, three model-subgroups can be defined for CDG. The first group,

piecewise functions, segment CDG into regions of behavior which are modeled with different

equations, allowing for high fitting accuracy [118]. Several authors claim piecewise definitions may lead to convergence issues [13], [117], and recommend other modeling approaches.

Piecewise defined models often use two equations to capture CDG [78], [89], [110], where the

capacitance at low voltage bias is static. This generally corresponds to a corner point at

< 0 [78], [110]. However, McNutt et al. identify a temperature dependent corner voltage

𝐷𝐷𝐷𝐷 in𝑉𝑉 [89]. Additionally,𝑉𝑉 piecewise definitions with more than two segments have also been defined

[79], [118]. Both of these models use a static capacitance for < 0 , and define two

𝐷𝐷𝐺𝐺 additional segments for the variable depletion region. In [118]𝑉𝑉, a fourth𝑉𝑉 segment is defined which sets a minimum static capacitance at high VDG.

TABLE IV

CDG MODELS FOR SIC POWER MOSFETS Model Dep. First Author Year Formulation Type Variable

Physics, Static COX and variable depletion capacitance, McNutt [89] 2007 , Piecewise VGS dep. gate inversion layer capacitance 𝐷𝐷𝐷𝐷 𝐺𝐺𝐺𝐺 Physics, 𝑉𝑉 𝑉𝑉 Static COX, 2-part depletion definition, and lower Cheng [118] 2019 Piecewise bound Semi-Physics, 𝐷𝐷𝐷𝐷 Yin [79] 2017 𝑉𝑉 Static COX and 2-part depletion definition Piecewise Behavioral, 𝐷𝐷𝐷𝐷 Below 0 V: tanh Duan [78] 2018 𝑉𝑉 Piecewise Above 0 V: arctan Mudholkar Physics, 𝐷𝐷𝐷𝐷 2014 𝑉𝑉 Static COX and variable depletion capacitance [39] Continuous Mukunoki Physics, 𝐷𝐷𝐷𝐷 2018 𝑉𝑉, Sum of exponentials [80] Continuous Physics, 𝐷𝐷𝐷𝐷 𝐺𝐺𝐺𝐺 Sakairi [16] 2018 𝑉𝑉 , 𝑉𝑉 Sum/product of tanh’s and junction capacitances Continuous Shintani Physics, 𝐷𝐷𝐷𝐷 𝐺𝐺𝐺𝐺 2018 𝑉𝑉 𝑉𝑉 Static COX and variable depletion capacitance [98] Continuous Semi-Physics, 𝐷𝐷𝐷𝐷 Zhou [110] 2018 𝑉𝑉 Inverse power function, Piecewise 𝑎𝑎 𝑉𝑉 𝑐𝑐 Semi-Physics, 𝐷𝐷𝐷𝐷 𝐺𝐺𝐺𝐺 − 𝑎𝑎 Riccio [81] 2018 𝑉𝑉 arctan �1− 𝑏𝑏 � Continuous Behavioral, 𝐷𝐷𝐷𝐷 Li [37] 2019 𝑉𝑉 Sum of logistic functions Continuous Behavioral, 𝐷𝐷𝐷𝐷 Sochor [13] 2019 𝑉𝑉 Sum of tanh’s and exponentials Continuous Mukunoki Physics, 𝐷𝐷𝐷𝐷 2016 𝑉𝑉 LUT: capacitance [73] LUT Endruschat Behavioral, 𝐷𝐷𝐷𝐷 2019 𝑉𝑉 LUT: capacitance [38] LUT Behavioral, 𝐷𝐷𝐷𝐷 Rizzo [114] 2020 𝑉𝑉 LUT: capacitance LUT Heckel Behavioral, 𝐷𝐷𝐷𝐷 2015 𝑉𝑉 LUT: charge [117] LUT 𝑉𝑉𝐷𝐷𝐷𝐷 The second group is continuously defined functions, which are recognizable by their continuously differentiable equations. Behavioral models within this group only consider the 23

shape of the function, generally using arctangent [78], [81], hyperbolic tangent [13], [16], [78],

exponential [13], [80], and logistics functions [37]. However, continuously defined physics

models derive more complex equations from semiconductor physics. Physics models often show

substantial differences in equations, even for models describing the same phenomena [39], [98].

The third group identified is lookup tables (LUTs), which are often cited for their ease of

use [117], since they can be defined directly by measured data [119]. There is also a lack of

consensus in the literature on the suitability of LUTs in terms of convergence. In [117], Heckel

claims that LUTs cause fewer convergence issues than piecewise-defined models. On the other

hand, in [119], Zeltser explains that LUTs may cause more convergence problems than

continuous functions due to “the discrete nature of the data and the irregularity of the array.”

While LUTs are generally defined in terms of capacitance [38], [73], [114], LUTs defined in

terms of charge have also been presented [117].

In addition to model type, models can also be distinguished in terms of dependencies

captured. Because the voltage across CDG is approximately -VGS,MAX when the device is gated

ON, it is necessary to to extend the dataset of CDG for < 0 [38], [73], [98]. In general,

𝐷𝐷𝐷𝐷 these papers show an increase in CDG for < 0 . However,𝑉𝑉 𝑉𝑉several authors model CDG with

𝐷𝐷𝐷𝐷 independent contributions from VDS and V𝑉𝑉GS [16], 𝑉𝑉[80], [89]. The authors of [16] and [80] calculate the dependence of CDG on VGS from experiment and highlight the substantial increase

in Miller capacitance for < 0 .

𝐷𝐷𝐷𝐷 2.2.2. Drain to Source𝑉𝑉 Capacitance𝑉𝑉

The primary contributor to drain to source capacitance is the bias-dependent charge at the junction of the p+ region and n- epitaxial layer [98]. As a result, many MOSFET models use the

definition of junction capacitance available in the SPICE diode model [37], [78], [79], [110] for

CDS. Table V lists many of the different models of CDS presented in the literature.

TABLE V

CDS MODELS FOR SIC POWER MOSFETS Model Dep. First Author Year Formulation Type Variable Physics, Junction capacitance from depletion width and McNutt [89] 2007 Continuous drain body area Mudholkar Physics, 𝐷𝐷𝐷𝐷 Junction capacitance from movement of depletion 2014 𝑉𝑉 [39] Continuous boundary Shintani Physics, 𝐷𝐷𝐷𝐷 2018 𝑉𝑉 Junction capacitance-defined by charge [98] Continuous Semi-Physics, 𝐷𝐷𝐷𝐷 Riccio [81] 2018 𝑉𝑉 arctan Continuous Behavioral, 𝐷𝐷𝐷𝐷 Sochor [13] 2019 𝑉𝑉 Sum of tanh’s and exponentials Continuous Mukunoki Behavioral, 𝐷𝐷𝐷𝐷 2018 𝑉𝑉, LUT plus product of logistic and exponential [83] NA Mukunoki 2016, Physics, 𝐷𝐷𝐷𝐷 𝐺𝐺𝐺𝐺 𝑉𝑉 𝑉𝑉 LUT: capacitance [73], [80] 2018 LUT Endruschat Behavioral, 𝐷𝐷𝐷𝐷 2019 𝑉𝑉 LUT: capacitance [38] LUT Behavioral, 𝐷𝐷𝐷𝐷 Rizzo [114] 2020 𝑉𝑉 LUT: capacitance LUT Heckel Behavioral, 𝐷𝐷𝐷𝐷 2015 𝑉𝑉 LUT: charge [117] LUT 𝑉𝑉𝐷𝐷𝐷𝐷 Because of the physical differences of the domains in which charge accumulates for CDG

and CDS, physics-based models of CDS [39], [89], [98] arrive at substantially different equations

for CDS compared to those derived for CDG. However, behavioral models tend to use the same

functions, such as arctangent [81], hyperbolic tangent [13], exponential [13], [83], and logistic

[13], [83] functions for both. This is due to the similar shape of the two capacitance curves. LUT models of CDS are implemented similarly to LUT models of CDG.

In [83], Mukunoki presents a unique model of CDS. In addition to the typical dependence

on VDS, this model considers the dependence of CDS on VGS. Further, this paper demonstrates

experimentally that CDS increases as a function of VGS. While the dependence of CDS over VDS is

defined by a LUT, the additional increase in CDS over VGS is fit with a continuous function, and the two dependences are summed.

2.2.3. Gate to Source Capacitance

Because CGS has only a modest dependence on VDS [13], [81], a majority of the models presented in the literature for CGS use a static capacitance to represent this element [37], [39],

[79], [81], [89], [98], [110], [114], [117]. However, several models include the dependence of

CGS on VGS [83] or VDS [13]. Table VI documents the models of CGS identified in the literature that capture these dependencies.

TABLE VI

CGS MODELS FOR SIC POWER MOSFETS First Model Dep. Year Formulation Author Type Variable Behavioral, Duan [78] 2018 tanh centered on zero Continuous Physics, 𝐺𝐺𝐺𝐺 Sakairi [16] 2018 𝑉𝑉, Sum/product of tanh’s Continuous Behavior, 𝐷𝐷𝐷𝐷 𝐺𝐺𝐺𝐺 Sochor [13] 2019 𝑉𝑉 𝑉𝑉 Sum of tanh’s and exponentials Continuous Mukunoki 2016, Physics, 𝐷𝐷𝐷𝐷 𝑉𝑉 LUT: capacitance [80], [83] 2018 LUT Mukunoki Behavioral, 𝐺𝐺𝐺𝐺 2018 𝑉𝑉 LUT: capacitance [73] LUT Endruschat Behavioral, 𝐺𝐺𝐺𝐺 2019 𝑉𝑉 LUT: capacitance [38] LUT 𝑉𝑉𝐺𝐺𝐺𝐺 Multiple authors identify that CGS has a substantial dependence on VGS [16], [38], [78],

[73]. In [16], Sakairi et al. include both the modest dependence on VDS and the strong dependence on VGS in the presented model definition. As seen in Table VI, voltage-dependent models of CGS are usually defined either by a LUT [38], [73], [80], [83] or by using a combination of hyperbolic tangents [13], [16].

2.2.4. Implementing Voltage Dependent Capacitance in SPICE

In general, papers describing SiC MOSFET interelectrode capacitance models emphasize the equations used to define voltage-dependent capacitance, but the mechanisms chosen for implementation of these models are not usually explained. For clarity, this dissertation uses the nomenclature “interelectrode capacitance model” to discuss the mathematic description of capacitance in terms of voltage, and the term “implementation” to discuss the netlist selected for usage in SPICE.

In [119], Zeltser and Yaakov identify multiple possible implementations for voltage- dependent capacitance. Their work highlights the nonlinear relationship between charge and voltage in a voltage-dependent capacitance. Figure 2 shows a notional plot of charge vs. bias voltage for a MOSFET CRSS measurement. From the ( ) relationship, capacitance can be defined in two ways. First, if capacitance is defined by𝑄𝑄 the𝑣𝑣 ratio between total charge and applied voltage, the result is called total capacitance, CT. Measurements of capacitance which use gate charge, for example, result in CT. Alternatively, capacitance can be defined by the derivative of the charge vs. bias voltage plot. This formulation is called local capacitance, CD. Measurement methods using small signal analysis, such as curve tracer measurements, will result in CD. While these two definitions are identical for linear capacitors, the same cannot be said for nonlinear capacitors. Thus, caution is required when combining data from different methodologies.

dQ C = D dv Q(v) arge

Ch Q C = T v

Voltage Figure 2. Illustration of total and local capacitance adapted from [119]

CT is defined by equation (1).

( ) ( ) = (1) 𝑄𝑄 𝑣𝑣 𝐶𝐶𝑇𝑇 𝑣𝑣 The displacement current through a capacitor 𝑣𝑣defined via CT is determined by solving (1) for charge and differentiating with respect to time. The result, which is obtained by application of the product rule, is given by equation (2).

( ) ( ) = ( ) + (2) 𝑑𝑑𝑑𝑑 𝑑𝑑𝐶𝐶𝑇𝑇 𝑣𝑣 𝑖𝑖𝑐𝑐 𝑡𝑡 𝐶𝐶𝑇𝑇 𝑣𝑣 𝑣𝑣 CD is defined by equation (3). 𝑑𝑑𝑑𝑑 𝑑𝑑𝑑𝑑

( ) = (3) 𝑑𝑑𝑑𝑑 𝐶𝐶𝐷𝐷 𝑣𝑣 The displacement current through a capacitor𝑑𝑑 defined𝑑𝑑 via CD is determined by solving (3)

for and dividing both sides of the equation by . The result, which does not require

application𝑑𝑑𝑑𝑑 of the product rule, is given by equation𝑑𝑑𝑑𝑑 (4).

( ) = ( ) (4) 𝑑𝑑𝑑𝑑 𝑖𝑖𝑐𝑐 𝑡𝑡 𝐶𝐶𝐷𝐷 𝑣𝑣 This means that for CT implementations, the derivative𝑑𝑑𝑑𝑑 of the total capacitance function

plays a direct role in determining the capacitor current in the time domain. Critically, this leads

to many nonlinear definitions of capacitance that cannot be solved correctly in SPICE using CT

implementations. If CT is defined by a LUT, for example, SPICE incorrectly evaluates that the 28

capacitance is periodically zero due to discontinuities in the derivative. Because of the

nonlinearity of semiconductor interelectrode capacitances, the models defined in terms of CT are

not considered in this study.

At least five implementations for interelectrode capacitance have been shown for SiC

MOSFETs in the literature. The first is the nonlinear mapping implementation (NLM), shown in

Figure 3(a). This implementation uses a static capacitor in SPICE to perform differentiation and

maps its current via a capacitance function to create a voltage-dependent capacitance. This model

was identified in [119] and used to model CGS in [37]. The function fc describes the specific

equation (or LUT) used to define capacitance. This implementation is extended in [38] into the

NLM2, shown in Figure 3(b). The final capacitance-defined implementation, shown in Figure

3(c), is a simple derivative implementation (SDI), in which a behavioral current source

multiplies the capacitance function by the mathematic derivative [110], [119].

NLM1 NLM2 SDI1 SDI2 QDC n1 n1 n1 n1 n1

V(n3) I = fc(V(n1,n2))*I(V1) I = iaux* - 1 I = C0*fc(V(n1,n2)) I = ddt(fq(V(n1,n2))) Q = fq(x) ( Cx ) iaux *ddt(V(n1,n2)) n3 C x C BV1 x V V = V(n1,n2) 1 V=0 BV1 V = fc(V(n1,n2)) n n n2 n2 n2 2 (a) 2 (b) (c) (d) (e)

Figure 3. Five implementations of voltage-dependent capacitance suited for interelectrode capacitances, (a) nonlinear mapping implementation with external capacitor [37], [119], (a) nonlinear mapping implementation with in-line capacitor [38], (c) simple derivative implementation with capacitance definition [119], (d) simple derivative implementation with charge definition [94], (e) charge-defined capacitor implementation [117] In contrast to capacitance-defined implementations, multiple interelectrode capacitance

implementations use the charge-defined function (fq) [39], [94], [98], [117]. Such models can be implemented in SPICE through the SDI shown in Figure 3(d), which takes the derivative of the charge function directly [94]. Figure 3(e) shows that models defined in terms of charge can also

be directly implemented with a capacitor defined by variable charge [117]. This charge-defined

capacitor (QDC) is not a native SPICE feature [28], but an addition to SPICE within certain

programs such as LTspice [120].

2.3. SPICE Solver Parameters and Convergence

In this study, significant consideration is given to the relative computational cost of

various model elements. While the analysis developed from the specific comparisons can be

generalized, many of the specific results (such as the time it took “model A” to complete

“simulation B”) are contingent on the extremely specific simulation conditions used. Some

variables in this study, such as computational hardware or operating system, are chosen due to

availability or necessity. However, many simulation parameters can and should be carefully

controlled to produce self-consistent results. The computational analysis described in this

dissertation is conducted in LTspice, a graphical SPICE simulation tool available from Linear

Technologies. LTspice is commonly used for the modeling and design of power electronics. It is

noted that the run-time and convergence of any given model in LTspice is highly dependent on

the solver, integration method, and SPICE options selected.

In order to identify the solver parameters most appropriate for this analysis, a study of literature relevant to power electronics simulations in SPICE was conducted. These parameters play a key role in determining simulation convergence, and parameter values selected for this study were chosen for robust convergence in complex simulations. Additionally, this section provides a set of guidelines that can be followed sequentially in order to systematically improve the likelihood of convergence for power electronics simulations in LTspice. This guidance also includes a description of known accuracy trade-offs, where applicable.

For LTspice, one of the first parameters to adjust for improving convergence is the solver

implementation. LTspice includes two separate internal solvers: normal and alternate. The

alternate solver has reduced roundoff error (which improves internal accuracy) and will converge

for many cases that cause difficulty for the normal solver. Because the alternate solver simulates

at approximately half the speed of the normal solver [120], it should only be selected when

convergence is a concern.

Of the standard SPICE options, is highly relevant to power electronics simulations as it determines the minimum conductance𝑔𝑔𝑔𝑔 𝑔𝑔allowed𝑔𝑔 across nonlinear devices [28]. This parameter is critical for preventing floating nodes when semiconductor devices are turned off, for example [121]. The importance of often goes unnoticed due to the stepping phase executed during the DC analysis of𝑔𝑔𝑔𝑔 most𝑔𝑔𝑔𝑔 transient simulations. Increasing𝑔𝑔𝑔𝑔 𝑔𝑔𝑔𝑔 from the default

value (10 ) can improve convergence, but values of greater than 10𝑔𝑔𝑔𝑔𝑔𝑔𝑔𝑔 can also cause −12 −8 convergence issues [56]. There is also a clear accuracy 𝑔𝑔𝑔𝑔trade𝑔𝑔𝑔𝑔-off associated with adjusting .

It has been noted that if is large enough to improve convergence, it is also large enough𝑔𝑔𝑔𝑔 𝑔𝑔to𝑔𝑔

reduce accuracy [121]. 𝑔𝑔𝑔𝑔𝑔𝑔𝑔𝑔

The next step for most simulations is to increase the relative tolerance ( ) allowed

for error in respect to the simulated signal, which is the upper error limit allowed𝑟𝑟𝑟𝑟𝑟𝑟 for𝑟𝑟𝑟𝑟𝑟𝑟 the

computation of the Newton convergence criteria and time-step control algorithm [121]. This parameter can be increased from 0.1% (denoted 0.001 in the solver options) [28] up to 1%

(denoted 0.01 in the solver options). This adjustment can improve convergence and decrease simulation run-time dramatically in exchange for a minor loss of accuracy. This parameter can be returned to its default value when a more accurate solution is required. It is noted that

significantly large values of (above 1%) may lead to large transient errors which can in turn cause convergence issues𝑟𝑟𝑟𝑟𝑟𝑟 [56]𝑟𝑟𝑟𝑟𝑟𝑟.

Additionally, the gear integration method tends to be more numerically stable than the trapezoidal method [122] and is recommended in conjunction with increased values [56].

While the gear method is often recommended for power electronics simulations𝑟𝑟𝑟𝑟𝑟𝑟 due𝑟𝑟𝑟𝑟𝑟𝑟 to the possibility of high frequency ringing artificially introduced by the trapezoidal method, the gear method can artificially damp real circuit oscillations [123]. As an alternative to the gear method,

LTspice includes the modified trapezoidal method, which has its own proprietary method for reducing artificial oscillations. The modified trapezoidal method is reported to be both faster and more accurate than the gear method, although less stable [123]. Therefore, the gear method of integration should be considered when increased stability is called for at the expense of accuracy.

Another option for improving simulation convergence is to increase the iteration count limits used by the solver. This approach also lengthens the simulation run-time but can be helpful in achieving convergence for simulations which are borderline stable. The specific parameters that can be increased are the DC iteration count limit ( 1), the DC transfer curve iteration count limit ( 2), the transient time point iteration count limit𝑖𝑖𝑖𝑖𝑖𝑖 ( 4), and the source stepping iteration count 𝑖𝑖limit𝑖𝑖𝑖𝑖 ( 6) [120]. 𝑖𝑖𝑖𝑖𝑖𝑖

The absolute𝑖𝑖𝑖𝑖𝑖𝑖 current error tolerance ( ), absolute voltage error tolerance ( ), and absolute charge error tolerance ( )𝑎𝑎𝑎𝑎 parameters𝑠𝑠𝑡𝑡𝑡𝑡𝑡𝑡 also play an important role in 𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣 determining both simulation time and𝑐𝑐 ℎconvergence.𝑔𝑔𝑔𝑔𝑔𝑔𝑔𝑔 All three of these tolerance parameters can be increased to reduce simulation time and improve convergence performance at the cost of accuracy. Currents smaller than and voltages smaller than are ignored by the

SPICE solver in the selection of 𝑎𝑎𝑎𝑎time𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎 step values and determination𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣 of convergence [121]. It is

noted that the default values for these parameters in LTspice are optimized for analog and integrated circuit analysis (1 – 100 µA signals). For analysis of power electronics applications, these parameters should be set significantly higher than the default values. A rule of thumb for

and is to set these values six to eight orders of magnitude lower than the peak

𝑣𝑣voltage𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣 and𝑎𝑎𝑎𝑎 current𝑎𝑎𝑎𝑎𝑎𝑎𝑎𝑎 signals within the simulation, respectively [56], [121].

Another method to reduce the run-time of power electronics simulations is to analyze the circuit with a fixed timestep. Fixed timesteps are not natively supported in LTspice but this behavior can be approximated as follows. First, , which influences the generation of the next timestep, is set to a high value such as 25. This𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡 increases the solver’s initial timestep increment. Next, , which is the maximum allowed timestep, is fixed to a value between 1% and 10% of the switching𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡 period. This forces the simulator to use a nearly constant timestep and eliminates calculations associated with the cyclical change between short periods of large-signal events and long periods of small-signal events [56].

Finally, solving the initial operating point at the beginning of transient simulations can play a critical role in determining convergence behavior. This step of the simulation can be bypassed by specifying the option in the LTspice transient simulation command. Disabling the initial operating point solution𝑢𝑢𝑢𝑢𝑢𝑢 will improve convergence behavior for many types of applications. Unfortunately, selecting this option can also create unexpected behavior. For example, all nodes that are not explicitly initialized by an initial condition statement will be initialized to zero volts. If skipping the initial operating point solution is not practical, an alternative approach is to progressively add high-value parallel resistors until all nodes have a

DC path to simulation ground (either directly or indirectly). This approach can also improve simulation convergence by facilitating the identification of the initial operating point.

The preceding guidance for improving simulation convergence is summarized below in

the form of a convergence troubleshooting checklist:

1. Employ the alternate solver (LTspice only).

2. Increase the minimum conductance: Increase from 10 to 10 (up to −12 −9 10 ). 𝑔𝑔𝑔𝑔𝑔𝑔𝑔𝑔 −8 3. Increase acceptable relative error: Increase from 0.001 to 0.005 (up to

0.01) 𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟𝑟

4. Try the gear integration method.

5. Increase allowed number of iterations:

• 1: DC iteration count limit (default 100)

• 𝑖𝑖𝑖𝑖𝑖𝑖2: DC transfer curve limit (default 10)

• 𝑖𝑖𝑖𝑖𝑖𝑖4: Transient time point limit (default 10)

• 𝑖𝑖𝑖𝑖𝑖𝑖6: Source stepping limit (default 25)

6. 𝑖𝑖Reduce𝑖𝑖𝑖𝑖 the absolute current and voltage accuracy tolerance: Increase and

to between 6 and 8 orders of magnitude below the maximum expected𝑎𝑎𝑎𝑎𝑎𝑎𝑡𝑡𝑡𝑡𝑡𝑡

current𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣𝑣 and voltage, respectively.

7. Attempt fixed timestep simulation: Set to 25 and to 1% of the

switching frequency. 𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡 𝑡𝑡𝑡𝑡𝑡𝑡𝑡𝑡

8. Skip solution for initial condition ( ).

In general, it is recommended that these steps𝑢𝑢𝑢𝑢𝑢𝑢 are conducted in the specified order and that each step include the changes made in prior steps. However, steps seven and eight address independent issues and do not necessarily need to be combined with other steps. Of course, none of these recommendations will correct for an error in the application circuit. Minor netlist

mistakes can sometimes lead to convergence problems that are difficult to diagnose. In these cases, a careful review of the SPICE error logs often reveals the origin of the problem. Other application characteristics that can lead to convergence problems include loops of voltage sources, series current sources, unrealistic parasitics, or poorly referenced nodes.

CHAPTER 3:

MODELING MOSFET STATIC BEHAVIOR

3.1. Introduction

The first domain of modeling to be analyzed is the conduction branch, which describes the static characteristics, or steady state behavior, of the MOSFET. Specifically, this conduction branch describes the dependence of channel current on gate-source voltage, drain-source voltage, and junction temperature [16]. These characteristics are critical for predicting conduction losses

[86]. As the conduction branch is a necessary, though not sufficient, condition for time domain evaluations, it is considered first such that it forms the foundation upon which the dynamic models considered in chapter 4 will be built.

Of the models identified in chapter 2, there are many excellent candidates for inclusion in a trade study of available SiC MOSFET models. However, only a subset of these models could be studied in this work. Accessibility of the models was a primary consideration, as not all models are published with sufficient detail to be reproduced. Another goal of the proposed study is to understand the tradeoffs between behavioral and physics-based models, which requires selection of at least one relevant model of each type. It is acknowledged that different types of models are suited for different purposes, and that designers should consider their modeling goals during model selection rather than focusing exclusively on quantitative metrics. Nevertheless, it is beneficial for practitioners to understand the computational and accuracy implications of model type selection.

Behavioral models may be the best choice for general application development due to

their computational advantages. However, there can be subtle challenges with this type of model.

For example, since behavioral models are usually defined and calibrated within the device safe

operating area (SOA), they may produce inaccurate and misleading results during fault

conditions such as avalanche, over-current, or gate stress. While additional behavior can be

defined to capture fault conditions [81], each addition requires additional modeling effort to

capture and also increases model complexity.

In addition, physics models can contain built-in dependence on process parameters.

Studies involving variation in these parameters are of interest for device designers as they have

important system performance implications. For example, in a topology with multiple devices in

parallel, current sharing will be heavily influenced by small differences in RDS(ON) or VTH

between parallel devices. Because physics models can include process parameter dependencies,

known statistical variance in these parameters can be included in the composition of the model to

determine the expected impact of such parameters on the resulting variance of RDS(ON) or VTH

values [36]. Such a correlation is not practical to perform using behavioral models. Overall, the

required features and appropriate metrics for models should be considered in light of their

intended usage. The compact models selected for this study were chosen to represent a variety of

features, implementation methods, and design goals.

The first model selected, referred to as the semi-physics model throughout this discussion, was presented by Sun et al. in [107]. It is a classical physics model that is adapted into a semi-physics model through the addition of auxiliary behavioral components. This is a common approach in the literature [77]–[79], [101], [107], [110], [112], [124], [125]. The model core used in [107] is the Level 1 model. The Level 1 model does not capture the soft saturation

characteristics of long channel devices [126], which is common among SiC MOSFETs.

However, the Level 1 model offers substantially better run-time performance than alternative

semi-physics models such as the Level 3 model [103]. The authors improve upon the conduction

behavior of the Level 1 model through three additional thermal elements: a threshold voltage

(VTH) shift, variable drain resistance (RDS), and current offset. Additionally, they use a standard

diode model for third quadrant characterization.

The second model selected, referred to as the non-segmented model throughout this

discussion, was presented by Li et al. in [37]. The non-segmented model is one of the most

recent behavioral models published for describing the SiC MOSFET. The design of this model

prioritizes run-time performance and convergence behavior, so this model is especially suitable

for application simulations. The conduction branch of the non-segmented model is derived from

a description of the transfer characteristic, originally presented by Angelov et al. [127],

multiplied by a VDS-dependent scaling equation. The authors stress the importance of using

continuous equations to describe the static characteristics of the conduction branch as it

transitions through cutoff, linear, and saturation regions. They claim that this continuous

definition is optimal for more complex circuit simulations.

The third model selected, referred to as the modified Curtice model throughout this

discussion, was presented by Endruschat et al. in [38]. This model is also one of the most recent behavioral models published in the literature, and its design prioritizes run-time performance and convergence behavior. The modified Curtice model is primarily designed for the GaN HEMT but is also described as a universal FET model. In [38], the authors support this claim by providing an example fitting of this model to the characteristics of a SiC MOSFET. The modified Curtice model uses parameter lookup tables defined at discrete operating conditions in order to capture

device behavior. In order to determine the table values, the output equation is independently fit at

each VGS bias condition represented in the forward curves. This streamlines the extraction

process but does not guarantee the continuity achieved by the global approach of the non-

segmented model. Therefore, each behavioral model is the result of fundamentally different

assumptions.

The fourth and final model selected, referred to as the physics model throughout this

discussion, was presented by Hossain et al. in [94]. The physics model was adapted for LTspice from Mudholkar’s Saber model presented in [39]. This model captures soft saturation, variable

capacitance (CV), temperature dependence, and self-heating effects. Additionally, it follows a simple parameter extraction sequence and avoids the need for proprietary process details by numerically fitting parameters such as base doping concentration, active area, and gate-drain overlap active area. The CV characteristics are modeled independently from the conduction characteristics and therefore can be fit separately. This independence was a key motivation in selecting this specific physics model as it allowed isolation of the conduction branch for this study. An overview of the models selected for this study is given in Table VII.

TABLE VII MODELS SELECTED FOR TRADE STUDY Description of First Author Model Title Year Conduction Model Sun [107] Semi-Physics 2014 Level 1 model with ancillary features Behavioral current source Li [37] Non-Segmented 2019 with continuous definitions Behavioral current source Endruschat [38] Modified Curtice 2019 with parameter lookup tables Physically accurate description Hossain [94] Physics 2018 suitable for transient simulations

In this paper, several metrics are used to evaluate the suitability of each model’s

conduction branch for converter simulations. First, the computational difficulty of fitting each

model to empirical data is considered. Second, the RMS error of the simulated forward and

transfer curves is used to quantify the accuracy of conduction predictions. Finally, the relative run-time performance of each model is evaluated through a detailed trade study.

3.2. STATIC DOMAIN MODEL PERFORMANCE

3.2.1. Fit Approaches and Challenges

In this section, the process of tuning each model to a common set of static characterization data is described. The static characterization data utilized for this purpose was obtained by the authors through measurement of a 1.2 kV, 25 mΩ SiC MOSFET sample (Cree

C2M0025120D) [128]. While the same experimental data was used for tuning each model, a unique methodology for fitting each model is required due to their inherent differences. One of the primary strategies used to fit these models is global optimization (GO). GOs minimize a particular objective (such as RMS error of the forward curves) while evaluating various parameter sets. The method for determining the next parameter set can vary drastically between approaches (such as the genetic algorithm or particle swarm). In general, GOs are slow to converge but have the advantage that they are resistant to selecting local minima. Multi-objective

GOs, which create a Pareto optimal front, were not used in this work due to their high computational cost. The other class of algorithms employed in this work are from MATLAB’s curve fitting toolbox. These algorithms minimize error between a predictor function and a two- dimensional dataset, rather than a single objective. While much faster than GOs, these algorithms are likely to select local minima. Finally, some parameters were derived analytically from the experimental data.

The Level 1 core of the semi-physics model cannot reliably be fit by simple algorithms because it has a relatively small number of interlocked parameters which determine its output over all regions with many local minima. Thus, a global optimization routine is used to fit the

model to the forward and transfer data individually. The solver iterates between each

characteristic, slowly approaching a parameter set which suitably predicts both. The preferred

approach for fitting this type of model is to establish process parameters, such as channel length,

from the device design. However, this proprietary information is unknown for the device under

consideration. Instead, several values from a reasonable range were used as a starting point for

tuning the remaining parameters. After tuning, the model variant with the lowest computed error

was selected. For this model, elevated temperature behavior is represented by a VTH shift, RDS

increase, and current offset. These parameters are independent of the Level 1 core and can be

calculated from the experimental data.

A distinct advantage of the modified Curtice model is the simple process used to fit its

parameters to experimental data. The characteristic conduction equation is independently curve- fit to each series of the forward data. The resulting parameters are then stored in a lookup table which SPICE linearly interpolates. Despite the simple tuning process, the modified Curtice model has several challenges. First, because the model is not tuned to the transfer data, the forward curves must have a small step between VGS values to achieve an accurate fit, which limits the possibility of using datasheet curves. Another challenge is that the characteristic conduction equation has many degrees of freedom and can easily become trapped in local minima, especially if the forward conduction data does not extend into the saturation region. For

1.2 kV SiC MOSFETs, saturation current at high VGS is often three times the current rating of the

device. Pulsed curve tracer measurements at these operating conditions can suffer from

inaccuracies due to device self-heating. Because the experimental data used in this study was

limited to 100A, the modified Curtice model required additional manual tuning above VGS values

of 10 V. The elevated temperature features of the modified Curtice model are implemented with

a VTH offset, an RDS increase, and two parameter shifts within the condition equation. For this

study, the necessary VTH and RDS changes were calculated from the experimental data while the parameter shifts were manually tuned.

The non-segmented model is first fit to the transfer data at low VDS bias (3 V was chosen

in this work). Next, a scaling equation adjusts the transfer characteristic across VDS. While the

original authors [37] used a global optimizer to fit the scaling equation, this is a computationally

intensive process. Leveraging the tuning framework developed for the modified Curtice model,

the scaling equation was instead fit independently at each VDS value. The resulting parameter values were then fit with a continuous equation to match the original implementation. Altering the original model to use a different equation is a necessary step for using the non-segmented model. For users without access to the specialized modeling software used by the authors of the original manuscript, this approach is faster and provides more accurate results than a globally optimized equation. The thermal model requires global optimization due to the universal influence of shifting and scaling VGS and VDS in the calculation of drain current.

Unlike the other models, which were tuned using MATLAB’s curve fitting toolbox, the

physics model was tuned in IC-CAP with a combination of manual and automated steps. The

manual tuning steps are conducted in order to identify parameter boundaries and avoid local

minima. The physics model is tuned sequentially by first fitting threshold and transconductance

parameters from the transfer characteristic data, followed by fitting the remaining conduction

parameters to forward characteristic data. While this process requires fewer function evaluations

than tuning the semi-physics model, it is nevertheless more challenging than tuning either of the

two behavioral models. One benefit of the physics model tuning process is that it requires

substantially less experimental data than tuning of the behavioral models.

There is significant variance in the computational requirements of tuning the four models

considered in this study. If sufficient experimental data is available, the modified Curtice model

is the least computationally expensive to tune overall. Tuning the non-segmented model at 25 °C

with the proposed technique is also extremely efficient. However, tuning the thermal parameters

of the non-segmented model is very expensive since it requires global optimization. The

complexity of tuning the physics model is somewhere in the middle of the other models. The

semi-physics model is the most computationally intensive model to fit as it requires global optimization for all parameters.

3.2.1. Fit Performance Comparison

In Figure 4, the simulated conduction behavior at 25 °C is overlaid with the experimental data for each of the four models. The experimental data was collected using a Keithley

Semiconductor Characterization System (SCS). Pulse time was set to 300 µs with the sampling window centered at 150 µs. The sampling window was adjusted to 50 µs for operating conditions greater than 10 V and 50 A to minimize inaccuracy due to self-heating at higher power levels.

These sampling windows were identified and validated using an oscilloscope which monitored the experiment. It is noted that the presented data is a subset of the collected data, which was selected for clarity of comparison. The full dataset contains twenty-five VGS operating conditions

for the forward curves and fourteen VDS operating conditions for the transfer curves. The full

dataset is used for the fitting and evaluation of all models described in this manuscript.

25°C, Forward, Semi-Physics 25°C, Transfer, Semi-Physics 150 Forward 150 Transfer

100 100 [A] [A] D D - Physics I I 50 50 Semi

0 0 0 5 10 15 0 5 10 15 20 V [V] V [V] DS GS 25°C, Forward, Non-Segmented 25°C, Transfer, Non-Segmented 150 Forward 150 Transfer

100 100 [A] [A] D D I I

- Segmented 50 50 Non

0 0 0 5 10 15 0 5 10 15 20 V [V] V [V] DS GS 25°C, Forward, Modified Curtice 25°C, Transfer, Modified Curtice 150 Forward 150 Transfer

100 100 [A] [A] D D I I 50 50 Modified Curtice

0 0 0 5 10 15 0 5 10 15 20 V [V] V [V] DS GS 25°C, Forward, Physics 25°C, Transfer, Physics 150 Forward 150 Transfer

100 100 [A] [A] D D I I

Physics 50 50

0 0 0 5 10 15 0 5 10 15 20 V [V] V [V] DS GS

VGS = 0 V VGS = 5 V Simulation VDS = 0 V VDS = 2 V VGS = 7.5 V VGS = 10 V V = 15 V V = 20 V Experiment V = 4 V V = 15 V GS GS DS DS Figure 4. Static domain model overlay at 25 °C

The semi-physics model predicts hard saturation at higher currents, whereas the

experimental data demonstrates soft saturation. This discrepancy reveals the primary limitation

of the Level 1 conduction model and significantly penalizes the model’s fidelity to SiC MOSFET

behavior at high VDS. The non-segmented model has the most accurate agreement for both the forward and transfer characteristics at 25 °C. The modified Curtice predicts the forward characteristics precisely but models the transfer characteristics somewhat less accurately. The transfer accuracy of this model could be improved by reducing the size of VGS step for the

forward measurement to less than 1 V. Finally, while slightly less accurate than the behavioral

models, the physics model also predicts the forward and transfer characteristics accurately.

The modified Curtice model’s predicted transfer characteristics demonstrate several

unexpected features. First, the predicted transfer curve at V = 2 shows an unusual deviation

DS from the experimental data between V = 8 and V = 10 . This𝑉𝑉 result indicates that the

GS GS parameters for V = 9 fit the forward curve𝑉𝑉 poorly at low values𝑉𝑉 of VDS. This corresponds to

GS the tuning algorithm accurately𝑉𝑉 fitting the saturation region and poorly fitting the linear region.

There is likely a different set of parameters that could resolve this discrepancy, but the flexibility

of the conduction equation combined with the soft saturation of SiC MOSFET devices makes

this problem challenging to eliminate systematically. The other unexpected feature of the transfer

prediction for the modified Curtice model is the piecewise linear fit at V 4 . This is a result

DS of the manual tuning performed due to the limited current range of the experimental≥ 𝑉𝑉 data. This

problem would likely be resolved with the availability of additional experimental data.

Visual overlays such as those shown in Figure 1 are often the only validation presented

for conduction models in the literature. In order to add quantitative analysis for both validation

and comparison, specific accuracy metrics are required. In this study, RMS error is selected as

the principal figure of merit for evaluating the accuracy of each model under consideration. This

figure of merit is calculated from equation (5):

= , , (5) 𝑛𝑛 2 Σ𝑖𝑖=1�𝑦𝑦𝑒𝑒𝑒𝑒𝑒𝑒 𝑖𝑖 − 𝑦𝑦𝑠𝑠𝑠𝑠𝑠𝑠 𝑖𝑖� where n is𝐸𝐸𝑅𝑅𝑅𝑅 the𝑅𝑅 number� of data points, is the value measured in experiment, and is the 𝑛𝑛 𝑒𝑒𝑒𝑒𝑒𝑒 𝑠𝑠𝑠𝑠𝑠𝑠 value predicted by simulation. 𝑦𝑦 𝑦𝑦

Figure 5 shows the RMS error of each considered model at three temperatures: 25 °C,

100 °C, and 150 °C. One RMS error value is computed for each curve of the forward and

transfer characteristics. Thus, forward curve error is plotted as a function of VGS and transfer

curve error is plotted as a function of VDS. Additionally, RMS error values are computed for all

available characterization data, including the curves omitted from Figure 4.

25 °C 100 °C 150 °C 15 15 15

10 10 10

5 5 5 RMS Error [A] Forward Curves 0 0 0 0 5 10 15 20 0 5 10 15 20 0 5 10 15 20 V [V] V [V] V [V] GS GS GS 15 15 15

10 10 10

5 5 5 RMS Error [A] Transfer Curves Transfer 0 0 0 0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35 0 5 10 15 20 25 30 35 V [V] V [V] V [V] DS DS DS

Semi-Physics Non-Segmented Modified Curtice Physics

Figure 5. RMS error at each temperature Analysis of the forward error reveals that the semi-physics model demonstrates

significant error near VGS of 8 V, which is a result of the hard saturation behavior predicted by

the model. This trend is also observed in the transfer data above 15 V. As anticipated from the

visual overlay, the non-segmented model demonstrates the lowest error at 25 C and is closely

followed by the modified Curtice model. The physics model has a slight increase in error at high

VGS due to a modest mismatch in predicted RDS(on). The RMS error of transfer curves is relatively

high for all models at values of VDS greater than 10 V. The semi-physics model exhibits the highest error in this region due to its incorrect prediction of hard saturation behavior.

Additionally, Figure 5 shows that the approach used by the non-segmented model for elevated temperature is significantly outperformed by the simpler thermal model used by the modified

Curtice model. The thermal model of non-segmented model does not accurately predict the transfer curves for multiple VDS bias conditions because the increased channel resistance at high

temperature is modeled by shifting and scaling VDS. While this approach is able to predict the

transfer characteristics very accurately at a single VDS bias condition, fitting multiple bias

conditions simultaneously is not possible. The physics model, which is fit at all temperatures

simultaneously, performs reasonably well at all temperatures. All the models demonstrate

relatively high error for V = 8 at 150°C. Overall, the modified Curtice is the most accurate

GS model for predicting the conduction𝑉𝑉 behavior of the considered SiC MOSFET at elevated

temperature.

Figure 6 presents the mean RMS error for each of the models at each temperature,

calculated from the results shown in Figure 5 using (5). This representation confirms that the

RMS error of the non-segmented is lowest at 25 °C but increases substantially at elevated

temperature. Additionally, the Curtice model exhibits only a modest increase in RMS error with

temperature. Finally, the semi-physics model demonstrates the highest average error for all

considered conditions.

Equivalent RMS Error Forward Transfer Mean 6 Forward Transfer Mean

5 Semi-Physics [ A ] 4 Non-Segmented 3 Modified Curtice 2 RMS Error [A]

RMS Error Error RMS Physics 1

25 °C 100 °C 150 °C 25 °C 100 °C 150 °C Forward Transfer

Figure 6. Equivalent RMS error for (a) forward, (b) transfer, and (c) mean over temperature Figure 6 also presents a comparison of the cumulative mean RMS error for the forward

and transfer curves of the models, the values for which are computed from the results of the first

two subplots of Figure 6 using (5). This comparison can be used to rank the models by accuracy.

The modified Curtice model demonstrates the lowest RMS error overall, followed by the non- segmented model due to its significantly increased error at elevated temperature. The physics model has slightly higher error than the non-segmented model, due to its more accurate prediction of soft-saturation, but significantly outperforms the semi-physics model, which

produces the highest RMS error.

3.3. Computational Trade Study

3.3.1. Overview of Simulation Study

Accuracy is a necessary but insufficient condition for establishing the suitability of a model for application simulations. Critically, models that do not converge, or that are unreasonably slow to do so, are of minimal benefit to application design. Therefore, a study was designed to quantitatively evaluate the relative computational performance of the considered models. MATLAB was used to build the simulations from templates, add circuit parameters, and

execute LTspice via batch commands, as originally demonstrated in [125]. Details on the framework developed to conduct this study are given in appendix A2. More than 500,000 unique

LTspice simulations were run in the development of this dissertation. All the models considered in this chapter were modified to use an identical interelectrode capacitance model, implemented with two behavioral current sources (for CDS and CGD) and a static capacitor for CGS. It is noted that the dynamic behavior of the models under study will not be addressed until chapter 4, but this alteration is required for a normalized comparison of the static conduction behavior of these models. To contextualize these results, the model provided by the SiC MOSFET device manufacturer was also included in the study [128].

Many commercial, free, and open source simulator platforms have been developed for

SPICE. Selection of a platform is a necessary limitation of this analysis, but while the specific results of this paper will be contextualized within the LTspice platform, the relative performance of these models is likely to be similar in other simulators. The accessibility of LTspice, as well as its popularity for power electronics applications, make it an excellent choice for this analysis.

Readers who wish to leverage this framework will also be able to conduct analysis in LTspice for direct comparisons to these results.

Three application simulations were developed for this study. First, a double-pulse test

(DPT) circuit, shown in Figure 7, was included for its simplicity and ubiquity. The DPT

simulation was evaluated over a 40 µs transient duration. A notable feature of the DPT

simulation in this study is the use of a charged capacitor bank rather than an ideal voltage source

for the power supply. This setup reflects a common implementation of DPT testbed hardware but

is more computationally complex than using an ideal voltage source.

Figure 7. Schematic template, double pulse test (DPT) Second, a buck converter, shown in Figure 8, was included to present a simple continuous converter simulation. Because this simulation has similar complexity to the DPT example but much longer transient duration (500 µs), it minimizes the influence of the operating point solution and startup.

Figure 8. Schematic template, buck converter Third, the single-phase neutral-point-clamped (NPC) inverter, shown in Figure 9, was included. The NPC inverter is the most complex simulation example considered in this study both because it is a multi-level topology and because it operates over the longest transient

duration (1 ms). In addition, the NPC simulation is likely of the most interest to perspective application designers because it is comparable in complexity to many practical topologies. The

NPC inverter simulation example demonstrated here was developed during the design of the

SiC-based NPC prototype converter described in [129]. For each simulation evaluation, the

circuit’s operating conditions and specific parasitic element values were randomized between

40% and 160% of the nominal values shown on their respective schematics.

Figure 9. Schematic template, neutral point clamped (NPC) inverter In the context of modular multi-level converters and similar practical topologies [130], the NPC example shown here is still a relatively modest simulation. Rather than developing additional unique converter templates, the multichip power module (MCPM) component shown in these examples was used as a modular building block. By changing the number of paralleled

SiC MOSFET die at each switch position within this package, the complexity of the simulation can be granularly controlled, and larger converter topologies can be readily synthesized. Figure

10 shows an example design of the MCPM component with two paralleled die per switch position. During this study, modules were simulated with 1, 2, 4, 8, 16, and 32 paralleled die per switch position. Each parallel device was fitted with individual circuit parasitics, as shown by the

“Parallel Device” in Figure 10.

Figure 10. MCPM package model In order to directly study the computational impact of combining SiC MOSFET devices in series, an additional module type was introduced: the multi-level MCPM. Figure 11 shows an example design of the multi-level MCPM with two series die per switch position. During this study, multi-level modules were simulated with 2, 4, 8, 16, and 32 series-connected die per switch position. Due to the computational complexity of this configuration, of the application simulations, only a one was analyzed during this phase of study. Thus, these simulations utilize the DPT application circuit with a 40 µs transient duration. While these simulations do not directly represent a specific converter design, they provide a simple and effective mechanism for evaluating the performance of simulating an arbitrary number of converter levels.

Figure 11. Multi-level MPCM package model Because of their strong influence on run-time, the simulation environment settings are

critical. While LTspice users often leave the solver, integration method, and SPICE options set to

their default values, these settings are rarely optimal for simulation run-time and convergence, especially for power electronics. Table VIII shows the SPICE configuration settings used in this simulation study, many of which were recommended for simulations utilizing the SiC MOSFET

manufacturer model [131]. These selections play a critical role in determining the simulation

time and were maintained for all models. It should be noted that these specific parameter values

favor speed and convergence over accuracy and may not be optimal for all simulations, as

discussed in chapter 2. These options can be configured in the control panel within LTspice or

via a .option directive in the schematic. The maximum thread count specified in Table VIII is

eight, which is the maximum for the CPU utilized in this study (Intel i7-7700k). Finally, the

version of LTspice used in this analysis is Version XVII, update 11/06/2019.

TABLE VIII SPICE SOLVER PARAMETERS Class Variable Value Solver Normal Max Threads 8 Matrix Compiler Object Code Engine Thread Priority High and Integration Method Gear Solver Noopiter True Skip gmin Stepping False gmin 10 abstol 10 −9 A Simulation chgtol 10 −6 c Tolerance reltol 10−12 % vntol 10−3 V itl1 1000−3 itl2 1000 Iteration Limits itl4 1000 itl6 1000

3.3.2. Results of Simulation Study

Figure 12 shows the run-time performance for each model described in Table VII and

each topology shown in Figure 7. The y-axis shows the average elapsed time per simulation while the x-axis shows the number of devices per switch position. For accuracy and consistency, the run-time for each simulation was extracted from the LTspice log file. Since each configuration exhibits run-to-run variance (even when limiting background computing tasks),

each value shown is this figure represents the average of at least one hundred LTspice

simulations. It is noted that a few points are omitted from the manufacturer model results due to

convergence failures in these simulations, even with the relaxed tolerances described in Table

VIII.

Double-Pulse Test Buck Converter Neutral-Point-Clamped Inverter Multi-Level DPT 10 4 1 Hour

10 3

10 2 1 Minute

10 1

Run-Time [Seconds] 1 Second 10 0

10 -1 1 2 4 8 16 32 1 2 4 8 16 32 1 2 4 8 16 32 1 2 4 8 16 32 Parallel Die per Switch Parallel Die per Switch Parallel Die per Switch Series Die per Switch Semi-Physics Non-Segmented Modified Curtice Physics Manufacturer Figure 12. Mean Run-time The first three simulations of Figure 12 (DPT, Buck, and NPC) clearly demonstrate the

impact of increasing application complexity. As converter models increase in simulation time,

number of devices, and topology levels, the corresponding run-time changes from under a

second to over an hour. This demonstrates the critical role of simulation optimization in

determining model usability and the motivation for identifying computational tradeoffs in model

design. Designers should attempt to identify the level of complexity for the application topology

under consideration when selecting an appropriate MOSFET model.

Additionally, a general trend emerges within the context of a given application example.

On average, the marginal computation cost for adding parallel die is slightly greater than 1:1. In

other words, doubling the number of paralleled devices more than doubles the simulation run-

time. While this relationship is not perfectly consistent (especially in the difference of 1 and 2

devices), it is generally applicable across the models, number of devices, and applications

considered here. This relationship, however, is closer to 1:4 for the multi-level DPT application.

Thus, while doubling the number of devices in parallel approximately doubles the run-time,

doubling the number of devices in series increases the runtime by a factor of 8. This is because

the multi-level design increases the number of interdependent nodes, and SPICE simulations are

fundamentally solved through nodal analysis [32]. Thus, simulation complexity increases more

quickly with the number of series devices than the number parallel devices.

Analyzing particular configurations within Figure 12 provides additional insight into

computational complexity trends. For example, the single-die DPT results reveal why this setup

is insufficient for analysis of model run-time. For this configuration, the fastest model takes approximately 0.25 seconds to complete the simulation on average while the slowest model takes

0.78 seconds; such a difference is unlikely to be noticed by the user, even though there are significant performance differences between these models. Analysis of the buck converter configuration begins to reveal these differences. In this configuration, the fastest model takes approximately 2.5 seconds to complete, while the slowest model takes 8 seconds. Further, if the buck converter is simulated with the 32 transistor MCPM model, the semi-physics model completes the simulation in 46 seconds while the manufacturer model takes longer than 8 minutes. Evaluating the single die configuration of the NPC inverter reveals that employing a behavioral model can reduce simulation run-time by 70% compared to the manufacturer model.

A result that may be unexpected is that the semi-physics model is marginally faster than the behavioral models, despite using a more mathematically complex description. This is likely the result of internal optimization for the Level 1 MOSFET model within SPICE, which is not applicable when utilizing arbitrary sources. This improvement, although modest, is repeatable and generally consistent across the cases considered here. The non-segmented model follows closely in second place with a run-time penalty of 5% over the semi-physics model on average. It has a slight advantage in run-time, however, over the third-place modified Curtice model, which on average incurs a 28% run-time increase over the semi-physics model. The run-time difference between the non-segmented and modified Curtice models indicates that the focus on model

flexibility comes at a modest penalty compared to focusing on model continuity. Finally, while the physics model is slower than the simplified transistor models, it outperforms the manufacturer model by a wide margin.

Figure 13 shows a subset of the run-time results for the 32 die per switch-position configuration of each example application. This comparison better illustrates the relative performance specific to each model. For the NPC with 32 die, the run-time difference is 90 minutes for the manufacturer model versus 11 minutes and 20 seconds for the semi-physics model.

Mean Run-Time: 32 Die Per Position 4 10 1 Hour

10 3 Semi-Physics

2 Non-Segmented 10 1 Minute Modified Curtice 1 10 Physics 1 Second Run-Time [Seconds] 10 0 Manufacturer

-1 10 DPT Buck NPC ML DPT

Figure 13. Mean run-time for each model and application with 32 die per switch position Figure 14 shows the run-time (normalized by total SPICE iterations) versus matrix size for the NPC converter. In this analysis, the runtime increases with matrix size as ( . ) to 1 28 ( . ). This range is in reasonable agreement with previous studies on the computational𝒪𝒪 𝑁𝑁 1 67 complexity𝒪𝒪 𝑁𝑁 of SPICE solvers. For example, Krapre reports that simulation run-time increases with circuit size as ( . ) for sequential matrix operations, which can be driven as low as 1 2 ( . ) for optimized𝒪𝒪 𝑁𝑁 parallel computing architectures [132]. However, scaling factor versus 0 7 circuit𝒪𝒪 𝑁𝑁 size is best approximated by number of equations [133], which is not linearly related to

matrix size. Since LTspice utilizes a proprietary parallel processing package [120], it is expected

that the complexity dependence on circuit size falls between ( . ) and ( . ), while the 0 7 1 2 complexity dependence on matrix size is slightly higher. 𝒪𝒪 𝑁𝑁 𝒪𝒪 𝑁𝑁

-1 10

-2 Semi-Physics N^1.42 10 Non- Segmented N^1.67 -3 10 Modified Curtice N^1.57

-4 10 Physics N^1.61

Run-Time/Iteration [Seconds] Manufacturer N^1.28 -5 10 2 4 10 10 3 10 Matrix Size Figure 14. NPC Simulation complexity, run-time versus matrix size 3.4. Convergence Study

Unlike simulation run-time, convergence behavior does not scale predictably with the complexity of the model. This is in part because convergence is highly dependent on the SPICE simulation options as well as the circuit topology. It would be convenient to develop a simplified metric to quantitatively rank the relative convergence of the models considered in this study.

However, such a metric is unlikely to generalize well. This metric would reflect the specific topology and simulation settings applied rather than providing much insight into the relative convergence of the models under consideration. Thus, a case study was conducted to evaluate trends in convergence behavior among the considered models. The convergence behavior of the manufacturer model has been previously studied in the literature [37]. This model was therefore utilized as a starting point for identifying regions of convergence. Table IX presents the convergence behavior of the manufacturer SiC MOSFET model in the multi-level DPT

application circuit for various SPICE options. The multi-level DPT application was selected for

this study because it is an especially challenging simulation. For the purposes of this study, a

simulation run was considered a convergence failure if one of the following conditions was met:

(1) a convergence error was indicated by the solver, (2) the simulation stopped before the final

time sample, or (3) if the mean value of a specific reference waveform was more than one order

of magnitude different than its known value. In the authors’ experience, any one of these

conditions is likely to be met when LTspice encounters convergence difficulty in solving a

complex converter simulation.

TABLE IX CONVERGENCE STUDY, MULTI-LEVEL DPT Skip Initial Operating Die Per Switch Default SPICE Options Shown Point Solution Position Options in Table II (& Idealized Capacitor Bank) Single Convergent Convergent Convergent 2 Failure Convergent Convergent 4 Failure Convergent Convergent 8 Failure Marginal1 Convergent 16 Failure Failure Convergent 32 Failure Failure Convergent 1. Marginal Success: only convergent for DC operating points less than 10% rated voltage

Table IX indicates that, when using the default SPICE options, the manufacturer model cannot solve any of the multi-level DPT simulations. It is noted that the single-die DPT

simulation is a traditional (non-multi-level) DPT. Altering the SPICE options according to the

values recommended in Table VIII leads to a significant improvement in convergence behavior,

but the model still does not converge in all cases. However, when skipping the initial operating

point solution, LTspice can correctly solve any of the multi-level DPT simulations with either

option set. It is noted that the SPICE options do not substantially influence convergence behavior

when skipping the initial operating point solution. However, the options do have a significant

impact on simulation run-time. For example, the 32 die-per-switch-position DPT configuration requires 37 minutes to solve with the default options, but only 20 seconds to solve using the options shown in Table II. 59

The significant improvement in convergence behavior when skipping the initial operating

point solution is related to the complexity of solving the DC bias conditions of this circuit.

Combining transistor models in series creates many nodes with interdependent DC bias

conditions. The multiple behavioral sources and conditional statements in the manufacturer

model lead to a complex system matrix for the initial operating point. In general, there are a wide

range of circuit topologies that have challenging DC operating point solutions; where viable,

bypassing the DC solution can significantly improve convergence behavior.

This case study illustrates that the convergence behavior of a transistor model is highly dependent on the application circuit as well as the solver options employed. The multi-level application circuit studied in this section poses a particular challenge for the LTspice solver.

However, in the authors’ experience, less complex circuits often exhibit similar convergence failures with certain combinations of models and simulation options. For example, convergence challenges have been reported for simulation of a full-bridge inverter based on the manufacturer model considered here [37]. However, the present paper has demonstrated successful convergence of much more complex application circuits utilizing this model by careful adjustment of the SPICE simulation options.

3.5. Conclusion

The analysis presented in this chapter provides useful guidance to practitioners in selecting models for use in application studies. It is recognized that the all models presented have suitably low RMS error for application design. Since all the transistor models are with 10% of the experimental data in operating area, accuracy of predicted of conduction losses will likely be limited by other factors such as the parasitic model, load model, or transistor variance.

Additionally, some of the findings presented herein are consistent with expectations. For

example, the semi-physics model is shown to be the least accurate but most computationally efficient option. Other findings are less intuitive. For example, it is demonstrated that connecting

SiC MOSFET models in series (as in a multi-level converter) is significantly more computationally demanding than connecting SiC MOSFET models in parallel. This finding may influence modeling decisions for emerging designs in the medium-voltage application space. The findings of this chapter suggest a path for the implementation of optimized SiC MOSFET models. Specifically, the different aspects of the presented models can be combined in a manner that blends the best aspects of each. This approach will be considered in chapter 5 of this dissertation.

CHAPTER 4:

MODELING DYNAMIC MOSFET BEHAVIOR

4.1. Introduction

Figure 15(a) shows a time-domain comparison of the models identified in chapter 3 during a turn-off transient event, with the manufacturer’s model shown for reference. Apart from the manufacturer’s model, each model was fit to the same characterization data. However, this comparison shows a wide variance in the model predictions. This comparison may be useful for identification of general differences between the models, but the significance of those differences increases the difficulty of studying the fundamental tradeoffs within the underlying interelectrode capacitance models. The large number of compounding details leads to less conclusive analysis of the sensitivities.

Figure 15(b) shows an alternate comparison, in which the four models from the literature are altered to employ the same interelectrode capacitance model. The implementation from the modified Curtice model was selected for this comparison because it is the most straightforward to add to the other models. Figure 15(b) demonstrates significantly less variation between the represented models than Figure 15(a). This demonstrates that the contribution of the interelectrode capacitances is substantially more influential in dynamic behavior prediction than the conduction branch.

Typical Model Behavior Equalized CV Model

10 [V]

GS 0 V -10

100

50 [A] D I

600

[V] 300 DS V

0 0.1 0.2 0 0.1 0.2 0.3 (a) Time [ s] Time [ s] (b) Experiment Semi-Physics Non-Segmented Modified Curtice Physics Manufacturer Figure 15. Comparison between published models and experimental data for = 10 , =

600 V, = 75 A, = 25 °C, (a) behavior as published in the literature, and𝑅𝑅 (b)𝐺𝐺 alteredΩ to𝑉𝑉𝐷𝐷𝐷𝐷 have identical𝐼𝐼𝐷𝐷 interelectrode𝑇𝑇𝐽𝐽 capacitance models Of the models identified in the literature review, there are many suitable candidates for

inclusion in a trade study of available SiC MOSFET models. However, only a subset of these

models could be studied in this work. Rather than limit the scope to the models identified in

chapter 3, a new group of five models are selected which represent a broader cross section of the

possible approaches.

The first model selected uses the arctangent function and is the simplest mathematical

formulation identified for both CDS and CDG. The equation of the arctangent model is shown in

(6):

( ) = + atan( ( + )) (6)

𝑐𝑐 where , , and are fitting parameters𝑓𝑓 𝑥𝑥 and𝑎𝑎 is the𝑏𝑏 voltage∗ 𝑥𝑥 defined𝑐𝑐 by the implementation.

𝑎𝑎 𝑏𝑏 𝑐𝑐 𝑥𝑥

The second model selected is the composite function identified in [13]. This model is

chosen to represent a continuous function with high accuracy. The equation of the composite

function model is shown in (7):

( ) = exp( ) tanh ( ) 1 2 (7) 𝑐𝑐𝑖𝑖 where , , , , and 𝑓𝑓 𝑐𝑐are𝑥𝑥 fitting� parameters𝑎𝑎𝑖𝑖 𝑏𝑏𝑖𝑖𝑥𝑥 and− is� the voltage�𝑑𝑑𝑖𝑖 𝑥𝑥 − defined𝑒𝑒𝑖𝑖 � − by� the implementation. 𝑖𝑖 The variable𝑎𝑎 𝑏𝑏 𝑐𝑐 𝑑𝑑denotes𝑒𝑒 the number of fitting functions𝑥𝑥 employed. The computational complexity

of the model 𝑖𝑖is dependent on , so the model fit was optimized to reduce the number of fitting

parameters while maintaining𝑖𝑖 RMS error below 0.25 nF. For this study, CDG was fit with = 6,

while CDS was fit with = 4. 𝑖𝑖

The third model𝑖𝑖 selected is the LUT defined in terms of capacitance; and the fourth

model selected is the LUT defined in terms of charge. These models are very common in the

literature, but their performance characteristics are the subject of ongoing debate. Including both

capacitance- and charge-based LUT implementations in this study makes it possible to evaluate

whether this distinction introduces any measurable difference in terms of accuracy or run-time performance for the LUT approach. A LUT can easily be implemented for any interelectrode capacitance.

The fifth and final model selected for this comparison is a function defined in terms of charge. However, such a model was not identified in the literature for SiC MOSFETs, so a new model was defined which is similar to the ( ) relationship shown in Figure 2. The charge equation model is a decaying exponential with𝑄𝑄 𝑣𝑣 a static capacitor offset, which is defined in (8):

( ) = exp( ) + (8)

𝑓𝑓𝑞𝑞 𝑥𝑥 𝑎𝑎 ∗ 𝑥𝑥 − 𝑏𝑏 ∗ −𝑐𝑐 ∗ 𝑥𝑥 𝑑𝑑

where , , , and are fitting parameters and is the voltage across the capacitor. This model

was deve𝑎𝑎 loped𝑏𝑏 𝑐𝑐 for 𝑑𝑑optimized simulation performance𝑥𝑥 via low computational complexity. A brief

overview of each model is given in Table X.

TABLE X MODELS SELECTED FOR TRADE STUDY Equation Model Dependent Variable Description of Model Reference Simple capacitance model Arctangent model (4) Capacitance for CDG and CGS [81] Presented in [13], sum of tanh’s and Composite function (5) Capacitance exponentials Capacitance-defined Lookup table defined - Capacitance LUT with capacitance [38], [73] Lookup table defined Charge-defined LUT - Charge with charge [117] Simple charge model Charge equation (6) Charge for CDG and CGS

In addition to the five models identified in Table X, the five in electrode capacitor

implementations identified in Figure 3 are also evaluated in this chapter. The first three implementations (NLM1, NLM2, and SDI1) are used in conjunction with the capacitance-defined models, while the other two (SDI2 and QDC) are used with the charge-defined models. This leads to nine possible capacitance-defined combinations and four possible charge-defined combinations.

4.2. Modeling a Discrete SiC MOSFET

4.2.1. Capacitance Measurements

Practical evaluation of the models selected in the previous section was conducted by first fitting each model to a common set of capacitance characterization data. The capacitance characterization data utilized for this purpose was obtained by the authors through the measurement of a 1.2 kV, 25 mΩ SiC MOSFET sample (Cree C2M0025120D) [128]. Figure 16 shows the device capacitance curves for this device, which were measured with a Keysight

B1505A curve tracer [134]. This data can be used to formulate definitions for fc by the following relationships:

= (9)

𝑅𝑅𝑅𝑅𝑅𝑅 𝐺𝐺𝐺𝐺 𝐶𝐶 = 𝐶𝐶+ with gate to source shorted (DC) (10)

𝑂𝑂𝑂𝑂𝑂𝑂 𝐺𝐺𝐺𝐺 𝐷𝐷𝐷𝐷 𝐶𝐶 = 𝐶𝐶 + 𝐶𝐶 with drain to source shorted (AC) (11)

𝐼𝐼𝐼𝐼𝐼𝐼 𝐺𝐺𝐺𝐺 𝐺𝐺𝐺𝐺 10 𝐶𝐶 𝐶𝐶 𝐶𝐶

1 CRSS

COSS 0.1 Capacitance [nF] CISS

0.01 0 200 400 600 800 1000 Drain-Source Voltage [V] Figure 16. Measured interelectrode capacitance versus drain to source voltage As has been identified in the literature, drain-source voltage bias is only one of the sensitivities relevant to interelectrode capacitance modeling. Another important consideration is the gate-source voltage bias. Figure 17 shows input capacitance, CISS, as a function of gate- source voltage bias. As an additional reference, CISS(VSD) is plotted to evaluate the notion that dependence on VSD and VGS is equivalent. This comparison suggests that these two dependencies are not equivalent, and that the most important dependence for CISS is related to VGS. It is noted that the measurement of CISS(VSD) stops at 0 V since the body diode would begin conducting for

> , where is the forward voltage of the MOSFET body diode.

𝑉𝑉𝑆𝑆𝑆𝑆 𝑉𝑉𝑓𝑓 𝑉𝑉𝑓𝑓

6 CISS(VGS) 5 CISS(VSD) Capacitance [nF] 4

3 -20 -10 0 10 20 Voltage [V] Figure 17. Measured input capacitance versus gate to source voltage, denoted CGG

The strong dependence of input capacitance on VGS is often modeled through a parameter

called CGG. While this dependence is easily modeled with a LUT, the equations defined to fit

CDG are not suited to fit the behavior of CGG. While a LUT for CGS could be used in conjunction

with continuous models for CDG and CDS, this would create a transistor model which mixes

multiple modeling approaches. In order to support evaluation of continuously differentiable

models that incorporate CGG, a new function was defined in terms of capacitance. This equation

is shown in (12):

( + ) ( ) = exp + tanh ( + h) 1) (12) 4 2 𝑥𝑥 𝑐𝑐 𝑓𝑓 where , , , , , 𝑓𝑓,𝑐𝑐 and𝑥𝑥 𝑎𝑎are− fitting𝑏𝑏 ∗ parameters� � and � is the�𝑔𝑔 voltage𝑥𝑥 � defined− � by the 𝑑𝑑

implementation.𝑎𝑎 𝑏𝑏 𝑐𝑐 𝑑𝑑 Specifically,𝑓𝑓 𝑔𝑔 ℎ this model of CGG is used𝑥𝑥 within transistor models which employ the arctangent model or the composite function for CDG and CDS. For the charge equation model,

this definition of CGG was modified into a charge definition by multiplying the full equation by

the node voltage variable, .

𝑥𝑥

4.2.1. Small Signal Accuracy of Capacitance Models

Figure 18 shows a detailed view of each model prediction against the measured

experimental data. The capacitance-defined LUT, shown in Figure 18(a) and Figure 18(b),

precisely predicts the experimental measurement with only slight error between table points.

Similarly, the composite function, shown in Figure 18(c) and Figure 18(d), with its relatively

high number of fitting parameters, has only slightly higher error than the capacitance-defined

LUT. The final capacitance model, the arctangent, is shown in Figure 18(e) and Figure 18(f).

Unlike the prior models, the arctangent model shows significant error, especially at low drain-

source bias voltages. The charge-defined LUT is shown in Figure 18(g) and Figure 18(h).

Because the charge is constant between steps, the capacitance is represented a discretization of the experimental data. This is consistent with the behavior shown in the original publication

[117]. Finally, the fit of the charge equation defined in (8) is shown in Figure 18(i) and Figure

18(j). Due to the low complexity of this model, its prediction of the experimental data is significantly worse than the LUTs or the composite function.

Table Table 10 8

7 1 6

5 .1 (a) (b) 4 Capacitance [nF] Capacitance [nF] .01 3 -2 0 2 4 10 10 10 10 -20 -10 0 10 20 Drain-Source Voltage [V] Gate-Source Voltage [V]

Composite Composite 10 8

7 1 6

5 .1 (c) (d) 4 Capacitance [nF] Capacitance [nF] .01 3 -2 0 2 4 10 10 10 10 -20 -10 0 10 20 Drain-Source Voltage [V] Gate-Source Voltage [V] Arctangent Arctangent 10 8

7 1 6

5 .1 (e) (f) 4 Capacitance [nF] Capacitance [nF] .01 3 -2 0 2 4 10 10 10 10 -20 -10 0 10 20 Drain-Source Voltage [V] Gate-Source Voltage [V]

Charge Table Charge Table 10 8

7 1 6

.1 (g) 5 (h)

4 Capacitance [nF] .01 Capacitance [nF] 3 -2 0 2 4 10 10 10 10 -20 -10 0 10 20 Drain-Source Voltage [V] Gate-Source Voltage [V]

Charge Equation Charge Equation 10 12

10 1 8

.1 (i) 6 (j) 4 Capacitance [nF] Capacitance [nF] .01 2 -2 0 2 4 10 10 10 10 -20 -10 0 10 20 Drain-Source Voltage [V] Gate-Source Voltage [V]

CRSS CO SS CISS Simulation Experiment CGG

Figure 18. Model comparison to experimental interelectrode capacitance data

In order to quantify this analysis, the RMS error was calculated for each model using equation (5). RMS error was computed for each model (capacitance-defined LUT, composite function, arctangent, charge-defined table, charge equation) for each measurement of Figure 18

(CRSS, COSS, CISS, CGG) at each experimental value (one per sample value). The RMS error value computed for each model prediction presented in this section is summarized in Figure 19.

Equivalent RMS Error 1.5

LUT

1 Composite [ nF ] Arctangent

RMS Error 0.5 Charge LUT Charge Equation

0 Crss Coss Ciss CRSS CO SS CISS CggCGG

Figure 19. Equivalent RMS error for the interelectrode capacitance models against the four experimental datasets Evaluating the computed RMS error in Figure 19 reveals that the LUTs and composite functions have extremely low error, as expected. Overall, the capacitance-defined LUT has the lowest RMS error, while the discrete steps evident for the charge-defined LUT implementation in Figure 18 produce slightly greater RMS error than the composite function. The charge equation is the least accurate model in COSS and CGG, but the arctangent model is the least accurate in CRSS and CISS; both have significantly higher RMS error than the other models.

4.3. Empirical Setup

In order to evaluate the accuracy of the dynamic models, the switching behavior of the device under consideration was evaluated using double pulse testing (DPT). Figure 20 shows the

DPT stand used in this analysis, which is an updated version of the system described in [113].

While the low-side device is characterized in this system, the high-side position is also populated

with a MOSFET, rather than a discrete diode. This eliminates the need for a separate diode

model in the analysis which follows. Both devices were fit to the same characterization data.

Figure 20. Empirical setup, DPT stand, gate drivers, and device under test (mounted to bottom of PCB) Figure 21 presents a simplified schematic of the DPT stand used in this work. In addition to a bulk capacitor bank, made up of six, 100 µF, 1200 V film capacitors, the test stand has a large array of 56 nF ceramic decoupling capacitors which are rated at 1000 V, and are packaged in 1210 SMT packaging. A nuance in the design of this test stand was the selection of a source resistor, RS, instead of a gate resistor. This decision increases the accuracy of the gate current measurement by avoiding the common-mode voltage that would otherwise be included in

measuring the voltage drop across the gate resistor.

LP1 IL

Gate Drivers L P2 1 Ω Q1 L EPC -5 V Load Inductor VGS + + Capacitors Decoupling Q2 Capacitor Bank Capacitor VIN RS - + - RShunt IG V - DS + - ID

Figure 21. DPT system schematic, components, and metrology Parasitic inductances in device packages and printed circuit boards significantly influence

the behavior of power electronics systems [64], [135]. The parasitics and parameters for the DPT test stand are enumerated in Table XI. The parasitics of the TO-247 SiC MOSFET package were measured with a Keysight E4990A impedance analyzer [136] employing the analysis techniques discussed in [137]. The remaining test stand parasitics were measured using the methodology proposed in [138]. Additional details on the induction extraction process are given in appendix

A3.

TABLE XI TEST STAND PARAMETER AND PARASITIC VALUES PARAMETER VALUE LD 0.7 nH LS 2.2 nH Package Parasitics LG 7.2 nH RGI 2.8 Ω Decoupling 6.5 µF LP1 5.25 nH Capacitor Banks Bank 600 µF LP2 6.35 nH Gate Loop LGK 13.5 nH L 620 µH Load Inductor EPC 0.19 pF ESR 220 mΩ RSHUNT 100 mΩ Current Shunt LSHUNT 1 nH

4.4. Accuracy Analysis of Dynamic Models

Considering the five implementations identified in Figure 3, and the five capacitance descriptions of Table X, nine possible capacitance-defined models and four possible charge- defined models can be created for each interelectrode capacitance. This creates a wide search space for optimization and produces far too many model combinations to compare simultaneously. In order to present a concise analysis, the possible combinations are strategically cross sectioned into smaller projections. First, the implementations are evaluated in order to down select a reduced subset of implementations for further analysis. Second, this reduced subset of implementations is employed to directly compare the accuracy of the model candidates and identify tradeoffs to inform optimal modeling choices.

In this section, the dynamic models and implementations are evaluated in terms of time- domain accuracy. Further analysis is conducted on simulation run-time in section 4.5. In order to evaluate these models in the time domain, the three interelectrode capacitance models must be combined with a model of the MOSFET conduction behavior to function properly in the time domain. The non-segmented model is selected for this purpose. This model is shown to demonstrate the lowest RMS error of the conduction models considered in chapter 3. To support this analysis, the non-segmented model was stripped down to its conduction elements and the interelectrode capacitor models were integrated into the netlist. Although this is necessary to make the following analysis fair, it does not limit the results of this section. The relative differences between these dynamic models is equally applicable to other conduction models.

4.4.1. Accuracy Impact of Implementation Selection

4.4.1.1. SDI Implementation Accuracy

The first analysis conducted with these newly formed transistor models considers an inherent tradeoff associated with both types of SDI. Figure 22 shows a comparison of the SDI and NLM predictions of drain current, in which all four models are based on a capacitance- defined LUT. While all three subplots show the drain current waveform, each was computed with a different maximum time step allowed for the solver in simulation: specifically, 1 nanosecond, 50 picoseconds, and 10 picoseconds. As the maximum time step is reduced, the damping predicted by SDI approaches the damping of the NLM prediction. The damping observed for larger time steps is therefore attributed to error within the solver. Using the SDI with the default time step produces results similar to the 1 nanosecond maximum step result, which is likely to lead to incorrect estimates of system damping. While this behavior is shown in

Figure 22 for the SDI defined by a LUT, the equation-defined variations exhibit the same issue.

Although not yet introduced, the results of the next section will show that this loss in accuracy is not justified by any improvement in computational complexity. This means that the SDI is objectively worse in both metrics of interest, namely accuracy and simulation speed.

100

[ A ] (a)

D 50 I Drain Current [A] 0

100

[ A ] (b)

D 50 I Drain Current [A] 0

100

[ A ] (c)

D 50 I Drain Current [A] 0 0 25 50 75 25 50 75 100 Time [ns] Time [ns]

NLM1 SDI1 NLM2 SDI2 Model: LUT

Figure 22. Comparison of NLM and SDI implementations with maximum solver timestep of (a) 1 ns, (b) 50 ps, (c) 10 ps 4.4.1.2. NLM vs QDC Implementations

Figure 23 shows a time-domain comparison of the nonlinear mapping implementations and the charge-based implementation. For this comparison, all the implementations use a LUT defined either by capacitance (NLM) or charge (QDC). Unlike the simple derivative implementation, which has a strong dependence on the maximum timestep selected for the simulator, these implementations have very little behavioral difference between default and tight maximum timestep values. Additionally, the two NLM implementations are identical, while the

QDC has a very modest difference in behavior. The most notable result of Figure 23 is the similarity in behavior between the QDC and the NLM implementations. Given the stairstep

behavior evident in the charge-defined LUT capacitance profile shown in Figure 18(g), compared to the piecewise smooth fit of the NLM model capacitance profile shown in Figure

18(a), it is unexpected that the prediction of the two approaches in the time domain is nearly identical.

10 [V]

[ V ] 0 GS GS V V -10

50 [ V ] [A]

D 25 DS I V 0

600

[V] 300 [ A ] DS D I V 0

0 50 100 150 Time [ns]

NLM1 NLM2 QDC Experiment (LUT) (LUT) (LUT)

Figure 23. Comparison of implementations with table functions The key conclusion from this analysis is that the SDI implementations have a distinct accuracy disadvantage when compared to any other implementation studied. This disadvantage can potentially be addressed through requiring a smaller timestep, which comes at the cost of additional simulation time. Given that there is no significant advantage of the SDI over the other implementations, this approach should generally be avoided. In the remaining time domain comparisons shown in this paper, NLM1 will be used for all capacitance-defined models, and

QDC will be used for all charge-defined models. It is noted that NLM2 would also be suitable for capacitance-defined models, although it was not selected for the remaining time domain comparisons.

4.4.2. Accuracy Impact of Model Selection

4.4.2.1. Influence of VGS Dependence

The first accuracy evaluation considers the importance of CGG to time-domain model accuracy. In Figure 24, two model variants are compared to the experimental DPT data.

Specifically, both models have identical LUT implementations for CDG and CDS, while differing

in CGS. The first includes the dependence of CISS on VGS as shown in Figure 18(b). The second

only considers the dependence of CISS on VDS and further, makes the simplifying assumption that

CGS can be modeled by a static capacitance. The most significant difference between the model

behavior shown in Figure 24 is the prediction of gate charge. Because the model with CGG predicts the input capacitance more accurately, power loop dynamics align correctly with the experiment. On the other hand, the simplified CISS model causes an underestimate of gate charge,

which produces a substantial time shift between the gate loop dynamics and the power loop

dynamics.

Turn-Off Switching Waveforms: VDS = 600 V, ID = 75 A, RS = 10 Ω Turn-On 20

10 [ V ] 0 GS

V -10 2

0 [ A ] G I -2 100

50 [ A ] D I 0 600

[ V ] 300 DS

V 0

20 [ kW ]

P 0

0 0.05 0.1 5.05 5.1 5.15 Time [ s] Time [ s]

Experiment LUT (with CGG) LUT (Static CGS) Implementation: NLM1 Figure 24. Comparison of models to experimental DPT data, lookup table (LUT) including CGG,

LUT with static CGS 77

Additionally, Figure 24 shows that CGG also improves the accuracy of the slew rate of the

switching transitions, especially in drain current at turn off. Because the inclusion of CGG

increases CGS for positive gate voltage, the predicted speed of the off-switching transition is

reduced. Accurately modeling the speed of waveform transitions is an important part of

switching loss prediction, which can be seen in the improved prediction of the instantaneous

power loss for the model that includes CGG.

4.4.2.2. Accuracy of Capacitance Models

Figure 25 presents a comparison of the three capacitance-defined models discussed in

section 4.1: the capacitance-defined LUT, the composite function, and the arctangent model. The

most interesting result of this comparison is the poor performance of the arctangent model at turn

off. This large mismatch at turn off is a result of the underprediction of the Miller capacitance at

low VDS. This leads to a shorter Miller plateau and faster transient. Interestingly, the error of the

static CGS prediction in Figure 24 and the error of the arctangent prediction in Figure 25 are very similar, especially at turn-off. This suggests that the characterization mismatch evident in the capacitance profile of the arctangent model in Figure 18 somewhat offsets the improvement gained by implementation of CGG in this model.

Another result of note is the similarity of the composite function and the capacitance-

defined LUT. Considering the significant mismatch seen when assuming a static CGS or using the

arctangent model, this result suggests that while large discrepancies in characterization data

fitting may cause errors in the time-domain, this process is subject to diminishing returns. The

LUT approach is arguably a ‘perfect’ representation of the capacitance profile shown in Figure

18. However, the differences in the time-domain predictions of the LUT and the composite function models are virtually indistinguishable in Figure 25.

Turn-Off Switching Waveforms: VDS = 600 V, ID = 75 A, RS = 10 Ω Turn-On 20

[ V ] 0 GS

V -10 2

0 [ A ] G I -2 100

50 [ A ] D I 0 600

300 [ V ] DS

V 0

20 [ kW ] 0 P

0 0.05 0.1 5.05 5.1 5.15 Time [ s] Time [ s]

LUT Composite Arctangent Experiment Implementation: NLM1 (with CGG) (with CGG) (with CGG) Figure 25. Models comparison to experimental DPT data, lookup table (LUT), composite function, arctangent model 4.4.2.3. Accuracy of Charge Models

Finally, Figure 26 presents a time-domain comparison of the models which use charge

definitions. The capacitance-defined LUT model is retained from the prior comparison as a

benchmark to aid analysis. This comparison corroborates the finding of Figure 23 that the

charge-defined LUT is functionally identical to the capacitance-defined LUT. The charge-based

function model, however, exhibits some discrepancies compared to both LUT models. The most

prominent difference, which is observed at turn off, is likely due to the relatively poor prediction

of CGG by the charge-based function model.

Turn-Off Switching Waveforms: VDS = 600 V, ID = 75 A, RS = 10 Ω Turn-On 20

[ V ] 0 GS

V -10 2

0 [ A ] G I -2 100

50 [ A ] D I 0 600

300 [ V ] DS

V 0

20 [ kW ] 0 P

0 0.05 0.1 5.05 5.1 5.15 Time [ s] Time [ s]

a b b LUT Charge LUT a. Implementation: NLM1 Experiment Charge Equation (with CGG) (with CGG) (With CGG) b. Implementation: QDC

Figure 26. Models comparison to experimental DPT data, lookup table (LUT), Charge LUT, Charge Equation 4.4.2.4. Switching Loss Predictions

In order to add a measure of quantitative analysis to the model comparisons in this

section, the switching losses predicted by each model are compared to the experimentally

measured values in Figure 27. This comparison demonstrates that the all models considered in

this study provide very accurate prediction of switching losses across a wide range of operating

conditions. In fact, if switching losses are the only metric of concern, all the presented models

are suitably accurate. To better distinguish between the small differences in the accuracy of these

models, Figure 27 also provides the percent error of the switching loss prediction for each model.

Comparing models, the arctangent is the furthest outlier from the group, with the highest total

error. The capacitance-defined LUT and the charge-defined LUT are the closest to each other in

prediction but vary slightly from the composite function and charge equation models.

RS = 2 Ω RS = 4.7 Ω RS = 10 Ω 4 ] 3 [ mJ

1 Switching Loss Switching Loss

a a a 10

5 [%]

-5 Percent Error -10

25 50 75 100 25 50 75 100 25 50 75 100

Drain Current [A]

b b Experiment Charge LUT Charge Equation a. Implementation: NLM1 LUTa Compositea Arctangenta b. Implementation: QDC

Figure 27. Switching loss comparison of models to experimental DPT data (all models include

CGG) Considering the time domain analysis as a whole, three candidate models are identified

that are very accurate: the composite function, the capacitance-defined LUT, and the charge-

defined LUT. Since these models have similar transient accuracy, they will be further compared

by considering computational efficiency through evaluation of total simulation run-time.

4.5. Computational Analysis of Dynamic Models

The framework presented in chapter 3 for evaluation of the relative run-time performance

of models in LTspice is also leveraged to evaluate these dynamic models. In this chapter, the

simple buck converter shown in Figure 8 is used as the test topology, with a total simulation time

of 500 µs. The multichip power module (MCPM) component is again used as a modular building

block. Parasitic parameters are randomized between simulations, and each model is evaluated at

least one hundred times.

Two minor changes were made in the present study compared to the setup of chapter 3.

First, this study uses the default SPICE simulation options and tolerances, including the modified

trapezoidal integration method and the “normal” solver configuration in LTspice. Second, the

conduction behavior in each model considered here is normalized to the conduction behavior of

the non-segmented model [37]. It is noted that the static behavior is out of scope for the present

chapter, but this alteration is required to ensure a fair comparison of the run-time performance of the dynamic models under consideration.

Most of the possible combinations of interelectrode capacitance models, implementations, and dependence on VGS were evaluated in this study. However, this creates 26

different SiC MOSFET model variants. The data presented in this section is therefore a small

subset of the total results of this study. This subset is selected to enable meaningful comparisons

between the most important modeling decisions. First, the computational cost of modeling CGG

will be shown in the context of the capacitance-defined LUT model. Second, the run-time performance of the five implementations using the capacitance-defined LUT model will be compared. Third, the relative performance of the three capacitance-defined models will be compared. Finally, the two charge-defined models will be compared.

Figure 28 presents the total run-time of each implementation when using a capacitance- defined LUT model for the simple buck converter with a single die per switch-position. The independent variable in this plot is inclusion of the CGS model dependence on VGS. In the CGG

configuration, the capacitance of CGS is a LUT dependent on the gate to source voltage. In

“Static CGS” configuration, this voltage-dependent capacitance is replaced with a static capacitor.

Figure 28 shows that inclusion of CGG has a negligible impact on total run-time of the SiC

MOSFET model regardless of implementation chosen. The differences shown in this plot

between the two configurations of each implementation are within the expected run-time variance for this study. Considering the significant improvement in accuracy shown in the previous section, inclusion of CGG should be considered even for models which emphasize

computational efficiency. Figure 14 also indicates that NLM1 is the fastest model in this

comparison; this is discussed in further in the context of Figure 15.

] SDI1 45 SDI2

[ Seconds 30 NLM1

NLM2 - Time 15

Run QDC Run-Time [Seconds] 0 C Static C Model: LUT GG GS Figure 28. Run-time of implementation for CGG cs Static CGS, using buck converter simulation with single die per switch-position Figure 29 presents the run-time for each implementation compared when considering

various numbers of transistors at each switch position. For this scaling, individual gate and

power loop parasitic inductances are included with each SiC MOSFET die within the simulation.

Figure 29 shows that the model implementation has a considerable influence on run-time performance and that the total run-time scales super-linearly with the number of parallel die per switch position. The fastest implementation in this comparison is NLM1, which takes 16.7

seconds on average to solve the simplest simulation and 160 seconds on average to complete the

most complex simulation. The NLM2 implementation demonstrates 10% longer run-time in the simplest simulation, and 107% longer run-time in the most complex simulation. The SDI models take significantly longer to solve the simpler simulations. In the single-die simulation, SDI1 and

SDI2 require 29.9 and 45.5 seconds to complete, respectively. Generally, the QDC is the slowest

implementation shown in this comparison. However, its cumulative performance is more

nuanced than the other implementations and is not well represented by this comparison alone.

This is discussed further in the context of Figure 31.

10 3 SDI1

2 10 SDI2

1 Minute NLM1 1 10 NLM2

Run-Time [Seconds] QDC 10 0 1 2 4 8 16 32 Parallel Die per Switch Model: LUT

Figure 29. Run-time of implementation vs die per switch-position, using capacitance-defined LUT model and buck converter simulation

As indicated in section 4.4.1.1, the SDI implementations are not faster than the NLM

implementations. This comparison, however, is made at the default maximum timestep value in

SPICE. If the maximum timestep is decreased for the SDI implementation such that the accuracy of the SDI and NLM implementations are comparable, the run-time penalty for using the SDI implementation would be increased further.

Figure 30 compares the run-time of the capacitance-defined models when using NLM1

implementation (thus, LUT of Figure 30 is equivalent to NLM1 of Figure 29). With a 20%

reduction in run-time compared to the capacitance-defined LUT, the arctangent model is the

fastest of the capacitance-defined models but comes with a corresponding accuracy disadvantage

when compared to the LUT and the composite function. The capacitance-defined LUT model has

an average run-time advantage of 33% over the composite function, for this particular

implementation. It should also be noted that the computational complexity of the composite

function is dependent on the number of fitting parameters used. This run-time penalty could

increase for more complex datasets. The hierarchy identified in Figure 30 has also been validated

for NLM2 and SDI1, which have been removed from this comparison for clarity.

10 3 LUT

2 10 Composite 1 Minute

1 10 Arctangent Run-Time [Seconds] 10 0 1 2 4 8 16 32 Implementation: Parallel Die per Switch NLM1

Figure 30. Run-time of model vs die per switch-position, using buck converter simulation The final run-time comparison, shown in Figure 31, demonstrates the significant difference in run-time between the two charge-defined models for the QDC implementation. The capacitance-defined LUT is included for comparison purposes. The charge-defined LUT is extremely slow – on average 125% slower than the capacitance-defined LUT. However, the charge function model is extremely fast – on average 40% faster than the capacitance-defined

LUT. This discrepancy in run-time for the two charge-based models is not expected. One possible explanation is that the QDC model has a significant speed advantage over all the other models, which is lost entirely when using a charge-defined LUT. The increase in simulation time for the charge-defined LUT is believed to be the result of the discontinuities in capacitance leading to very small iteration time when the voltage passes through a step.

10 3 LUTa

2 10 Charge LUTb 1 Minute Charge Equationb 1 10

Run-Time [Seconds] Implementation: 0 10 a: NLM1 1 2 4 8 16 32 b: QDC Parallel Die per Switch

Figure 31. Run-time of model vs die-per-switch position, buck converter Table XII shows the cumulative results of the accuracy and run-time analyses conducted in section 4.4 and section 4.5, respectively. From these results, three specific model recommendations can be made. First, the equation-based QDC approach is uniquely suited for lightweight models which consider computation speed the primary metric. Second, the capacitance-defined LUT implemented with NLM1 presents a good balance of accuracy and computation speed. Third, the composite function with NLM1 is an excellent choice for models which are not overly constrained by computation time and which seek to avoid the possibility of convergence challenges which may be associated with LUTs. The NLM2, SDI1, and SDI2 implementations do not positively differentiate themselves and are not recommended. Similarly, the arctangent and charge-defined LUT models are likewise absent from the optimal front of accuracy versus run-time.

TABLE XII STUDY CONCLUSIONS: MODEL SPEED VS. ACCURACY Implementation Accuracy Performance

NLM1 Nominal Fastest of Capacitance-Defined

NLM2 Nominal Slower than NLM1

SDI1 Dependent on Timestep Slower than NLM1

SDI2 Dependent on Timestep Slower than QDC QDC Nominal Fastest Model Arctangent model Low Fast Composite function High Slower Capacitance- defined LUT High Moderate Charge-defined LUT High Slowest Charge equation Low Fastest

4.6. Conclusion

This study provides a targeted extension to the existing literature on modeling the dynamic behavior of SiC MOSFETs in SPICE. While the literature contains numerous examples of suitable SiC MOSFET models, few comparisons between these models exist to facilitate modeling decisions. From the perspective of application design, model accuracy and computational complexity must both be carefully considered to achieve models with practical utility. Therefore, in this chapter, attention is given to quantifying the trade-offs associated with modeling decisions.

The resulting analysis provides useful guidance to practitioners in selecting models for use in application studies. Charge-defined models generally have a reasonable performance advantage over capacitance-defined models, albeit with a modest decrease in accuracy. This advantage, however, is insignificant when compared to the high computational cost of charge- defined lookup tables. Capacitance-defined lookup tables, however, have lower computational overhead and are a good balance of simulation speed and accuracy. Additionally, since lookup tables can use experimental data directly these models are very easy to create.

In addition to model recommendations, this analysis presents strong recommendations

for appropriate implementations of interelectrode capacitance in LTspice. Defining a capacitor

with voltage-dependent charge is optimal for simulation speed and should be selected when a

model can be defined in terms of charge. For capacitance-defined models, implementations

which leverage a linear capacitor in SPICE have both accuracy and speed advantages over

models which take the voltage derivative mathematically. As the absolute increase in model run-

time is strongly correlated to simulation complexity, consideration of these trade-offs is critical for application simulations. In total, this analysis equips model designers to make quantitatively motivated optimizations in future model development.

CHAPTER 5:

APPLICATION-FOCUSED SIC MOSFET MODEL

5.1. Introduction

Chapters 3 and 4 identify and quantify the inherent tradeoffs between accuracy and simulation performance of the various candidate elements of published SiC MOSFET models.

Many of the models identified in the literature have unique contributions, but no single model

exists on the optimal front of accuracy versus simulation run-time. By combining the best

contributions of the models identified in the literature, a new model is proposed in this chapter

which emphasizes low computation complexity and minimizes run-time while avoiding major

penalties to accuracy. Such a model is uniquely suited for application design within the field of

power electronics. In addition to selecting model components from the prior analysis, this

chapter also proposes modifications and optimizations for the static and dynamic components to

further enhance the proposed MOSFET model.

5.2. Static Model Optimization

As identified in chapter 3, the non-segmented model has excellent accuracy at 25 °C and

extremely good computational performance. While the level 1 model is slightly faster in

simulation run-time, it also incurs a relatively high penalty to accuracy, which is not acceptable

for the goals of this dissertation. Similarly, the non-segmented model has relatively low accuracy

at elevated temperature, which likewise is not acceptable. Fortunately, the thermal components

of the non-segmented model are separable from its conduction branch, and its accuracy at

elevated temperature can be greatly improved by replacing the original thermal model with an

improved thermal model.

Figure 1 shows the accuracy of the non-segmented conduction branch at 150 °C using the

thermal model originally published by Li [37]. This thermal model is a linear scaling and shifting

of VGS and VDS at elevated temperature. This design avoids all discontinuities in the model

definition and is computed with the core behavioral current rather than in additional netlist

components. This design, however, is poorly suited for modeling the increase in drain resistance

at high temperature, as the increase in channel resistance creates nonlinear scaling in the

saturation region. This effect is especially obvious in the model forward prediction at = 20 V

𝐺𝐺𝐺𝐺 and transfer prediction at = 35 V. Figure 32 also shows a modified version of the𝑉𝑉 non-

𝐷𝐷𝐷𝐷 segmented conduction branch𝑉𝑉 incorporating the Wang thermal model, which was published in

[77] and used by the semi-physics model [107]. This model, which adds a thermally dependent

series resistance and gate-source offset voltage, is a more realistic and accurate of model of

semiconductor dependence on temperature. Additionally, the Wang model can easily be

calculated from experimental data while the Li model is computationally intensive to fit.

150°C, Forward,Forward Li Thermal, 150 Model °C 150°C, Transfer,Transfer Li Thermal, 150 Model °C 150 150

100 100 [A] [A] D D I 50 I 50

0 0 0 5 10 15 0 5 10 15 20 V [V] V [V] DS GS 150°C,Forward Forward, External, 150 °C 150°C,Transfer Transfer, External, 150 °C 150 150

100 100 [A] [A] D D I 50 I 50

0 0 Wang Thermal ModelWang Thermal 0 5 10 15 0 5 10 15 20 V [V] V [V] DS GS

VGS = 0 V VGS = 5 V Simulation VDS = 0 V VDS = 2 V VGS = 7.5 V VGS = 10 V VDS = 4 V VDS = 15 V V = 15 V V = 20 V Experiment V = 35 V GS GS DS Figure 32. Model prediction of experimental data, Forward and Transfer, TJ = 150 °C While the Wang model is significantly more accurate than the Li model, the Li thermal

model has a significant advantage in simulation performance. Figure 33 shows the comparative

run-time of both models in the DPT test circuit shown in Figure 7. This analysis explains why the accuracy compromise was originally accepted by Li for this continuous thermal model.

Specifically, the Li thermal model introduces only a 3% increase in simulation run-time when compared to the non-segmented model with no thermal dependence whatsoever. The Wang model, however, increases the simulation run-time by 400%. This significant increase in computational complexity indicates that the Li model is preferred over the Wang model for simulations which do not need to be accurate over a broad temperature range.

1 10 No Thermal Model

Li Thermal 10 0 Model

Wang Thermal Run-Time [Seconds] -1 Model 10 1 2 4 8 16 32 Parallel Die per Switch

Figure 33. Run-time comparison between thermal models in DPT, for non-segmented core Careful analysis of the two model approaches, however, indicates that a better

compromise of accuracy and simulation performance can be achieved than available through

either of these approaches as published. Figure 34 shows a high-level overview of the Li and

Wang models. While Li’s model internalizes the thermal dependence completely, the Wang model implements external elements for each thermally dependent characteristic. While the main accuracy advantage of the Wang model is derived from the external model of drain resistance, the main contributor to its high simulation cost is the dependent voltage source used to offset

VGS. Fortunately, this offset can be moved within the main model of drain current, at least for

behavioral sources. Figure 34 proposes a new thermal model which incorporates a gate-voltage offset operation into the behavioral current source representing channel current, and which also employs an external, thermally dependent drain resistance.

Li Thermal Model Wang Thermal Model New Thermal Model Drain Drain Drain

Gate Gate Gate Source Source Source

Figure 34. Non-segmented conduction model with three thermal model variants The prediction of the new model is compared to experimental data in Figure 36. When

restricted to DC analysis, the new model is mathematically identical the Wang model, and

perfectly replicates its predictive accuracy. This conclusion is further corroborated by the total

RMS error of all three models, which is shown in Figure 36. This figure is a corollary to Figure 5

and is likewise computed by taking the RMS of the RMS error at each bias, calculated using equation (5) iteratively.

150°C,Forward Forward,, 150 New °C 150°C,Transfer Transfer,, 150 New °C 150 150

100 100 [A] [A] D D I 50 I 50

New Themral Model 0 0 0 5 10 15 0 5 10 15 20 V [V] V [V] DS GS

VGS = 0 V VGS = 5 V Simulation VDS = 0 V VDS = 2 V VGS = 7.5 V VGS = 10 V VDS = 4 V VDS = 15 V V = 15 V V = 20 V Experiment V = 35 V GS GS DS Figure 35. New thermal model prediction of experimental data, Forward and Transfer, TJ = 150 °C

Equivalent RMS Error, 150 °C 5

] 4 A

[ Li Thermal Model 3 Wang Thermal Model 2

RMS Error [A] 1 New Thermal Model RMS Error

Forward Transfer

Figure 36. Equivalent RMS error of thermal models at 150 °C for the three thermal models with non-segmented conduction model Figure 37 shows that the computational cost of the new model is substantially lower than that of the Wang thermal model. Despite having significantly higher accuracy than the Li thermal model, the new model increases average run-time by only 15% compared to a model with no thermal dependence. The substantial improvement in accuracy over temperature is sufficient justification for this modest increase in run-time. Therefore, the new thermal model proposed herein is selected in conjunction with the non-segmented conduction branch to implement the static behavior in the new MOSFET model.

No Thermal

1 Model 10 Li Thermal Model 10 0 Wang Thermal Model Run-Time [Seconds] -1 10 New Thermal 1 2 4 8 16 32 Model Parallel Die per Switch

Figure 37. Run-Time in DPT of new thermal model versus prior art

5.3. Dynamic Model Optimization

Charge-defined capacitor implementations (QDC) have demonstrable advantages for

computationally lightweight models. Chapter 4 identified that QDCs using simple charge

equations are capable of the lowest run-time, albeit with some loss of accuracy. Additionally, because these models are recognized by LTspice as capacitors, solver optimizations can be employed in finding DC bias solutions. Such optimizations are not applicable to implementations based on arbitrary current sources. This advantage is especially important for simulation of complex converter topologies (such as multilevel converters), as the failure to accurately solve for the DC operating point is a major cause of non-convergence in transient converter simulations for such systems [56].

Ideally, charge-defined LUTs could leverage the advantages of the QDC implementation without accuracy loss, but chapter 4 identified that this strategy has relatively high computational cost. Considering the low accuracy and low complexity of the charge equation defined in chapter

4, a model which is more accurate than the charge equation but with lower computational cost than the charge-defined LUT would be an ideal candidate for an application-focused MOSFET model. The high accuracy of the capacitance-defined composite function suggests that a similar model could be created in terms of charge with similarly high accuracy. As identified by the comparison of the composite and arctangent models, the new model would need to balance the improved accuracy against the run-time cost of more computationally complex fitting functions.

Dynamic MOSFET models regularly employ sigmoid functions to define interelectrode capacitance, and such functions have also been employed in the definition of composite functions [13]. An additional challenge is encountered, however, as defining models in terms of charge requires matching the integral of capacitance. To overcome this challenge, the integral of

a sigmoid function was selected for the proposed model. Specifically, the logistics function was

selected as its integrand is computationally lightweight relative to other common sigmoid

functions. Its integrand is defined by Equation (13).

= ln(1 + ) (13) 1 +𝑥𝑥 𝑒𝑒 𝑥𝑥 This type of function has been� used previously𝑥𝑥 𝑑𝑑𝑑𝑑 in a 𝑒𝑒GaN HEMT model with charge- 𝑒𝑒 defined interelectrode capacitance [75]. In the previous work, this model was presented as a

single fitting function. In the proposed model, this approach is expanded into a new composite

function defined for capacitor charge. Specifically, this new function is defined as,

( ) = + + ln 1 + exp ( + ) (14) where , , and represent𝑓𝑓𝑞𝑞 𝑥𝑥 elements𝑄𝑄0 𝑥𝑥 𝐶𝐶of0 variable� 𝑎𝑎𝑖𝑖 length� arrays�𝑏𝑏 𝑖𝑖of𝑥𝑥 fitting𝑐𝑐𝑖𝑖 �pa� rameters. is a 𝑖𝑖 𝑖𝑖 𝑖𝑖 𝑖𝑖 0 fixed capacitor𝑎𝑎 𝑏𝑏 within𝑐𝑐 the model that is useful in preventing regions of negative capacitance,𝐶𝐶

which will cause convergence issues in time-domain simulations. Finally, is used to

0 normalize the total charge of the fitting equation to the origin. 𝑄𝑄

Figure 38 shows the small-signal prediction of the proposed capacitance model. This

figure demonstrates that the fitting function can predict the experimental data with high

accuracy. The particular fit shown in this figure uses 26 parameters for CGD, 20 parameters for

CDS, and 23 fitting parameters for CGG. Figure 39 shows the RMS error of the proposed model alongside that of the most accurate interelectrode capacitance models identified in chapter 4.

These error metrics are calculated using equation (5). While the capacitance-defined LUT demonstrates the lowest average RMS error overall, the charge composite function has slightly lower CISS error and is second-lowest in CGG and CRSS error. Other than the slight advantage in

COSS, the capacitance-defined composite function has higher average error than the charge

composite function. This accuracy improvement is not the result of an inherent advantage of the

charge composite function; rather it is the result of choosing fewer fitting parameters for the

capacitance-defined composite function. While the capacitance composite function could be

fitted with additional parameters to improve its accuracy, this would increase its computational

difficulty. It will be shown that despite the increased number of parameters and higher accuracy

of the charge-defined composite function compared to the capacitance-defined composite

function, the charge-defined composite function has improved run-time performance.

Charge Composite Charge Composite 10 8

7 1 6

5 .1 4 Capacitance [nF] Capacitance [nF] .01 3 -2 0 2 4 10 10 10 10 -20 -10 0 10 20 Drain-Source Voltage [V] Gate-Source Voltage [V]

C C CISS Simulation Experiment C RSS O SS GG Figure 38. Small signal prediction of the charge composite function

Equivalent RMS Error 0.25

0.2 LUT 0.15 Composite

0.1 Charge LUT

0.05 Charge Composite RMS Error [nF]

0 CrssC CossC CissC CggC RSS O SS ISS GG Figure 39. Comparison to other accurate capacitance models Figure 40 compares the time-domain prediction of the new charge composite function to

the capacitance-defined LUT. The accuracy difference between the charge composite function and LUT is negligible. This particular result is not entirely surprising given that, in AC analysis,

these two models predict nearly identical interelectrode capacitance for the dependencies

considered. Further, this comparison provides additional insight into the comparison of the

capacitance composite function and the LUT shown in Figure 25. Specifically, it is likely that the

inclusion of additional tuning parameters in the capacitance composite function would eliminate

the remaining discrepancy between these two models.

Turn-Off Switching Waveforms: VDS = 600 V, ID = 75 A, RS = 10 Ω Turn-On 20

10 [ V ] 0 GS V -10 2

0 [ A ] G I -2 100

50 [ A ] D I 0 600

[ V ] 300 DS V 0

20 [ kW ]

P 0

0 0.05 0.1 5.05 5.1 5.15 Time [ s] Time [ s]

a b LUT Charge Composite a. Implementation: NLM1 Experiment (with C ) (With C ) GG GG b. Implementation: QDC Figure 40. Time domain accuracy of charge composite In order to compare the run-time of the charge composite function to the other dynamic

models, it was evaluated in the buck converter circuit shown in Figure 8. Figure 41 shows that

the run-time of the charge composite function is comparable to that of the capacitance-defined

LUT, and that it has a slight run-time advantage over the capacitance-defined composite function. Interestingly, this performance increase is in-spite of the increased number of fitting equations used in the charge composite function. This highlights the increase in computational efficiency associated with the charge composite function. For a given level of accuracy, this approach will have higher run-time performance than any implementation based on behavioral sources. Additionally, reducing the number of fitting functions could further improve the computation speed of the charge composite function, although this would come at the cost of

accuracy. The run-time of the standard charge equation represents the lower bound of complexity achievable by a variable QDC implementation.

LUTa Compositea 2 10 Charge LUTb

Charge Equationb

Charge Compositeb 1 10 Run-Time [Seconds] Implementation: 1 2 4 8 16 32 a: NLM1 Parallel Die per Switch b: QDC

Figure 41. Run-time of charge composite, for buck converter This analysis shows that the charge composite function is essentially identical in speed and accuracy to the capacitance-defined LUT, but with the inherent advantages of the QDC implementation. Specifically, this implementation has fewer nodes and fewer components than the NLMs, does not suffer from the timestep restrictions of the SDIs, and is recognized in

LTspice as a capacitor rather than as an arbitrary source. This makes the charge composite function the optimal choice for application models and complex simulations. There is one distinct advantage, however, to the capacitance-defined LUT which should also be recognized.

Specifically, the LUT can be created by simply interpolating experimental data, whereas fitting the charge composite function is more difficult. This difficulty arises from the need to evaluate the model fit in terms of the charge function gradient and the variable number of fitting parameters which affect both accuracy and computational complexity. While the LUT is certainly acceptable for models prioritizing rapid development and deployment, the increased fitting difficulty associated with the charge composite function was not of primary concern for the goals of this dissertation.

5.4. Final Model

The results of the proceeding analysis provide a sufficiently wide set of model characteristics to address all aspects required to synthesize a new model optimized for application simulations. Table VII gives a brief description of the model elements selected as well as their original source. The conduction equations are derived from the non-segmented model [37], but the tuning strategy developed for the modified Curtice model [38] is employed to reduce the computational difficulty of fitting the conduction model. Additionally, a new thermal model, modified from the semi-physics thermal model published by Wang [77], was selected to model dependence on temperature. Due to the high run-time penalty of the original model, it was adapted to improve run-time performance with no loss to accuracy. The 3rd quadrant model also follows the strategy presented for the non-segmented model, in which the SPICE diode element is used to model the body diode of the MOSFET. Finally, the charge composite function proposed in this chapter is used to capture the dynamic characteristics of the MOSFET.

Together, these model elements comprehensively define the behavior of the SiC MOSFET. The combined netlist of the final proposed model is shown in Figure 42.

TABLE XIII MODELS ELEMENTS SELECTED FOR SYNTHESIS Model Component Definition Description Conduction Non-Segmented [37] Continuously defined behavioral current source Equation Conduction Tuning Repeatedly fit tuning variables at each VGS and Modified Curtice [38] Strategy interpolate with continuous function External variable drain resistance, Thermal Model Modified Wang Model [77] internalized gate offset voltage 3rd Quadrant SPICE Diode Model [28] Body diode behavior

CGD Charge Composite Dependent on VDS

CDS Charge Composite Dependent on VDS

CGS Charge Composite Dependent on VDS and VGS

100

Synthesized Model Drain

Qc RDT (20) (18) Gate IDIO Qc ID ST (19) (20) Qc (13) (20) Source

Figure 42. Final proposed SiC MOSFET model, combining all prior elements Figure 42 shows the synthesized model, which includes the following definitions:

, , = + , (15)

𝐼𝐼𝐷𝐷𝐷𝐷𝐷𝐷�𝑉𝑉(𝐺𝐺𝐺𝐺 𝑉𝑉, 𝐷𝐷𝐷𝐷 𝑇𝑇)𝐽𝐽=� 𝐼𝐼𝐷𝐷𝐷𝐷( 𝐷𝐷�𝑉𝑉)𝐺𝐺𝐺𝐺 𝑉𝑉𝑂𝑂(𝑂𝑂�𝑇𝑇,𝐽𝐽� 𝑉𝑉𝐷𝐷𝐷𝐷) � (16) ( ) =𝐼𝐼𝐷𝐷𝐷𝐷 𝑉𝑉[𝐺𝐺𝐺𝐺1 +𝑉𝑉𝐷𝐷𝐷𝐷tanh(𝐼𝐼𝑇𝑇𝑇𝑇 (𝑉𝑉𝐺𝐺𝐺𝐺 +⋅ 𝐼𝐼𝑂𝑂𝑂𝑂𝑂𝑂) +𝑉𝑉𝐺𝐺𝐺𝐺k 𝑉𝑉𝐷𝐷𝐷𝐷( + k ) )] (17) ( ) 2 𝐼𝐼𝑇𝑇𝑇𝑇 𝑉𝑉𝐺𝐺𝐺𝐺 𝑘𝑘1 ⋅ ( , 𝑘𝑘)2 =⋅ 𝑉𝑉𝐺𝐺𝐺𝐺 𝑘𝑘3 4 ⋅ 𝑉𝑉𝐺𝐺𝐺𝐺 5 (18) 1 + (𝐺𝐺𝐺𝐺 ) 𝐷𝐷𝐷𝐷 𝑂𝑂𝑂𝑂𝑂𝑂 𝐺𝐺𝐺𝐺 𝐷𝐷𝐷𝐷 𝑝𝑝 𝑉𝑉 ⋅ 𝑉𝑉 𝐼𝐼 = 𝑉𝑉 𝑉𝑉 25 + 𝐺𝐺𝐺𝐺 𝐷𝐷𝐷𝐷+ 25 (19) 𝑞𝑞 𝑉𝑉 ⋅ 𝑉𝑉 2 = 25 + + 25 + 10 𝑉𝑉𝑂𝑂𝑂𝑂�𝑇𝑇𝐽𝐽� 𝑇𝑇𝑉𝑉1 ⋅ �𝑇𝑇𝐽𝐽 − � 𝑇𝑇𝑉𝑉2 ⋅ �𝑇𝑇𝐽𝐽 � (20) 2 −6 𝑅𝑅𝐷𝐷𝐷𝐷�𝑇𝑇𝐽𝐽� 𝑇𝑇𝑅𝑅0(�𝑇𝑇𝑅𝑅)1 ⋅=�𝑇𝑇series𝐽𝐽 − � 𝑇𝑇𝑅𝑅2 ⋅ �𝑇𝑇1𝐽𝐽 , � � (21) 𝑉𝑉𝑆𝑆𝑆𝑆 𝑉𝑉𝑇𝑇𝑇𝑇 𝐼𝐼𝐷𝐷𝐷𝐷𝐷𝐷 𝑉𝑉𝑆𝑆𝑆𝑆 �𝐼𝐼𝑆𝑆 �𝑒𝑒 − � 𝑅𝑅𝑆𝑆� ( ) = + + ln 1 + exp ( + ) (22) where , , , , 𝑄𝑄,𝑐𝑐 𝑥𝑥 , 𝑄𝑄,0 𝑥𝑥, 𝐶𝐶0 , �,𝑎𝑎 𝑖𝑖 , �, , ,� 𝑏𝑏𝑖𝑖, 𝑥𝑥 , and𝑐𝑐𝑖𝑖 �� are fitting 𝑖𝑖 1 2 3 4 5 𝑉𝑉1 𝑉𝑉2 𝑅𝑅0 𝑅𝑅1 𝑅𝑅2 𝑆𝑆 𝑆𝑆 0 𝑖𝑖 𝑖𝑖 𝑖𝑖 parameters,𝑘𝑘 𝑘𝑘 while𝑘𝑘 𝑘𝑘 ( 𝑘𝑘 ) 𝑇𝑇and 𝑇𝑇( 𝑇𝑇) are𝑇𝑇 fitting𝑇𝑇 functions𝐼𝐼 𝑁𝑁 𝑅𝑅 . Additionally,𝐶𝐶 𝑎𝑎 𝑏𝑏 the𝑐𝑐 body diode model

𝐺𝐺𝐺𝐺 𝐺𝐺𝐺𝐺 identified in (19) is𝑝𝑝 implemented𝑉𝑉 𝑞𝑞 𝑉𝑉 as a native diode model within SPICE. Finally, it is

101

recommended that a high-value static resistor is placed in parallel with the behavioral resistor,

RDT, to improve simulation performance for finding the initial DC operating point in transient simulations. One giga-ohm was used in this model implementation, but other values less than

1/ would also be suitable. The netlist of this model is given in appendix A1.

𝑔𝑔𝑔𝑔𝑔𝑔𝑔𝑔Figure 43 shows the complete static behavior of the proposed model when fit to experimental data collected for a discrete SiC MOSFET [128]. The novel conduction model proposed in this dissertation leads to an excellent prediction of the static characteristics across all temperatures. Additionally, the modular nature of the charge composite function allows a highly accurate fit of the interelectrode capacitance.

102

25°C, Forward, Final Model 25°C, Transfer, Final Model 150 Forward, 25 °C 150 Transfer, 25 °C

100 100 [A] [A] D D I 50 I 50

0 0 0 5 10 15 0 5 10 15 20 V [V] V [V] DS GS 100°C, Forward,Forward Final, 100 Model °C 100°C, Transfer,Transfer Final, 100 Model °C 150 150

100 100 [A] [A] D D I 50 I 50

0 0 0 5 10 15 0 5 10 15 20 V [V] V [V] DS GS 150°C, Forward,Forward Final, 150 Model °C 150°C, Transfer,Transfer Final, 150 Model °C 150 150

100 100 [A] [A] D D I 50 I 50

0 0 0 5 10 15 0 5 10 15 20 V [V] V [V] DS GS

VGS = 0 V VGS = 5 V Simulation VDS = 0 V VDS = 2 V VGS = 7.5 V VGS = 10 V VDS = 4 V VDS = 15 V VGS = 15 V VGS = 20 V Experiment VDS = 35 V

Charge Composite Charge Composite 10 Capacitance, VDS 8 Capacitance, VGS

7 1 6

5 .1 4 Capacitance [nF] Capacitance [nF] .01 3 -2 0 2 4 10 10 10 10 -20 -10 0 10 20 Drain-Source Voltage [V] Gate-Source Voltage [V]

C C CISS Simulation Experiment CGG RSS O SS Figure 43. Final variant of proposed model, static validation

103

Figure 44 shows the model prediction of the experimental DPT data when using a 10 Ω

gate resistance. The experimental test setup is described in section 4.3. In general, the model

accurately predicts the gate charge at both turn-off and turn-on, which is a result of considering the VGS dependence of CISS. Additionally, the model is relatively accurate in the power loop

dynamics, accurately predicting the slew rate of both voltage and current as well as instantaneous

power loss.

Turn-Off Switching Waveforms: VDS = 600 V, ID = 75 A, RS = 10 Ω Turn-On 20

10 [ V ]

GS 0 V -10 2

[ A ] 0 G I

-2 100

50 [ A ] D I 0 600

[ V ] 300 DS V 0

20 [ kW ]

P 0

0 0.05 0.1 0.15 5.05 5.1 5.15 5.2 Time [ s] Time [ s] Experiment Final Model Figure 44. Final variant of proposed model, dynamic validation, = 10

𝑅𝑅𝑆𝑆 Ω

104

Figure 45 shows the model prediction of the experimental DPT data when using a 4.7 Ω

gate resistance. In general, the model accurately models the gate charge at both turn-off and turn-

on, which is a result of considering the VGS dependence of CISS. Additionally, the model is

accurate in predicting the power loop dynamics, particularly at turn-off. A modest discrepancy is noted in the drain-source voltage at turn-on, but this only minimally impacts the prediction of switching loss.

Turn-Off Switching Waveforms: VDS = 600 V, ID = 75 A, RS = 4.7 Ω Turn-On 30 15

[ V ] 0 GS

V -15

[ A ] 0 G I -2

100

50 [ A ] D I 0 600

[ V ] 300 DS V 0

20 [ kW ]

P 0

0 0.05 0.1 0.15 5.05 5.1 5.15 5.2 Time [ s] Time [ s] Experiment Final Model Figure 45. Final variant of proposed model, dynamic validation, = 4.7

𝑅𝑅𝑆𝑆 Ω

105

Figure 46 shows the model prediction of the experimental DPT data when using a 2 Ω

gate resistance. In general, the model accurately models the gate charge at both turn-off and turn-

on, which is a result of considering the VGS dependence of CISS. Additionally, the model is

accurate in predicting the power loop dynamics, particularly at turn-off. A modest discrepancy is again noted in the drain-source voltage at turn-on, but this only minimally impacts the prediction of switching loss.

Turn-Off Switching Waveforms: VDS = 600 V, ID = 75 A, RS = 2 Ω Turn-On

[ V ] 15

GS 0 V -15

4 2

[ A ] 0 G

I -2 -4

100

[ A ] 50 D I 0

600

[ V ] 300 DS V 0

40 20 [ kW ]

P 0

0 0.05 0.1 0.15 5.05 5.1 5.15 5.2 Time [ s] Time [ s] Experiment Final Model Figure 46. Final variant of proposed model, dynamic validation, = 2

𝑅𝑅𝑆𝑆 Ω

106

In order to add a measure of quantitative analysis to the model comparisons in this

section, the switching losses predicted by the model are compared to the experimentally

measured values in Figure 47. This comparison demonstrates that the model provides a very

accurate prediction of switching losses across a wide range of operating conditions. Figure 47

also provides the percent error of the switching loss prediction, showing that the model has less

than 10% error for all considered operating conditions.

RS = 2 Ω RS = 4.7 Ω RS = 10 Ω 4 ] 3 [ mJ

1 Switching Loss Switching Loss

a a a 10

5 [%]

-5 Percent Error -10

25 50 75 100 25 50 75 100 25 50 75 100

Drain Current [A] Experiment Final Model Figure 47. Final variant of proposed model, switching loss prediction 5.5. Conclusion

This chapter proposes a new SiC MOSFET model which incorporates some of the best elements of published models, while introducing several novel features which collectively advance the performance of this model beyond anything reported in the literature to date. While the model is extremely accurate in time domain prediction, it is also highly optimized for computational cost and has extremely low run-time relative to the degree of accuracy achieved.

The motivation and design decisions also result in good model convergence for complex

107

transient simulations. In total, this model is well suited for supporting simulation-based design of complex SiC-based applications.

108

CHAPTER 6:

CONCLUSION AND FUTURE WORK

The primary contribution of this dissertation is a novel SiC MOSFET model which has not been described previously in the literature. This work extends the prior art by leveraging the best-performing components of several previously published models. Through careful study of computational cost contextualized within simulation accuracy, individual model elements are evaluated and selected by quantitative metrics that describe the tradeoff between these criteria. In addition, several model enhancements, which are not previously described in the literature, are introduced to address deficiencies of the published model elements. The result of this methodology is the synthesis of a model which is uniquely optimized for application design and complex converter simulations, both in its ability to converge and in its computational speed.

Additionally, the new SiC MOSFET model presented herein is highly accurate in both static and transient simulations.

In addition to this new model, this dissertation provides studies and results in chapters 3,

4, and 5 with applicability outside this dissertation. While these studies were performed to inform the design of a specific model, their results can also inform future model optimization efforts. For models which prioritize computational performance, many of the tools, techniques, and benchmarks presented herein should be heeded. For example, a key result identified in chapter 5 is that the introduction of thermal dependence, even in a simplified form, can have a significant impact on model run-time performance. For application-focused models, the computational complexity increase of individual model additions should be carefully evaluated,

109

and benchmarked. If major performance degradation is identified, there may exist alternate implementations with similar accuracy but reduced computational complexity.

Finally, this dissertation provides a new suite of tools and techniques that can be used to quantitatively evaluate the accuracy and performance of future models. While there are numerous SiC MOSFET models available in the literature today, there is no means available to compare these models in a quantitative fashion. This makes it difficult for application designers to select a SiC MOSFET model based on technical merit. The tools and analyses presented in this dissertation provide a means by which engineers can quantitatively assess the impact of model design decisions. Overall, the contributions of this dissertation are expected to improve the SiC MOSFET modeling landscape in two related ways. First, the performance of SiC

MOSFET models is expected to improve, as model designers become more aware of the impact of individual modeling decisions. Second, the availability and accessibility of application- focused SiC MOSFET models is expected to increase, as the model proposed herein is leveraged by application designers and further improved by researchers in subsequent studies.

110

REFERENCES

[1] K. Armstrong, S. Das, and J. Cresko, “Wide Bandgap Semiconductor Opportunities in Power Electronics,” Oak Ridge, TN, 2017. doi: ORNL/TM-2017/702.

[2] I. C. Kizilyalli, E. P. Carlson, D. W. Cunningham, J. S. Manser, and A. Y. Liu, “Wide Band-Gap Semiconductor Based Power Electronics for Energy Efficiency,” Washington, DC, 2018. [Online]. Available: https://arpa-e.energy.gov/sites/default/files/documents/ files/ARPA-E_Power_Electronics_Paper-April2018.pdf.

[3] L. M. Tolbert et al., “Power Electronics for Distributed Energy Systems and Transmission and Distribution Applications,” Oak Ridge, Tennessee, 2005. doi: ORNL/TM-2005/230.

[4] X. She, A. Q. Huang, O. Lucia, and B. Ozpineci, “Review of Silicon Carbide Power Devices and Their Applications,” IEEE Trans. Ind. Electron., vol. 64, no. 10, pp. 8193– 8205, 2017, doi: 10.1109/TIE.2017.2652401.

[5] P. Roussel, “SiC market and industry update,” in Int. SiC Power Electron. Appl. Workshop, Kista, Sweden, 2011.

[6] J. Millan, P. Godignon, X. Perpina, A. Perez-Tomas, and J. Rebollo, “A survey of wide bandgap power semiconductor devices,” IEEE Trans. Power Electron., vol. 29, no. 5, pp. 2155–2163, 2014, doi: 10.1109/TPEL.2013.2268900.

[7] B. Wrzecionko, J. Biela, and J. W. Kolar, “SiC power semiconductors in HEVs: Influence of junction temperature on power density, chip utilization and efficiency,” in 2009 35th Annual Conference of IEEE Industrial Electronics, Porto, Portugal, 2009, pp. 3834–3841, doi: 10.1109/IECON.2009.5415122.

[8] Yole Group, “GaN and SiC Power Devices: Market Overview,” Munich, Germany, 2018.

[9] C. Blake and C. Bull, “IGBT or MOSFET: Choose wisely,” 2018. [Online]. Available: https://www.infineon.com/dgdl/Infineon-IGBT_or_MOSFET_Choose_Wisely-Article- v01_00-EN.pdf?fileId=5546d462533600a40153574048b73edc.

[10] Roll2Rail, “New generation power semiconductor - Common specification for traction and market analysis, technology roadmap, and value cost prediction,” Brussels, Belgium, 2016. doi: R2R-T1.1-D-BTS-030-07.

[11] Yole Group, “Power SiC: Materials, Devices, and Applications,” 2019.

111

[12] K. Li, P. Evans, and M. Johnson, “Using Multi Time-Scale Electro-thermal Simulation Approach to Evaluate SiC-MOSFET Power Converter in Virtual Prototyping Design Tool,” in 2017 IEEE 18th Workshop on Control and Modeling for Power Electronics (COMPEL), Stanford, CA, 2017, pp. 1–8, doi: 10.1109/COMPEL.2017.8013278.

[13] P. Sochor, A. Huerner, R. Elpelt, and I. T. Ag, “A Fast and Accurate SiC MOSFET Compact Model for Virtual Prototyping of Power Electronic Circuits,” in PCIM Europe 2019; International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, Nuremberg, Germany, 2019, pp. 1–8.

[14] A. Stupar, T. McRae, N. Vukadinovic, A. Prodic, and J. A. Taylor, “Multi-Objective Optimization of Multi-Level DC-DC Converters using Geometric Programming,” IEEE Trans. Power Electron., vol. 34, no. 12, pp. 11912–11939, 2019, doi: 10.1109/TPEL.2019.2908826.

[15] R. Spence and S. R. Soin, Tolerance Design of Electronic Circuits. London: Imperial College Press, 1997.

[16] H. Sakairi, T. Yanagi, H. Otake, N. Kuroda, and H. Tanigawa, “Measurement Methodology for Accurate Modeling of SiC MOSFET Switching Behavior over Wide Voltage and Current Ranges,” IEEE Trans. Power Electron., vol. 33, no. 9, pp. 7314– 7325, 2018, doi: 10.1109/TPEL.2017.2764632.

[17] J. Allmeling and N. Felderer, “Sub-cycle average models with integrated diodes for real- time simulation of power converters,” in 2017 IEEE Southern Power Electronics Conference (SPEC), Puerto Varas, 2017, pp. 1–6, doi: 10.1109/SPEC.2017.8333566.

[18] P. Yi, Y. Cui, A. Vang, and L. Wei, “Investigation and evaluation of high power SiC MOSFETs switching performance and overshoot voltage,” in 2018 IEEE Applied Power Electronics Conference and Exposition (APEC), San Antonio, TX, 2018, pp. 2589–2592, doi: 10.1109/APEC.2018.8341382.

[19] S. K. Powell, N. Goldsman, J. M. McGarrity, J. Bernstein, C. J. Scozzie, and A. Lelis, “Physics-based numerical modeling and characterization of 6H-silicon-carbide metal- oxide-semiconductor field-effect transistors,” J. Appl. Phys., vol. 92, no. 7, pp. 4053– 4061, 2002, doi: 10.1063/1.1499523.

[20] G. D. Licciardo, L. Di Benedetto, and S. Bellone, “Modeling of the SiO2/SiC Interface- Trapped Charge as a Function of the Surface Potential in 4H-SiC Vertical-DMOSFET,” IEEE Trans. Electron Devices, vol. 63, no. 4, pp. 1783–1787, 2016, doi: 10.1109/TED.2016.2531796.

[21] Y. Ren, M. Xu, J. Zhou, and F. C. Lee, “Analytical loss model of power MOSFET,” IEEE Trans. Power Electron., vol. 21, no. 2, pp. 310–319, 2006, doi: 10.1109/TPEL.2005.869743.

112

[22] J. H. Allmeling and W. P. Hammer, “PLECS-piece-wise linear electrical circuit simulation for Simulink,” in Proceedings of the IEEE 1999 International Conference on Power Electronics and Drive Systems. PEDS’99 (Cat. No.99TH8475), Hong Kong, 1999, vol. 1, pp. 355–360, doi: 10.1109/PEDS.1999.794588.

[23] H. A. Mantooth, K. Peng, E. Santi, and J. L. Hudgins, “Modeling of Wide Bandgap Power Semiconductor Devices—Part I,” IEEE Trans. Electron Devices, vol. 62, no. 2, pp. 423– 433, Feb. 2015, doi: 10.1109/TED.2014.2368274.

[24] B. N. Pushpakaran, S. B. Bayne, and A. A. Ogunniyi, “Electro-Thermal Transient Simulation of Silicon Carbide Power MOSFET,” in Digest of Technical Papers-IEEE International Pulsed Power Conference, 2013, pp. 1–6, doi: 10.1109/PPC.2013.6627596.

[25] H. Jiang, J. Wei, X. Dai, M. Ke, I. Deviny, and P. Mawby, “SiC Trench MOSFET with Shielded Fin-Shaped Gate to Reduce Oxide Field and Switching Loss,” IEEE Electron Device Letters, vol. 37, no. 10, pp. 1324–1327, 2016, doi: 10.1109/LED.2016.2599921.

[26] M. Okawa, R. Aiba, T. Kanamori, H. Yano, N. Iwamuro, and S. Harada, “Experimental and Numerical Investigations of Short-Circuit Failure Mechanisms for State-of-the-Art 1.2kV SiC Trench MOSFETs,” in 2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD), Shanghai, China, 2019, pp. 167–170, doi: 10.1109/ISPSD.2019.8757617.

[27] G. Romano et al., “Short-circuit failure mechanism of SiC power MOSFETs,” in 2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC’s (ISPSD), Hong Kong, 2015, pp. 345–348, doi: 10.1109/ISPSD.2015.7123460.

[28] T. Quarles, A. R. Newton, D. O. Pederson, and A. Sangiovanni-Vincentelli, “Spice3 User Manual,” Berkeley, CA, 1993. doi: 10.1073/pnas.0703993104.

[29] Synopsis, “SaberRD: Integrated Environment for Simulation and Modeling.” https://www.synopsys.com/verification/virtual-prototyping/saber.html (accessed Oct. 07, 2020).

[30] Keysight Technology, “PathWave Advanced Design System (ADS): Power Electronics.” https://www.keysight.com/us/en/products/software/pathwave-design-software/pathwave- advanced-design-system/pathwave-ads-power-electronics.html (accessed Oct. 07, 2020).

[31] Gary Smith EDA, “IC CAD MArket Trends 2015: Developments of Multi-CAD Models,” 2015. [Online]. Available: http://www.garysmitheda.com/wp- content/uploads/2016/02/GSEDA_MT_ICCAD2015.pdf.

[32] L. Chua and P.-M. Lin, Compter Aided Analysis of Electronic Circuits: Algorithms & Computational Techniques. Englewood Cliffs, NJ: Prentic-Hall, Inc., 1975.

[33] C. He et al., “A physically based scalable SPICE model for silicon carbide power MOSFETs,” in 2017 IEEE Applied Power Electronics Conference and Exposition (APEC), Tampa, FL, 2017, pp. 2678–2684, doi: 10.1109/APEC.2017.7931077.

113

[34] T. H. Duong, J. M. Ortiz, D. W. Berning, A. R. Hefner, S. H. Ryu, and J. W. Palmour, “Electro-thermal simulation of 1200 V 4H-SiC MOSFET short-circuit SOA†,” in 2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC’s (ISPSD), Hong Kong, 2015, pp. 217–220, doi: 10.1109/ISPSD.2015.7123428.

[35] X. Zhao, H. Li, Y. Wang, Z. Zhou, K. Sun, and Z. Zhao, “A Temperature-dependent PSpice Short-circuit Model of SiC MOSFET,” 2019 IEEE Work. Wide Bandgap Power Devices Appl. Asia (WiPDA Asia), pp. 1–5, 2019, doi: 10.1109/wipdaasia.2019.8760311.

[36] C. He, J. Victory, Y. Xiao, H. De Vleeschouwer, E. Zheng, and Z. Hu, “SiC MOSFET Corner and Statistical SPICE Model Generation,” in 2020 32nd International Symposium on Power Semiconductor Devices and ICs (ISPSD), Vienna, Austria, 2020, no. 1, pp. 154– 157, doi: 10.1109/ispsd46842.2020.9170091.

[37] H. Li, X. Zhao, K. Sun, Z. Zhao, G. Cao, and T. Q. Zheng, “A Non-Segmented PSpice Model of SiC mosfet with Temperature-Dependent Parameters,” IEEE Trans. Power Electron., vol. 34, no. 5, pp. 4603–4612, 2019, doi: 10.1109/TPEL.2018.2865611.

[38] A. Endruschat, C. Novak, H. Gerstner, T. Heckel, C. Joffe, and M. Marz, “A Universal SPICE Field-Effect Transistor Model Applied on SiC and GaN Transistors,” IEEE Trans. Power Electron., vol. 34, no. 9, pp. 9131–9145, 2019, doi: 10.1109/TPEL.2018.2889513.

[39] M. Mudholkar, S. Ahmed, M. N. Ericson, S. S. Frank, C. L. Britton, and H. A. Mantooth, “Datasheet Driven Silicon Carbide Power MOSFET Model,” IEEE Trans. Power Electron., vol. 29, no. 5, pp. 2220–2228, 2014, doi: 10.1109/TPEL.2013.2295774.

[40] P. Alexakis, O. Alatise, R. Li, and P. Mawby, “Modeling Power Converters using Hard Switched Silicon Carbide MOSFETs and Schottky Barrier Diodes Petros,” in 2013 15th European Conference on Power Electronics and Applications (EPE), Lille, France, 2013, pp. 1–9, doi: 10.1109/EPE.2013.6631758.

[41] M. Alhalabi, A. Rashed, N. B. Iqbal, and A. Al Tarabsheh, “Modelling of SiC Power MOSFET in Matlab, Simulink, and LTSpice,” in 2018 IEEE International Conference on Environment and Electrical Engineering and 2nd Industrial and Commercial Power Systems, Palermo, Italy, 2018, doi: 10.1109/EEEIC.2018.8494204.

[42] CREE Inc., “SpeedFit 2.0 Design SimulatorTM.” https://www.wolfspeed.com/speedfit/ (accessed Oct. 07, 2020).

[43] Infineon Technologies, “Infineon’s IGBT Simulation Tools.” https://www.infineon.com/cms/en/tools/landing/igbt.html (accessed Oct. 07, 2020).

[44] GaN Systems, “GaN Systems Circuit Simulation Tools.” https://gansystems.com/design- center/circuit-simulation-tools/ (accessed Oct. 07, 2020).

[45] J. Allmeling, W. Hammer, and J. Schönberger, “Transient simulation of magnetic circuits using the permeance-capacitance analogy,” 2012 IEEE 13th Work. Control Model. Power Electron. COMPEL 2012, 2012, doi: 10.1109/COMPEL.2012.6251786.

114

[46] K. Rouzbehi et al., “Comparative efficiency study of single phase photovoltaic grid connected inverters using PLECS®,” in 2015 International Congress on Technology, Communication and Knowledge (ICTCK), Mashhad, Iran, 2015, pp. 536–541, doi: 10.1109/ICTCK.2015.7582725.

[47] G. Y. Choe, J. S. Kim, B. K. Lee, C. Y. Won, J. S. Kim, and J. S. Shim, “Design of photovoltaic generation system using PLECS,” in INTELEC 2009 - 31st International Telecommunications Energy Conference, Incheon, South Korea, 2009, pp. 1–4, doi: 10.1109/INTLEC.2009.5351925.

[48] M. Zhu, L. Xia, Y. Hu, W. Zhang, D. Ji, and X. Song, “Design of impacted flexible actuator’s servo controller’s heat sink based on PLECS,” in 2017 First International Conference on Electronics Instrumentation & Information Systems (EIIS), Harbin, China, 2017, pp. 1–5, doi: 10.1109/EIIS.2017.8298630.

[49] J. Allmeling, N. Felderer, and M. Luo, “High Fidelity Real-Time Simulation of Multi- Level Converters,” in 2018 International Power Electronics Conference (IPEC - Niigata 2018 - ECCE Asia), Niigata, Japan, 2018, pp. 2199–2203, doi: 10.23919/IPEC.2018.8508021.

[50] J. Allmeling, “Model Continuity: From Offline Simulation to Real-Time Testing,” EE Times, Europe, Nov. 2019.

[51] A. N. Lemmon, A. D. Brovont, C. D. New, B. W. Nelson, and B. T. Deboi, “Modeling and Validation of Common-Mode Emissions in Wide Bandgap-Based Converter Structures,” IEEE Trans. Power Electron., vol. 35, no. 8, pp. 8034–8049, 2020, doi: 10.1109/TPEL.2019.2963883.

[52] A. D. Brovont, A. N. Lemmon, C. New, B. W. Nelson, and B. T. Deboi, “Analysis and Cancellation of Leakage Current through Power Module Baseplate Capacitance,” IEEE Trans. Power Electron., vol. 35, no. 5, pp. 4678–4688, 2020, doi: 10.1109/TPEL.2019.2944410.

[53] H. W. Ott, Electromagnetic Compatibility Engineering, 1st ed. Hoboken, New Jersey: John Wiley & Sons, Inc., 2009.

[54] Y. Liu, K. Y. See, S. Yin, R. Simanjorang, A. K. Gupta, and J. S. Lai, “Equivalent circuit model of high power density SiC converter for common-mode conducted emission prediction and analysis,” IEEE Electromagn. Compat. Mag., vol. 8, no. 1, pp. 67–74, 2019, doi: 10.1109/MEMC.2019.8681373.

[55] S. Ohn et al., “Three Terminal Common-Mode EMI Model and EMI Mitigation Strategy for Full SiC UPS,” in 2018 IEEE Energy Conversion Congress and Exposition (ECCE), Portland, OR, 2018, pp. 2094–2101, doi: 10.1109/ECCE.2018.8557578.

[56] S. Sandler, Switch-Mode Power Supply Simulation Designing with SPICE 3, Chapter 10, 2nd ed. New York, NY: McGraw-Hill Education, 2006.

115

[57] J. Flicker et al., “Module-level paralleling of vertical GaN PiN diodes,” in 2016 IEEE 4th Workshop on Wide Bandgap Power Devices and Applications (WiPDA), Fayetteville, AR, 2016, pp. 139–142, doi: 10.1109/WiPDA.2016.7799925.

[58] A. Borghese et al., “Effect of Parameters Variability on the Performance of SiC MOSFET Modules,” in 2018 IEEE International Conference on Electrical Systems for Aircraft, Railway, Ship Propulsion and Road Vehicles & International Transportation Electrification Conference (ESARS-ITEC), Nottingham, 2019, pp. 1–5, doi: 10.1109/ESARS-ITEC.2018.8607593.

[59] H. Li et al., “Influences of Device and Circuit Mismatches on Paralleling Silicon Carbide MOSFETs,” IEEE Trans. Power Electron., vol. 31, no. 1, pp. 621–634, 2016, doi: 10.1109/TPEL.2015.2408054.

[60] R. Azar, F. Udrea, W. T. Ng, F. Dawson, W. Findlay, and P. Waind, “The Current Sharing Optimization of Paralleled IGBTs in a Power Module Tile Using a PSpice Frequency Dependent Impedance Model,” IEEE Trans. Power Electron., vol. 23, no. 1, pp. 206–217, 2008, doi: 10.1109/TPEL.2007.909182.

[61] T. López and R. Elferich, “Current sharing of paralleled power MOSFETs at PWM operation,” in 2006 37th IEEE Power Electronics Specialists Conference, Jeju, South Korea, 2006, pp. 1–7, doi: 10.1109/PESC.2006.1711923.

[62] Y. Mao, Z. Miao, C. M. Wang, and K. D. T. Ngo, “Passive Balancing of Peak Currents Between Paralleled MOSFETs With Unequal Threshold Voltages,” IEEE Trans. Power Electron., vol. 32, no. 5, pp. 3273–3277, 2017, doi: 10.1109/TPEL.2016.2646323.

[63] X. Liao, H. Li, Z. Huang, and K. Wang, “Voltage Overshoot Suppression for SiC MOSFET-Based DC Solid-State Circuit Breaker,” IEEE Trans. Components, Packag. Manuf. Technol., vol. 9, no. 4, pp. 649–660, 2019.

[64] Z. Chen, “Characterization and Modeling of High-Switching-Speed Behavior of SiC Active Devices,” M.S. thesis, Bradley Dept. Elect. Comput. Eng., Virginia Polytech. Inst., Blacksburg, VA, USA, 2009.

[65] B. Hughes et al., “Normally-off GaN-on-Si multi-chip module boost converter with 96% efficiency and low gate and drain overshoot,” in 2014 IEEE Applied Power Electronics Conference and Exposition - APEC 2014, Fort Worth, TX, 2014, pp. 484–487, doi: 10.1109/APEC.2014.6803352.

[66] B. T. DeBoi and A. N. Lemmon, “Bus Snubber Optimization for Multi-Chip Power Modules using SPICE Simulations,” in 2019 IEEE International Workshop on Integrated Power Packaging (IWIPP), Toulouse, France, 2019, pp. 125–130, doi: 10.1109/IWIPP.2019.8799089.

[67] S. Ji et al., “Short circuit characterization of 3rd generation 10 kV SiC MOSFET,” in 2018 IEEE Applied Power Electronics Conference and Exposition (APEC), San Antonio, TX, 2018, pp. 2775–2779, doi: 10.1109/APEC.2018.8341410.

116

[68] Y. Shi, R. Xie, L. Wang, Y. Shi, and H. Li, “Short-circuit protection of 1200V SiC MOSFET T-type module in PV inverter application,” in 2016 IEEE Energy Conversion Congress and Exposition (ECCE), Milwaukee, WI, 2016, pp. 1–5, doi: 10.1109/ECCE.2016.7855428.

[69] H. Li, Y. Wang, X. Zhao, K. Sun, Z. Zhou, and Y. Xu, “A Junction Temperature-based PSpice Short-circuit Model of SiC MOSFET Considering Leakage Current,” in IECON 2019 - 45th Annual Conference of the IEEE Industrial Electronics Society, Lisbon, Portugal, 2019, pp. 5095–5100, doi: 10.1109/IECON.2019.8927663.

[70] L. Ceccarelli, R. Kotecha, F. Iannuzzo, and A. Mantooth, “Fast Electro-thermal Simulation Strategy for SiC MOSFETs Based on Power Loss Mapping,” in 2018 IEEE International Power Electronics and Application Conference and Exposition (PEAC), Shenzhen, China, 2018, pp. 1–6, doi: 10.1109/PEAC.2018.8590288.

[71] T. Liu, Y. Zhou, Y. Feng, T. T. Y. Wong, and Z. John Shen, “Experimental and Modeling Comparison of Different Damping Techniques to Suppress Switching Oscillations of SiC MOSFETs,” in 2018 IEEE Energy Conversion Congress and Exposition (ECCE), Portland, OR, 2018, pp. 7024–7031, doi: 10.1109/ECCE.2018.8557872.

[72] D. Foty, “MOSFET Modeling for Circuit Simulation: Requiem or Recovery?,” in ECCTD’01 - European Conference on Circuit Theory and Design, Espoo, Finland, 2001, pp. 1–5, doi: 10.1109/101.708477.

[73] Y. Mukunoki et al., “Characterization and Modeling of a 1.2-kV 30-A Silicon-Carbide MOSFET,” IEEE Trans. Electron Devices, vol. 63, no. 11, pp. 4339–4345, 2016, doi: 10.1109/TED.2016.2606424.

[74] K. Chen, Z. Zhao, L. Yuan, T. Lu, and F. He, “The Impact of Nonlinear Junction Capacitance on Switching Transient and Its Modeling for SiC MOSFET,” IEEE Trans. Electron Devices, vol. 62, no. 2, pp. 333–338, 2015, doi: 10.1109/TED.2014.2362657.

[75] H. L. Yeo and K. J. Tseng, “Modelling Technique utilizing Modified Sigmoid Functions for Describing Power Transistor Device Capacitances Applied on GaN HEMT and Silicon MOSFET,” in 2016 IEEE Applied Power Electronics Conference and Exposition (APEC), Long Beach, CA, 2016, pp. 3107–3114, doi: 10.1109/APEC.2016.7468308.

[76] Y. Cui, M. Chinthavali, and L. M. Tolbert, “Temperature dependent Pspice model of silicon carbide power MOSFET,” in 2012 Twenty-Seventh Annual IEEE Applied Power Electronics Conference and Exposition (APEC), Orlando, FL, 2012, pp. 1698–1704, doi: 10.1109/APEC.2012.6166050.

[77] J. Wang et al., “Characterization, Modeling, and Application of 10-kV SiC MOSFET,” IEEE Trans. Electron Devices, vol. 55, no. 8, pp. 1798–1806, 2008, doi: 10.1109/TED.2008.926650.

117

[78] Z. Duan, T. Fan, X. Wen, and D. Zhang, “Improved SiC Power MOSFET Model Considering Nonlinear Junction Capacitances,” IEEE Trans. Power Electron., vol. 33, no. 3, pp. 2509–2517, 2018, doi: 10.1109/TPEL.2017.2692274.

[79] S. Yin et al., “An Accurate Subcircuit Model of SiC Half-Bridge Module for Switching- Loss Optimization,” IEEE Trans. Ind. Appl., vol. 53, no. 4, pp. 3840–3848, 2017, doi: 10.1109/TIA.2017.2691734.

[80] Y. Mukunoki et al., “Modeling of a Silicon-Carbide MOSFET with Focus on Internal Stray Capacitances and Inductances, and Its Verification,” IEEE Trans. Ind. Appl., vol. 54, no. 3, pp. 2588–2597, 2018, doi: 10.1109/TIA.2018.2796587.

[81] M. Riccio, V. D’Alessandro, G. Romano, L. Maresca, G. Breglio, and A. Irace, “A Temperature-Dependent SPICE Model of SiC Power MOSFETs for Within and Out-of- SOA Simulations,” IEEE Trans. Power Electron., vol. 33, no. 9, pp. 8020–8029, 2018, doi: 10.1109/TPEL.2017.2774764.

[82] V. D’Alessandro et al., “SPICE Modeling and Dynamic Electrothermal Simulation of SiC Power MOSFETs,” Proc. Int. Symp. Power Semicond. Devices ICs, pp. 285–288, 2014, doi: 10.1109/ISPSD.2014.6856032.

[83] Y. Mukunoki et al., “An Improved Compact Model for a Silicon-Carbide MOSFET and Its Application to Accurate Circuit Simulation,” IEEE Trans. Power Electron., vol. 33, no. 11, pp. 9834–9842, 2018, doi: 10.1109/TPEL.2018.2796583.

[84] W. R. Curtice, “A MESFET Model for Use in the Design of GaAs Integrated Circuits,” IEEE Trans. Microw. Theory Tech., vol. 28, no. 5, pp. 448–456, 1980, doi: 10.1109/TMTT.1980.1130099.

[85] D. Cittanti, F. Iannuzzo, E. Hoene, and K. Klein, “Role of Parasitic Capacitances in Power MOSFET Turn-on Switching Speed Limits: a SiC Case Study Davide,” in 2017 IEEE Energy Conversion Congress and Exposition (ECCE), Cincinnati, OH, Oct. 2017, pp. 1387–1394, doi: 10.1109/ECCE.2017.8095952.

[86] D. Diaz, M. Vasic, O. Garcia, J. A. Oliver, P. Alou, and J. A. Cobos, “Hybrid Behavioral- Analytical Loss Model for a High Frequency and Low Load DC-DC Buck Converter,” in 2012 IEEE Energy Conversion Congress and Exposition (ECCE), Raleigh, NC, 2012, pp. 4288–4294, doi: 10.1109/ECCE.2012.6342239.

[87] E. Santi, K. Peng, H. A. Mantooth, and J. L. Hudgins, “Modeling of Wide-Bandgap Power Semiconductor Devices - Part II,” IEEE Trans. Electron Devices, vol. 62, no. 2, pp. 434– 442, 2015, doi: 10.1109/TED.2014.2373373.

[88] T. R. McNutt, A. R. Hefner, H. A. Mantooth, D. Berning, and S. H. Ryu, “Silicon carbide power MOSFET model and parameter extraction sequence,” in IEEE 34th Annual Conference on Power Electronics Specialist, 2003. PESC ’03, Acapulco, Mexico, 2003, vol. 1, pp. 217–226, doi: 10.1109/TPEL.2006.889890.

118

[89] T. R. McNutt, A. R. Hefner, H. A. Mantooth, D. Berning, and S. H. Ryu, “Silicon Carbide Power MOSFET Model and Parameter Extraction Sequence,” IEEE Trans. Power Electron., vol. 22, no. 2, pp. 353–363, 2007, doi: 10.1109/TPEL.2006.889890.

[90] M. Hasanuzzaman, S. K. Islam, L. M. Tolbert, and B. Ozpineci, “Model simulation and verification of a vertical double implanted (DIMOS) transistor in 4H-SIC,” in Proceedings of the IASTED Multi-Conference - Power and Energy Systems, Palm Springs, CA, 2003, vol. 7, pp. 313–316.

[91] M. D. Hasanuzzaman, S. K. Islam, L. M. Tolbert, and B. Ozpineci, “Design, modeling, testing, and spice parameter extraction of DIMOS transistor in 4H-silicon carbide,” Int. J. High Speed Electron. Syst., vol. 16, no. 2, pp. 733–746, 2006, doi: 10.1142/S0129156406003989.

[92] R. Fu, A. Grekov, J. Hudgins, A. Mantooth, and E. Santi, “Power SiC DMOSFET Model Accounting for Nonuniform Current Distribution in JFET Region,” IEEE Trans. Ind. Appl., vol. 48, no. 1, pp. 181–190, 2012, doi: 10.1109/TIA.2011.2175678.

[93] M. Mudholkar, M. Saadeh, and H. A. Mantooth, “A datasheet driven power MOSFET model and parameter extraction procedure for 1200V, 20A SiC MOSFETs,” Proceedings of the 2011 14th European Conference on Power Electronics and Applications. Birmingham, UK, pp. 1–10, 2011.

[94] M. M. Hossain, L. Ceccarelli, A. U. Rashid, R. M. Kotecha, and H. A. Mantooth, “An Improved Physics-based LTSpice Compact Electro-Thermal Model for a SiC Power MOSFET with Experimental Validation,” in IECON 2018 - 44th Annual Conference of the IEEE Industrial Electronics Society, Washington, DC, Oct. 2018, pp. 1011–1016, doi: 10.1109/IECON.2018.8592522.

[95] K. Peng, S. Eskandari, and E. Santi, “Characterization and modeling of SiC MOSFET body diode,” in 2016 IEEE Applied Power Electronics Conference and Exposition (APEC), Long Beach, CA, 2016, pp. 2127–2135, doi: 10.1109/APEC.2016.7468161.

[96] S. Diao et al., “Multi-Dimensional Models of SiC Power MOSFET for Accurately Predicting the Characteristics,” CES Trans. Electr. Mach. Syst., vol. 1, no. 3, pp. 300–305, 2017, doi: 10.23919/TEMS.2017.8086109.

[97] W. Jouha, A. El Oualkadi, P. Dherbecourt, E. Joubert, and M. Masmoudi, “Silicon Carbide Power MOSFET Model: An Accurate Parameter Extraction Method Based on the Levenberg-Marquardt Algorithm,” IEEE Trans. Power Electron., vol. 33, no. 11, pp. 9130–9133, 2018, doi: 10.1109/TPEL.2018.2822939.

[98] M. Shintani, Y. Nakamura, K. Oishi, M. Hiromoto, T. Hikihara, and T. Sato, “Surface- Potential-Based Silicon Carbide Power MOSFET Model for Circuit Simulation,” IEEE Trans. Power Electron., vol. 33, no. 12, pp. 10774–10783, 2018, doi: 10.1109/TPEL.2018.2805808.

119

[99] I. Angelov, V. Desmaris, K. Dynefors, P. Å. Nilsson, N. Rorsman, and H. Zirath, “On the large-signal modelling of AlGaN/GaN HEMTs and SiC MESFETs,” in European Gallium Arsenide and Other Semiconductor Application Symposium, GAAS 2005, Paris, France, 2005, pp. 309–312.

[100] R. Fu, E. Santi, and Y. Zhang, “Power SiC MOSFET Model with Simplified Description of Linear and Saturation Operating Regions,” in 2015 9th International Conference on Power Electronics and ECCE Asia (ICPE-ECCE Asia), Seoul, South Korea, 2015, pp. 190–195, doi: 10.1109/ICPE.2015.7167785.

[101] A. P. Arribas, F. Shang, M. Krishnamurthy, and K. Shenai, “Simple and Accurate Circuit Simulation Model for SiC Power MOSFETs,” IEEE Trans. Electron Devices, vol. 62, no. 2, pp. 449–457, 2015, doi: 10.1109/TED.2014.2384277.

[102] H. Shichman and D. A. Hodges, “Modeling and Simulation of Insulated-Gate Field-Effect Transistor Switching Circuits,” IEEE J. Solid-State Circuits, vol. 3, no. 3, pp. 285–289, 1968, doi: 10.1109/JSSC.1968.1049902.

[103] T. Sakurai and A. R. Newton, “A Simple Short-Channel MOSFET Model and Its Application to Delay Analysis of Inverters and Series-Connected MOSFETs,” in IEEE International Symposium on Circuits and Systems, New Orleans, LA, 1990, pp. 105–108, doi: 10.1109/ISCAS.1990.111928.

[104] N. Phankong, T. Funaki, and T. Hikihara, “A Static and Dynamic Model for a Silicon Carbide Power MOSFET,” in 2009 13th European Conference on Power Electronics and Applications, Barcelona, Spain, 2009, vol. 1, pp. 1–10.

[105] N. Phankong, T. Yanagi, and T. Hikihara, “Evaluation of Inherent Elements in a SiC Power MOSFET by Its Equivalent Circuit,” in Proceedings of the 2011 14th European Conference on Power Electronics and Applications, Birmingham, UK, 2011, pp. 1–8.

[106] J. Lu, K. Sun, H. Wu, Y. Xing, and L. Huang, “Modeling of SiC MOSFET with Temperature Dependent Parameters and its Applications,” in 2013 Twenty-Eighth Annual IEEE Applied Power Electronics Conference and Exposition (APEC), Long Beach, CA, 2013, pp. 540–544, doi: 10.1109/APEC.2013.6520262.

[107] K. Sun, H. Wu, J. Lu, Y. Xing, and L. Huang, “Improved Modeling of Medium Voltage SiC MOSFET Within Wide Temperature Range,” IEEE Trans. Power Electron., vol. 29, no. 5, pp. 2229–2237, 2014, doi: 10.1109/TPEL.2013.2273459.

[108] S. Yin, T. Wang, K. J. Tseng, J. Zhao, and X. Hu, “Electro-Thermal Modeling of SiC Power Devices for Circuit Simulation,” in ECON 2013 - 39th Annual Conference of the IEEE Industrial Electronics Society, Vienna, Austria, 2013, pp. 718–723, doi: 10.1109/IECON.2013.6699223.

120

[109] A. Borghese et al., “An Experimentally Verified 3.3 kV SiC MOSFET Model Suitable for High-Current Modules Design,” in 2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD), Shanghai, China, 2019, pp. 215–218, doi: 10.1109/ISPSD.2019.8757576.

[110] Y. Zhou, “SPICE Modeling of SiC MOSFET Considering Interface-Trap Influence,” CPSS Trans. Power Electron. Appl., vol. 3, no. 1, pp. 56–64, 2018, doi: 10.24295/cpsstpea.2018.00006.

[111] B. N. Pushpakaran, S. B. Bayne, G. Wang, and J. Mookken, “Fast and accurate electrothermal behavioral model of a commercial SiC 1200V, 80 mΩ power MOSFET,” in 2015 IEEE Pulsed Power Conference (PPC), Austin, TX, 2015, pp. 1–5, doi: 10.1109/PPC.2015.7296918.

[112] A. J. Sellers, M. R. Hontz, R. Khanna, A. N. Lemmon, and A. Shahabi, “An Automated SPICE Modeling Procedure Utilizing Static and Dynamic Characterization of Power FETs,” in 2018 IEEE Applied Power Electronics Conference and Exposition (APEC), San Antonio, TX, 2018, vol. 2018-March, pp. 255–262, doi: 10.1109/APEC.2018.8341019.

[113] A. J. Sellers, M. R. Hontz, R. Khanna, A. N. Lemmon, B. T. DeBoi, and A. Shahabi, “An Automated Model Tuning Procedure for Optimizing Prediction of Transient and Dispersive Behavior in Wide Bandgap Semiconductor FETs,” IEEE Trans. Power Electron., vol. 35, no. 11, pp. 12252–12263, 2020, doi: 10.1109/tpel.2020.2986928.

[114] S. A. Rizzo, N. Salerno, A. Raciti, G. Bazzano, A. Raffa, and P. Veneziano, “Parameters optimization of a behavioural SPICE model of an automotive grade SiC MOSFET using Particle Swarm Optimization algorithm,” in 2020 International Symposium on Power Electronics, Electrical Drives, Automation and Motion (SPEEDAM), Sorrento, Italy, 2020, pp. 381–386, doi: 10.1109/speedam48782.2020.9161843.

[115] A. Raffa, P. P. Veneziano, A. Manzitto, and G. Bazzano, “A new analog behavioral spice macro model with self-heating effects and 3rd quadrant behavior for silicon carbide power MOSFETs,” in PCIM Europe digital days 2020; International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, Nuremberg, Germany, 2020, pp. 1–8.

[116] M. Bucher, C. Lallement, C. Enz, F. Théodoloz, and F. Krummenacher, “The EPFL-EKV MOSFET Model Equations for Simulation Model Version 2.6,” Electronics Laboratories, Swiss Federal Institute of Technology (EPFL), Lausanne, Switzerland, 1997. [Online]. Available: https://weble.upc.edu/asig/Circuits_Impresos/manuals de l%27orcad/ekv26.pdf.

[117] T. Heckel and L. Frey, “A Novel Charge Based SPICE Model for Nonlinear Device Capacitances,” in 2015 IEEE 3rd Workshop on Wide Bandgap Power Devices and Applications (WiPDA), Blacksburg, VA, 2015, pp. 141–146, doi: 10.1109/WiPDA.2015.7369263.

121

[118] Z. Cheng, H. Peng, and J. Chen, “More Accurate Miller Capacitor Modeling for SiC Switching Characteristic Prediction in High Frequency Applications,” in 2019 IEEE 4th International Future Energy Electronics Conference (IFEEC), Singapore, 2019, doi: 10.1109/IFEEC47410.2019.9015024.

[119] I. Zeltser and S. Ben-Yaakov, “On SPICE Simulation of Voltage-Dependent Capacitors,” IEEE Trans. Power Electron., vol. 33, no. 5, pp. 3703–3710, 2018, doi: 10.1109/TPEL.2017.2766025.

[120] M. Engelhardt, “LTspice® XVII Help File,” Analog Devices Corporation, Norwood, MA, 2018. [Online]. Available: https://www.analog.com/en/design-center/design-tools-and- calculators/ltspice-simulator.html.

[121] K. Kundert, The Designer’s Guide to Spice and Spectre, 1st ed. Dordrecht: Kluwer Academic Publishers, 1995.

[122] C. A. Thompson, “A Study of Numerical Integration Techniques for Use in the Companion Circuit Method of Transient Circuit Analysis,” Purdue University, School of Electrical Engineering, West Lafayette, IN, 1992. [Online]. Available: https://docs.lib.purdue.edu/cgi/viewcontent.cgi?article=1301&context=ecetr.

[123] M. Engelhardt, “SPICE Differentiation,” 2015. https://www.analog.com/en/technical- articles/spice-differentiation.html (accessed May 17, 2020).

[124] Z. Chen, D. Boroyevich, R. Burgos, and F. Wang, “Characterization and modeling of 1.2 kV, 20 A SiC MOSFETs,” in 2009 IEEE Energy Conversion Congress and Exposition, San Jose, CA, 2009, pp. 1480–1487, doi: 10.1109/ECCE.2009.5316106.

[125] A. Shahabi, A. Lemmon, S. Banerjee, and K. Matocha, “Application-Focused Modeling Procedure for 1.2kV SiC MOSFET’s,” in 2017 IEEE Applied Power Electronics Conference and Exposition (APEC), Tampa, FL, 2017, pp. 3515–3521, doi: 10.1109/APEC.2017.7931202.

[126] G. Angelov and M. Hristov, “SPICE Modeling of MOSFETs in Deep Submicron,” in 27th International Spring Seminar on Electronics Technology: Meeting the Challenges of Electronics Technology Progress, 2004., Bankya, Bulgaria, 2004, pp. 257–262, vol. 2, doi: 10.1109/ISSE.2004.1490430.

[127] I. Angelov et al., “Large-signal modelling and comparison of AlGaN/GaN HEMTs and SiC MESFETs,” in 2006 Asia-Pacific Microwave Conference, Yokohama, Japan, 2006, pp. 279–282, doi: 10.1109/APMC.2006.4429422.

[128] CREE, “C2M0025120D Silicon Carbide Power MOSFET C2M MOSFET Technology,” C2M0025120D datasheet, 2015.

122

[129] C. D. New, A. N. Lemmon, B. T. Deboi, B. W. Nelson, J. Zhao, and A. D. Brovont, “Design and Characterization of a Neutral-Point- Clamped Inverter Using Medium- Voltage Silicon Carbide Power Modules,” in 2020 IEEE Applied Power Electronics Conference and Exposition (APEC), New Orleans, LA, 2020.

[130] T. Liang and V. Dinavahi, “Real-Time Device-Level Simulation of MMC-BasedMVDC Traction Power System on MPSoC,” IEEE Trans. Transp. Electrif., vol. 4, no. 2, pp. 626– 641, 2018, doi: 10.1109/TTE.2018.2823059.

[131] CREE Inc., “SiC MOSFET PSPICE Model - Quick Start Guide, Rev 1.7.” pp. 1–9, 2015.

[132] N. Kapre, “SPICE^2 - A Spatial Parallel Architecture for Accelerating the SPICE Circuit Simulator,” PhD Dissertation, California Institute of Technology, Department of Computing and Mathematical Sciences, Pasadena, California, 2010.

[133] T. L. Quarles, “Analysis of Performance and Convergence Issues for Circuit Simulation,” Memorandum No. UCB/ERL M89/42. Electronics Research Laboratory, University of California, Berkeley, 1989, [Online]. Available: https://www2.eecs.berkeley.edu/Pubs/TechRpts/1989/ERL-89-42.pdf.

[134] Keysight Technology, “B1505A Power Device Analyzer/Curve Tracer,” 5990-3853EN datasheet, 2019.

[135] J. Wang, H. S. Chung, and R. T. Li, “Characterization and Experimental Assessment of the Effects of Parasitic Elements on the MOSFET Switching Performance,” IEEE Trans. Power Electron., vol. 28, no. 1, pp. 573–590, 2013, doi: 10.1109/TPEL.2012.2195332.

[136] Keysight Technology, “E4990A Impedance Analyzer 20 Hz to 10/20/30/50/120 MHz,” 5991-3890EN datasheet, 2018.

[137] B. Nelson, A. Lemmon, B. Deboi, M. Olimmah, and K. Olejniczak, “Measurement-Based Modeling of Power Module Parasitics with Increased Accuracy,” in 2020 IEEE Applied Power Electronics Conference and Exposition (APEC), New Orleans, LA, 2020, pp. 1430–1437, doi: 10.1109/APEC39645.2020.9124202.

[138] B. T. DeBoi, A. N. Lemmon, B. W. Nelson, C. D. New, and D. M. Hudson, “Improved Methodology for Parasitic Characterization of High-Performance Power Modules,” IEEE Trans. Power Electron., vol. 35, no. 12, pp. 13400–13408, 2020, doi: 10.1109/tpel.2020.2992332.

[139] A. Lemmon, S. Banerjee, K. Matocha, and L. Gant, “Analysis of packaging impedance on performance of SiC MOSFETs,” in PCIM Europe 2016; International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, Nuremberg, Germany, 2016, pp. 984–991.

[140] A. Dutta and S. S. Ang, “Effects of parasitic parameters on electromagnetic interference of power electronic modules,” in 2017 IEEE Applied Power Electronics Conference and Exposition (APEC), Tampa, FL, 2017, pp. 2706–2710, doi: 10.1109/APEC.2017.7931081.

123

[141] H. Li and S. Munk-Nielsen, “Challenges in switching SiC MOSFET without Ringing,” in PCIM Europe 2014; International Exhibition and Conference for Power Electronics, Intelligent Motion, Renewable Energy and Energy Management, Nuremberg, Germany, 2014, pp. 989–994.

[142] H. Huang, X. Yang, Y. Wen, and Z. Long, “A switching ringing suppression scheme of SiC MOSFET by Active Gate Drive,” in 2016 IEEE 8th International Power Electronics and Motion Control Conference (IPEMC-ECCE Asia), Hefei, China, 2016, pp. 285–291, doi: 10.1109/IPEMC.2016.7512300.

[143] M. Mazzola, M. Rahmani, J. Gafford, A. Lemmon, and R. Graves, “Behavioral modeling for stability in multi-chip power modules,” in 2015 IEEE International Workshop on Integrated Power Packaging (IWIPP), Chicago, IL, 2015, pp. 87–90, doi: 10.1109/IWIPP.2015.7295985.

[144] Keysight Technology, “16047E Test Fixture, Operation and Service Manual,” Document 16047-90040, 2018.

[145] B. W. Nelson, A. N. Lemmon, B. T. Deboi, and T. J. Freeborn, “Modeling and Validation of Fixture-Induced Error for Impedance Measurements,” IEEE Trans. Instrum. Meas., vol. 68, no. 1, pp. 129–137, 2019, doi: 10.1109/TIM.2018.2838858.

124

APPENDIX

A1. Netlist of proposed Model

**************************************************************** **************************************************************** ** ** ** ### ###### ######## ###### ** ** ## ## ## ## ## ## ## ** ** ## ## ## ## ## ** ** ## ## ## ###### ###### ** ** ######### ## ## ## ** ** ## ## ## ## ## ## ## ** ** ## ## ###### ######## ###### ** ** ** **************************************************************** **************************************************************** * * Author: Blake W. Nelson * * The University of Alabama * School of Electrical and Computer Engineering * Last Updated: 2020/10/10 * **************************************************************** ******************** Netlists and Components ******************* ****************************************************************

.SUBCKT C2M0025120D D G S Tj

Rd1 d1 D 1G BRt d1 D R = Rdt(V(Tj)) BIds d1 S I = IdsT(V(G,S),V(d1,S),V(Tj))

*** Body Diode *** Dbody S D bd .model bd d(level=1,Cjo=1f,Is=3.0777e-10,N=4.5838,Rs=0.0107,bv=10000)

*** CV Model *** Cgg G S Q = x*3.0e-9 - 4.0970e-11 + + log(1+exp( 2.2*(x - 1.2)))*5.6e-10 + + log(1+exp( 0.9*(x - 5)))*1.8e-10 + + log(1+exp( 0.8*(x - 9)))*2.5e-10 + + -1*log(1+exp(-3.0*(x + 4.8)))*8.5e-10 + + -1*log(1+exp(-2.4*(x + 6.5)))*5.0e-10 + + -1*log(1+exp(-1.0*(x + 12)))*2.5e-10 + + -1*log(1+exp(-1.0*(x + 9)))*2.0e-10

125

Cgd D G Q = x*1.3e-11 + 8.5907e-09 + + -1*log(1+exp(-3.00*(x + 0)))*1.6e-10 + + -1*log(1+exp(-1.00*(x + 0)))*8.5e-10 + + -1*log(1+exp(-10.0*(x + 0)))*5.0e-11 + + -1*log(1+exp(-0.50*(x - 5.5)))*8.0e-10 + + -1*log(1+exp(-3.00*(x -11.5)))*6.0e-11 + + -1*log(1+exp(-0.09*(x - 25)))*3.1e-10 + + -1*log(1+exp(-0.05*(x - 100)))*1.6e-10 + + -1*log(1+exp(-0.015*(x- 250)))*5.3e-10

Cds D S Q = x*2.16e-10 + 8.2187e-08 + -1*log(1+exp(-0.015*(x- 250)))*1.0e-8 + + -1*log(1+exp(-0.05*(x - 100)))*4.0e-9 + + -1*log(1+exp(-0.09*(x - 25)))*7.0e-9 + + -1*log(1+exp(-0.40*(x -11.5)))*0.9e-9 + + -1*log(1+exp(-0.40*(x - 5.5)))*1.0e-9 + + -1*log(1+exp(-0.80*(x - 1)))*1.3e-9

**************************************************************** ********************** Models and Parameters ***************** **************************************************************** * Conduction Parameters (25 ^C) .param k1 = 20.3106 .param k2 = 0.0918 .param k4 = -0.0087 .param k3 = -4.8429 .param k5 =-16.3450 .func p(Vgs) = table(Vgs, 0, 0, 3.0, 0.1659, 3.5, 0.3599, 4.0, 0.5920, 4.5, 0.8075, 5.0, 0.9837, 5.5, 1.0799, 6.0, 1.1334, 6.5, 1.1455, 7.0, 1.1356, 7.5, 1.1313, 8.0, 1.1443, 8.5, 1.2596, 9.0, 1.2684, 10.0, 1.1803, 11.0, 1.1197, 12.0, 1.0832, 13.0, 1.0700, 14.0, 1.0609, 15.0, 1.0667, 16.0, 1.0789, 17.0, 1.0862, 18.0, 1.0973, 20.0, 1.1187, 30.0, 1.4260) .func q(Vgs) = table(Vgs, 0, 0, 3, 0.5805, 3.5, 0.5845, 4, 0.5484, 4.5, 0.4892, 5, 0.4545, 5.5, 0.3852, 6, 0.3263, 6.5, 0.2751, 7, 0.2332, 7.5, 0.2040, 8, 0.1866, 8.5, 0.1986, 9, 0.1873, 10, 0.1448, 11, 0.1178, 12, 0.1002, 13, 0.0896, 14, 0.0794, 15, 0.0752, 16, 0.0721, 17, 0.0680, 18, 0.0652, 20, 0.0597, 30, 0.0597)

.func IdsT(Vgs,Vds,T1) = Ids(Vgs+Vos(T1),Vds) .func Ids(Vgs,Vds) = Itf(Vgs)*Iout(Vgs,Vds) .func Itf(Vgs) = k1*(1+tanh(k2*(Vgs+k3) + k4*(Vgs+k5)*(Vgs+k5))) .func Iout(Vgs,Vds) = p(Vgs)*Vds/(1+q(Vgs)*Vds)

* Temp Parameters .func Rdt(T1) = TR0*(TR1*(T1-25)+TR2*(T1-25)*(T1-25))+1u .func Vos(T1) = TV1*(T1-25)+TV2*(T1-25)*(T1-25)

.param TR0 = 6.777845e-03 .param TR1 = 1.883542e-02 .param TR2 = 1.002091e-04 .param TV1 = 1.193087e-02 .param TV2 = -2.248858e-05

.ENDS C2M0025120D 126

A2. spicebench: Automated Quantification of Model Runtime

Section 3.3.1 describes a simulation study for the quantification of transistor model run-

time, and details on the specific framework are defined here. Figure 48 gives a graphic overview

of the system developed to carry out the large number of simulations. Specifically, unique

simulations are built by copying an application .asc files (such as the DPT of Figure 7), a MPCM

.asc file (such as the two die in parallel module shown in Figure 10), and a model text file (such

as the non-segmented model) from their respective repositories into a target directory.

Additionally, a text file generated by MATLAB is include in LTspice to define the parameters

used by the simulation. Using the batch command interface of LTspice, simulations can

automatically be initialized by MATLAB. MATLAB then decodes the .raw file to collect that the

transient data and confirm the simulation was successful. Finally, it parses the log file generated

by LTspice to capture the simulation statistics, especially time elapsed.

1st Repo: spicebench: Automated Analysis Toolbox Application Files

Analysis Double Pulse Test 10 4

10 3

10 2

10 1 Runtime [Seconds] nd 10 0

10 -1 2 Repo: 1 2 4 8 16 32 Target Run Parallel Die per Switch

DoubleBuck Converter Pulse Test MCPM Files Directory Simulation .raw .log 10 4 10 3

10 2

10 1 Runtime [Seconds]

10 0

10 -1 11 22 44 8 16 32 Copy Parallel Die per Switch Neutral PointDouble Clamped Pulse Converter Test 10 4

Batch 3 10

10 2

Command 10 1 Runtime [Seconds] rd 10 0 10 -1 3 Repo: 11 22 44 8 16 32 Parallel Die per Switch

DoubleMultilevel Pulse DPT Test Model Files 10 4

10 3

10 2

10 1 Runtime [Seconds] M Iterations N Simulations Collect 10 0

10 -1 Outputs 11 22 44 8 16 32 ParallelSeries Die Die per per Switch Switch

Figure 48. spicebench: Analysis of LTspice simulation run-time using MATLAB This automated toolbox makes the extremely large simulations studies required by this dissertation possible. While minimum requirement of 100 simulations might at first appear

127

excessive, this come from a general underestimation of the variance in LTspice run-time.

Outside of Monte Carlo simulations, circuit parameters are not often changed from their nominal values. If parameters are the unchanged, LTspice will typically solve systems in predictable manner with very low variance in simulation run-time. This, however, is a quirk of the solver; whether a single parameter set is representative of a simulation’s difficulty is questionable. By randomizing circuit parameters (such as parasitic values and voltages), the variance in simulation run-time increases substantially. To draw meaningful conclusions then, many simulations are required. In general, more than 100 simulations were run for each condition, but it was the lowest number accepted for any datapoint on the various run-time results given in this dissertation. Therefore, creating a single datapoint (manufacture model in NPC with 32 die per switch position) required roughly 7 days of continuous simulations time.

A few interesting computation results were also identified well after the simulation parameters were selected. For example, selecting 4 threads (rather than the maximum of 8) can often produce slightly improved run-time results with the i7-7700k. This may indicate that hyperthreading is not beneficial in these SPICE transient simulation or that performance is limited by system memory bandwidth, causing regression when too many parallel tasks are initialized. It is recommended the optimal number of threads is checked on a per simulation basis to avoid wasting computing resources.

Another interesting comparison came from repeating the conduction study results with a workstation which uses dual Xeon CPUs (E5-2640 V4, 2.4 GHz 20 cores). These results could then be compared to the original study conducted on the “benchmark PC” which uses a i7-7700k

(4.2 GHz, 4 cores). Figure 49 shows the direct run-time result for each computer, as well as a run-time comparison metric. In general, the low speed, high core count workstation had lower

128

performance in low complexity simulations. In simulations with more transistor models,

especially in transistors parallel, the workstation PC shows modest improved run-time than the

low core count CPU.

Double Pulse Test Buck Converter Neutral Point Clamped Converter Multilevel DPT 150

100 Gained Performance 50 Equal Perfomance 0

-50 Lost Difference [%]

Performance -100

-150 1 2 4 8 16 32 1 2 4 8 16 32 1 2 4 8 16 32 1 2 4 8 16 32 Parallel Die per Switch Parallel Die per Switch Parallel Die per Switch Series Die per Switch

Double Pulse Test Buck Converter Neutral Point Clamped Converter Multilevel DPT 10 4 1 Hour

10 3

Workstation 2 10 1 Minute Dual Xeon 10 1 2.4 GHz

Runtime [Seconds] 1 Second 20 Core, 40 Thread 10 0

10 -1 1 2 4 8 16 32 1 2 4 8 16 32 1 2 4 8 16 32 1 2 4 8 16 32 Parallel Die per Switch Parallel Die per Switch Parallel Die per Switch Series Die per Switch

Double Pulse Test Buck Converter Neutral Point Clamped Converter Multilevel DPT 10 4 1 Hour

10 3

Benchmark PC 2 10 1 Minute i7-7700k 10 1 4.2 GHz

Runtime [Seconds] 1 Second 4 Core, 8 Thread 10 0

10 -1 1 2 4 8 16 32 1 2 4 8 16 32 1 2 4 8 16 32 1 2 4 8 16 32 Parallel Die per Switch Parallel Die per Switch Parallel Die per Switch Series Die per Switch Non-Segmented Modified Curtice Semi-Physics Physics Manufacturer Figure 49. PC Comparison A3. Parasitic Inductance Extraction

Parasitic inductances in device packages and printed circuit boards significantly alter the

behavior of power electronics systems [64], [135]. A well-known phenomenon caused by parasitic inductances is voltage overshoot [64], [139] at turn-off. Additionally, under-damped, high-frequency oscillation can occur during switching events as energy is exchanged among parasitic inductances and intrinsic device capacitances. This high frequency content increases the

129

electromagnetic emissions of the system [64], [140]–[143]. Thus, accurate models of inductance

are needed to evaluate the influence of parasitic capacitances on system behavior.

The package parasitics of the MOSFET [128] were evaluated with the Keysight E4990A impedance analyzer [136] using with an appropriate fixture from the instrument manufacturer

[144]. Figure 50 shows the package inductance of the C2M0025120D over frequency. First, the drain to source inductance was measured using the methodology published in [137], in which

the MOSFET is gated on during the measurement. Thus, rather than measuring LDS and COSS,

LDS and RDS(ON) were measured (the lower series impedance leads to a more accurate prediction

of LDS [145]). To measure the gate to source inductance, a MOSFET was overvolted (50 V for 1

second) across gate to source causing a breakdown of the insulating layer, bypassing CGS. This

greatly reduced the series impedance of the measurement, again improving the accuracy of the

LGS prediction. The final inductance, from gate to drain, was measured normally, but rather than

estimating the inductance form the self-resonant frequency, the value of LGD at 120 MHz was

selected. The final internal parasitic measured was the parasitic resistance in the MOSFET’s

gate, which was measured with the curve tracer [134].

8 LGD 6

4 LDS Inductance [nH] 2 LGS

0 5 7 10 10 6 10 10 8 Freqeuncy [Hz] Figure 50. Package inductance vs frequency

130

In addition to the package parasitics, test stand parasitics play a key role in the dynamic behavior of the system. Figure 21 shows a schematic overview of the test stand used for DPT in this analysis. The parasitics listed in Table XI were calculated using the methodology proposed in [138]. Figure 51 shows the measured impedance data for the power loop with annotations which can be cross referenced to the schematic. The same methodology was also used to quantify the gate loop parasitic inductance.

] 1

CBANK CDECPL

0.1 LP1 + LP2 LP1 Impedance [

0.01 10 3 10 4 10 5 10 6 10 7 10 8 90

Phase [°] -45

-90 10 3 10 4 10 5 10 6 10 7 10 8 Frequency [Hz]

Figure 51. Test stand impedance

131