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AND9083 Application Note ON Semiconductor Is Now To learn more about onsemi™, please visit our website at www.onsemi.com onsemi and and other names, marks, and brands are registered and/or common law trademarks of Semiconductor Components Industries, LLC dba “onsemi” or its affiliates and/or subsidiaries in the United States and/or other countries. onsemi owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of onsemi product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent-Marking.pdf. onsemi reserves the right to make changes at any time to any products or information herein, without notice. The information herein is provided “as-is” and onsemi makes no warranty, representation or guarantee regarding the accuracy of the information, product features, availability, functionality, or suitability of its products for any particular purpose, nor does onsemi assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Buyer is responsible for its products and applications using onsemi products, including compliance with all laws, regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use onsemi products for any such unintended or unauthorized application, Buyer shall indemnify and holdonsemi and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that onsemi was negligent regarding the design or manufacture of the part. onsemi is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Other names and brands may be claimed as the property of others. AND9083/D MOSFET Gate-Charge Origin and its Applications Introduction Engineers often estimate switching time based on total drive resistances and gate charge or capacitance. Since www.onsemi.com capacitance is non-linear, gate charge is an easier parameter for estimating switching behavior. However, the MOSFET APPLICATION NOTE switching time estimated from datasheet parameters does not normally match what the oscilloscope shows. This is due to differences between the parameters taken from the datasheet and the application conditions. For example, in Figure 1 the 32 V gate charge of NTD5805N was characterized at two different conditions and results varied greatly. If datasheet values are characterized at conditions different from the + user, the differences will introduce error in the estimation. I 0 à 10 V D VDS This article will explain how to better estimate gate charge − from datasheets and their applications. For simplicity in this article, power MOSFET NTD5805N’s datasheet [1] is used + VGS with circuit conditions of 32 V and 30 A. − 10 9 8 I = 30 A, V = 5 V D DS 30 A 7 6 5 ID = 5 A, VDS = 30 V SOURCE VOLTAGE (V) SOURCE VOLTAGE − 4 Figure 2. Inductive Switching TO − 3 2 QSW , GATE 35 1 10 V DS GS V 0 ID 9 , DRAIN V 0 5 10 15 20 25 30 35 DS 30 I D 8 , DRAIN CURRENT (A), QG, TOTAL GATE CHARGE (nC) Q G 25 7 − Figure 1. NTD5805N Gate-to-Source Voltage vs. (V) SOURCE VOLTAGE 6 Total Charge 20 5 VGP SOURCE VOLTAGE (V) SOURCE VOLTAGE 15 Inductive Switching − 4 In switch-mode power supplies, MOSFETs switch TO − 3 10 inductive loads. Figure 2 shows a basic buck circuit with high VTH 2 side MOSFET turn on transition. Before the high side AB C 5 MOSFET is turned on, inductor current is flowing through the , GATE 1 GS V 0 0 low side MOSFET’s body diode (VBD). The turn-on transition 0 10 20 30 is broken down into three regions (Figure 3). These regions QG, TOTAL GATE CHARGE (nC) will be individually explained. Figure 4 shows the transition through these regions in terms of output characteristics. Gate Figure 3. Gate-to-Source Voltage charge can be derived from the non-linear capacitance and Switching vs. Total Charge curves, which are fully characterized at a range of VDS (VGS = 0 V) and VGS (VDS = 0 V) as shown in Figure 5. © Semiconductor Components Industries, LLC, 2016 1 Publication Order Number: February, 2016 − Rev. 2 AND9083/D AND9083/D VGS = 5.5 V − 10 V 100 3000 90 VGS = 5.2 V 2500 80 5 V Ciss 70 2000 60 C 4.5 V 50 1500 40 C 4.2 V B VGP 1000 A 30 , DRAIN CURRENT (A) 4 V C, CAPACITANCE (pF) D Coss I 20 500 A 10 B 3.5 V Crss 0 0 0 1 2 3 30 40 10 5051015 20 25 30 35 40 V V VDS, DRAIN−TO−SOURCE VOLTAGE (V) GS DS GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V) Figure 4. On-Region Characteristics for Different Gate-to-Source Voltages Figure 5. Capacitance Variation Region A: MOSFET QGS Region C: MOSFET Remaining Total Gate Charge This is the region where gate-to-source voltage (VGS) This is the region where the MOSFET enters into ohmic rises from 0 V to its plateau voltage (VGP). When the gate mode operation as seen in the ID−VDS curve (Figure 4). VGS rises from 0 V to its threshold voltage (VTH), the MOSFET rises from VGP to driver supply voltage (VGDR). Both ID and is still off with no drain current (ID) flow and drain-to-source VDS remain relatively constant. ID is still clamped by the voltage (VDS) remains clamped. Once gate voltage reaches inductor current. As VGS increases, the channel VTH, the MOSFET starts conducting and ID rises. Its VDS is (VDS =I*RDS(ON)) continue to be more enhanced and VDS still clamped to VDD +VBD until all inductor current is dropped slightly. The charge needed is shown as region C in being supplied by the MOSFET. In this region, gate current Figure 5 and can be calculated by Equation 3. is used to charge the input capacitance (Ciss) with its VDS V ^ ŕ GDR @ being clamped. Since voltage across gate-to-drain changes QC Ciss(VGS) dV (eq. 3) VGP from VDD to VDD –VGP, charge is stored from the input capacitance curve at that range. It can be approximated by Equation 1. Getting the Gate Charge for Different Conditions It was explained above how different sections of gate V ^ ŕ DD @ charge are formed. Circuit conditions determine gate charge QGS * Ciss(VDS) dV (eq. 1) VDD VGP boundaries between regions A, B and C (Figure 6). The range is set by VDD and VGDR. VGP can be found from Region B: MOSFET QGD ID−VDS curves at inductor current (ID) and supply voltage This is the region where VGS is held at VGP and remains (VDD). With these three voltages found, gate charge equals flat. ID clamps to inductor current and VDS clamping effect to area under those capacitance regions. An example is is gone, MOSFET’s VDS starts to drop. It can be seen from shown in Table 1 employing methodology described the ID−VDS curve (Figure 4) that VGS remains relatively same circuit conditions as characterization data in Figure 1 constant at fixed ID with varying VDS. This is the origin of using only simple estimations. Total gate charge (QGTOT) is the flat plateau seen on the gate charge curve. During this the total amount charge stored by the MOSFET on its gate region, the gate current is used to charge the reverse transfer up to the driver voltage. Switching gate charge (QSW) is the capacitance (Crss). VDS is decreasing from VDD +VBD to amount charge needed to complete ID and VDS transitions. ID *RDS(ON). Thus the voltage across Crss (gate-to-drain capacitance) changes from {(VDD +VBD) − VGP} to {(ID *RDS(ON)) − VGP}. The polarity of voltage is reversed. Charge (Equation 2) needed for this transition is shown as the area under region B capacitance curve of Figure 5. V * V Q ^ ŕ DD GP Crss(V ) @ dV ) GD 0 DS (eq. 2) V ) ŕ GP Crss(V ) @ dV 0 GS www.onsemi.com 2 AND9083/D GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (V) VGS VDS 3000 2500 C 2000 1500 A 1000 C, CAPACITANCE (pF) 500 B 0 VGDR VGP(ID) VDD − VGP(ID) VDD Figure 6. Circuit Parameters Effects Table 1. ESTIMATION OF GATE CHARGE BASED ON METHOD DESCRIBED Parameters VDD = 30 V, ID = 5 A VDD = 5 V, ID = 30 A Refer to VGP 3.6 V 4.2 V ID –VDS Curve Region A − Charge 3.6 V * 1.7 nF ≈ 6.1 nC 4.2 V * 1.9 nF ≈ 8.0 nC Region B − Charge (30 V – 3.6 V) * 0.2 nF + (5 V – 4.2 V) * 0.4 nF + 3.6 V * 1.1 nF ≈ 9.2 nC 3.6 V * 1.1 nF ≈ 4.9 nC Capacitance Curve Region C − Charge (10 V – 3.6 V) * 2.7 nF ≈ 18 nC (10 V – 4.2 V) * 2.7 nF ≈ 15.95 nC QGTOT 33 nC 29 nC Sum A, B & C VTH 2.7 V 2.7 V Datasheet Value QSW (3.6 V – 2.7 V) / 3.6 V * 6.1 nF + (4.2 V – 2.7 V) / 4.2 V * 8.0 nF + QA(after VTH) + QB 9.2 nC ≈ 11 nC 4.9 nC ≈ 7.8 nC Resistive Switching 32 V LED and heating coil are examples of resistive switching.
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