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DC Bias Point of the Common-Source Amplifier N “Common” Means “Grounded” Or More Generally, “Connected to a DC Supply” for Biasing, We

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DC Bias Point of the Common-Source Amplifier N “Common” Means “Grounded” Or More Generally, “Connected to a DC Supply” for Biasing, We Common-Source Amplifier DC Bias Point of the Common-Source Amplifier n “Common” means “grounded” or more generally, “connected to a DC supply” For biasing, we 1. ignore the small-signal source vs and its small-signal resistance: RS --> 0 W 2. ignore the load resistor (since it’s a small-signal resistance, too): RL --> inf. W What is going on with the load resistor RL? DC level of the output voltage is NOT zero ... but A “typical load” does not draw much if any DC current ... because it is non- Where to set VOUT? linear and the load resistor is the load’s small-signal model! What is a “typical load”? EE 105 Fall 2000 Page 1 Week 9 EE 105 Fall 2000 Page 2 Week 9 Graphical “Load-Line” Analysis Small-Signal Model of CS Amplifier The current through RD must equal the drain current. n Substitute parameters at operating point selected so that VOUT» VDD¤ 2 V – V I =-------------------------------DD OUT-= I D RD RD What does this equation mean? n Find two-port parameters of this amplifier: “natural” to use the transconductance form Rin = VOUT Rout = Gm = VBIAS EE 105 Fall 2000 Page 3 Week 9 EE 105 Fall 2000 Page 4 Week 9 Two-Port Model of Common-Source Amplifier Current-Source Supplies n Attach the source and load to find output current as a function of the source n A current source to supply current, rather than a resistor, allows a high DC voltage current for the device with a large incremental (small-signal) resistance The plot of iSUP vs. vSUP is: (note that vSUP must be positive) Infinite input resistance is ideal for a voltage input iSUP Output resistance increases with RD increasing, but DC drain current ID will 1/2 decrease and gm will decrease with ID vSUP EE 105 Fall 2000 Page 5 Week 9 EE 105 Fall 2000 Page 6 Week 9 Common-Source with Current Source Supply Graphical Analysis of CS Amplifier with Current-Source Supply n RD is replaced with idealized current source with internal resistance n For DC bias analysis, the small-signal source (with RS) and the load resistor RL are eliminated, along with the internal resistance roc of the current source The region of input bias voltage VBIAS for which the current source and the MOSFET are in their constant-current regions is extremely small .... VOUT VBIAS EE 105 Fall 2000 Page 7 Week 9 EE 105 Fall 2000 Page 8 Week 9 Common-Source/Current-Source Supply Models p-Channel Common-Source Amplifier n The small-signal model is identical to the resistor supply, except that the current n Source of p-channel is tied to positive supply; current supply sinks ISUP to source’s internal resistance roc replaces RD ground or to lower supply Tradeoffs are different from case of resistor load since ID is now decoupled from the small-signal current supply resistance roc n DC bias: Eliminate small-signal sources; control voltage is VSG = VDD - VBIAS EE 105 Fall 2000 Page 9 Week 9 EE 105 Fall 2000 Page 10 Week 9 p-Channel CS Small-Signal Model Common Gate Amplifiers n p-channel MOSFET small-signal model has the source at the top n Input signal is applied to the source, output is taken from the drain n Summary: current gain is about unity, input resistance is low, output resistance is high a CG stage is a current “buffer” ... it takes a current at the input that may have a relatively small Norton equivalent resistance and replicates it at the output port, which is a good current source due to the high output resistance. Transform this into a circuit with vgs as the control voltage Biasing is very easy ... IBIAS = - ISUP Note that the source can be tied to the bulk if the device is in a well. EE 105 Fall 2000 Page 11 Week 9 EE 105 Fall 2000 Page 12 Week 9 Common-Gate Current Gain Ai Common-Gate Input Resistance Rin n Small-signal circuit, with output shorted (according to the two-port procedure to n Apply test current, with load resistor RL present at the output find Ai) n Add the currents at the input node and set equal to the test current: ævt – voutö it = –gmvgs+gmbvt + ç--------------------÷ èro ø Analysis: iout= id and id =– ig – is =–is = –it n The output voltage = - iout (roc || RL) = - (- it)(roc || RL) (why?) Solving for the short-circuit current gain: ævt – (rocRL)i ö i = g v +g v + -------------------------------------t i t m t mb t ç÷ out èro ø Ai =-------- = –1 it EE 105 Fall 2000 Page 13 Week 9 EE 105 Fall 2000 Page 14 Week 9 Input Resistance (Cont.) Common-Gate Output Resistance Rout n Solve for the ratio of the test voltage to the test current n Test circuit: leave source resistance RS of small-signal source current in place; remove roc for analysis and put it back in at the end ... 1 + (r R )¤ r vt oc L o Rin=----= ---------------------------------------------- it gm +gmb+ (1 ¤ ro) the input resistance is a function of the load resistance RL ... n Evaluate the relative sizes of the terms: gm is around 500 mS gmb is around 50 mS 1/ro is around 5 mS or less, so neglect versus gm + gmb n Circuit analysis exercise: current supply is usually good enough that rocRL @ RL it helps to note that vs = itRS n Kirchhoff’s current law at the source resistor node: sum currents leaving node vt 1 + RL ¤ ro Rin=----= ------------------------- v v – v it gm + gmb s s t ------– gmvgs– (–gmbvs) +-------------- = 0 RS ro What about ratio of RL and ro? It depends ... 1 1 vt v æ------+g +g + ---- ö= ---- sèR m mbr ø r IF RL << ro, then we get a simpler form of the S o o n Substituting vt = it RS and solving for the output resistance = (vt / it ) || roc 1 1 Rin@ ---------------------- » ------ (for roc, ro >> RL) gm + gmb gm Rout= roc(RS[ro ¤ RS +gmro +gmbro + 1]) ... quite a mess EE 105 Fall 2000 Page 15 Week 9 EE 105 Fall 2000 Page 16 Week 9 Common-Gate Output Resistance (Cont.) Common-Gate Two-Port Model n The output resistance is a function of the source resistance RS see Appendix to Chapter 8 for an analysis of the error in using the two-port approach for the common-gate amplifier n Evaluate the relative sizes of the terms: gm is around 500 mS gmb is around 50 mS ro is around 200 kW Design tradeoffs: g r = (0.5)(200) = 100 >> 1 m o Ideal current buffer has Rin = 0 W: need to increase gm to approach this goal n Simplifying Also, an ideal current buffer has Rout = infinity W: increase g r ... and use a good current supply with a large r Rout@ roc([ro +(gmro + gmbro )RS])= roc[r o(1 +(g m + gmb)RS)] m o oc If we neglect the backgate generator (gmb << gm ) Rout@ roc[r o(1 + (g mRS)] n The output resistance of the common-gate can be very large ... on the order of 100 times ro ... if the current supply’s resistance is large enough not to limit it. EE 105 Fall 2000 Page 17 Week 9 EE 105 Fall 2000 Page 18 Week 9 P-Channel Common Gate Amplifier Common-Drain Amplifier n Also called a “source follower” for reasons that will become clear shortly Small-signal model is identical to n-channel version For DC bias, neglect small signal source (and its resistance) and the small-signal load resistance; iSUP = ISUP Note that VOUT= VBIAS– VGS The DC gate-source voltage is: EE 105 Fall 2000 Page 19 Week 9 EE 105 Fall 2000 Page 20 Week 9 DC Transfer Curve DC Transfer Curve for Common-Drain Amps p-well CMOS process means that the source and bulk can be shorted ... not true for an n-well process. VOUT VBIAS Simple idea: slope of transfer curve is the voltage gain ... about 1 The threshold voltage VTn is not a constant, since the source-bulk voltage VSB The common-drain is a voltage buffer increases as VOUT increases: - VTn= VTOn+ gn (VOUT– V )–2fp – 2fp dvOUT Av = -----------------» 1 dvBIAS EE 105 Fall 2000 Page 21 Week 9 EE 105 Fall 2000 Page 22 Week 9 Common-Drain Open-Circuit Voltage Gain Output Resistance of Common-Drain Amplifier For finding Av exactly, remove the source and its resistance and the load resistance n Leave the source resistance attached while exercising the output with a test ... apply a test voltage and find the output voltage voltage KCL at source node: KCL at the source node ... remove ro || roc and put it back in vout -----------------–gm(vt – vout)–(–gmbvout) = 0 it +gm(0 – vt)+(–gmbvt) = 0 rocro æö æv ö v ----------------1 -+g + g = g v R =(r r )----t =(r r )æ---------------------1 - ö= --------------------------------------------------------------1 - outçm mb ÷ m t out o oc ç÷ o oc èø èrocro ø èit ø gm + gmb [1 ¤ (ro roc )]+gm + gmb Typically, ro || roc >> gm + gmb vout gm gm 1 Rout@ ---------------------- Av =--------- = ----------------------------------------------------» ---------------------- g + g vt æ1 ö gm + gmb m mb gm +gmb+ ç-----------------÷ èrocroø EE 105 Fall 2000 Page 23 Week 9 EE 105 Fall 2000 Page 24 Week 9 Common-Drain Small-Signal Model Summary of MOSFET Two-Port Models Input resistance is infinite: open-circuit from gate-source If source and bulk can be shorted (possible for a MOSFET in a well), then the gate is essentially 1 (since backgate generator has zero vsb controlling it.) Output resistance is ideally zero for a voltage-output amplifier: typical values gm = 500 mS gmb = 50 mS 1 Rout= ---------------------- » 2 kW gm + gmb The output resistance can be reduced by increasing the transconductance ..
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