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CMOS-RF Power Amplifier for Wireless Communications

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CMOS-RF Power Amplifier for Wireless Communications FACULDADE DE ENGENHARIA DA UNIVERSIDADE DO PORTO CMOS-RF Power Amplifier for Wireless Communications Daniel José Azevedo Oliveira Final report submitted for fulfillment of the Dissertation in the Integrated Master in Electrical and Computers Engineering Telecommunications Major Supervisor: Vítor Manuel Grade Tavares (PhD) Co-Supervisor: Manuel Cândido Duarte dos Santos (Eng) July 2009 c Daniel José Azevedo Oliveira, 2009 Abstract The present work addresses the study and implementation of a radio-frequency (RF) power amplifier (PA). Several classes of amplification are analyzed, from both the linear and the non- linear classes of amplification. From the non-linear class amplifiers, the current-mode class-D (CMCD) amplifier was the chosen, because it is a zero-voltage-switching (ZVS) amplifier but with a lower peak drain voltage than other ZVS amplifiers, like the class-E amplifier. Since CMOS devices have a low breakdown voltage, having a lower peak drain voltage is an important feature. The ZVS characteristic enables the CMCD to work at higher frequencies ideally without energy losses at each RF cycle, in opposition to its dual counterpart, the voltage-mode class-D (VMCD). Following the basic operation of the CMCD amplifier, a non-linear analysis is made starting with the impact of the load network quality factor, QL, on the amplifier performance. The second part of the non-linear analysis comprises a study to understand the impact of the inductor unloaded quality factor, along with QL, on the PA efficiency. It is concluded that lowering QL by increasing the RLC network inductor size, and decreasing the filter capacitance by the same factor, greatly improves the PA overall performance. A vast set of simulations is presented in this work. First the low QL approach that improves the PA performance is corroborated, achieving nearly 76% of drain efficiency with 16-dBm of output power. A small comparative study between a 90-nm and a 350-nm CMOS technology is also performed, showing that the selected 90-nm technology is better suited to implement the CMCD PA. The NMOS-RF I-V characteristic curves of both technologies are also shown in order to discuss the breakdown voltage of the transistors. The CMCD cascode topology is presented as a solution to increase the output power, sacrific- ing only a small percentage of the drain efficiency. Since with the cascode architecture there are two transistors at each branch, it is possible to raise the supply voltage to higher values than with the basic topology. A layout with the selected 90-nm CMOS technology, of the current-mode class-D PA cascode topology is presented. A group of post-layout simulations is performed with Assura and Cali- bre parasitic extractions, which leads to the need of a post-layout RLC filter re-tuning. After a correction in the RLC filter capacitance value, new Assura and Calibre parasitic extractions are performed producing good results. A 64:06% drain efficiency with Assura extraction and 62:81% with Calibre are achieved against the 66:18% drain efficiency of the ideal case. The output power is approximately 21-dBm with both parasitic extractions and in the ideal case. i ii Resumo O presente trabalho tem como objectivo o estudo e implementação de um amplificador de potência (PA) para rádio-frequência (RF). Várias classes de amplificadores são analisadas e destas, o amplificador de funcionamento classe-D em modo corrente (CMCD) é o seleccionado para implementação. Devido ao amplificador CMCD possuir a característica zero-voltage-switching (ZVS) e de ter uma tensão de pico no dreno dos transístores menor que o amplificador classe-E, também ele um amplificador ZVS, fazem dele a melhor opção para um estudo aprofundado e im- plementação. O facto de não existirem implementações desta classe em CMOS, reportadas até à data também teve influência na decisão. Após o estudo do funcionamento básico do amplificador classe-D em modo corrente, é efec- tuada uma análise ao impacto do factor de qualidade da rede de carga, QL, no desempenho do PA. A segunda parte desta análise não linear do comportamento do CMCD, é feita tendo em conta o impacto do factor de qualidade da bobine da rede RLC juntamente com QL. Daqui pode-se con- cluir que baixar o QL, aumentado o valor da bobine e diminuindo o valor do condensador de carga pelo mesmo factor, traduz-se num aumento de desempenho por parte do amplificador. Um vasto conjunto de simulações é apresentado neste trabalho. Nestas simulações o método de baixar o factor de qualidade da rede de carga é comprovado com recurso a uma tecnologia CMOS de 90-nm, obtendo-se aproximadamente 76% de eficiência de dreno com 16-dBm de potência de saída. Um estudo comparativo entre a tecnologia CMOS de 90-nm e outra de 350-nm é efectuado, onde se demonstra que a tecnologia de 90-nm é mais adequada à implementação do amplificador de potência. As curvas características I-V dos transístores de rádio-frequência NMOS, de ambas as tecnologias, são apresentadas para definir as tensões de quebra dos transístores. A topologia cascode do amplificador classe-D em modo corrente é apresentada como solução para aumentar a potência de saída do amplificador, sacrificando apenas uma pequena percentagem da eficiência de dreno. Este aumento de potência de saída do amplificador é possivel pois, com a topologia cascode temos dois transístores em cada ramo, o que nos permite aumentar a tensão de alimentação do circuito. Um layout do amplificador de potência CMCD desenhado na tecnologia CMOS 90-nm é ap- resentado. Foi necessário efectuar uma re-sintonização do filtro RLC após terem sido efectuadas simulações post-layout e os resultado não serem os esperados. Após a correcção na capacidade do filtro RLC, novas extracções parasitas do layout são efectuadas com as ferramentas Assura e Calibre produzindo bons resultados. Eficiências de dreno de 64:06% com o Assura e 62:18% com o Calibre foram atingidas contra os 66:18% do caso ideal. A potência de saída atingida é aproximadamente 21-dBm nas extrações parasitas e no caso ideal. iii iv Acknowledgments First of all I would like to thank my mother, father and brother for making the person I am today. Without you this work was not possible. To my girlfriend who always supported me whenever things went wrong, I would like to show my deepest appreciation. I would like to show my gratitude to both of my supervisors for all their support and encour- agement. To Professor Vítor Grade Tavares for his advises. To the Engineer and future PhD Cândido Duarte for always making me give the best of me, and for the initial idea which made this thesis possible. The Microelectronic Students’ Group at the Faculty of Engineering of the University of Porto, which I am a member since the beginning, also played an important role in this work. My interests in RF grew and were developed thanks to those hard Friday nights spent at the University, but it was worth it. Thanks to all the group members for the good times but mainly to its founders, who keep the group alive since its beginning. To all my other friends that are with me since the beginning of this course, thank you. For the study hours shared, the fun times spent and also for being there in the bad times. At last, I would like to show my gratitude to all my other friends that make part of my life and always bring me something positive into it. I hope I also bring something positive into your life. Daniel José Azevedo Oliveira v vi “An expert is a man who has made all the mistakes which can be made in a very narrow field.” Niels Bohr vii viii Contents 1 Introduction1 1.1 Motivation . .1 1.2 Bluetooth features . .2 1.3 Power amplifiers overview . .4 1.3.1 Linear amplifiers . .4 1.3.2 Non-linear amplifiers . .8 1.4 State of the art . 12 1.4.1 Amplifiers for Bluetooth . 12 1.4.2 Class-D−1 amplifiers . 13 2 Class-D−1 Power Amplifier 17 2.1 Current-Mode Class-D power amplifier . 17 2.2 Basic operation . 18 2.3 Ideal analysis . 20 2.4 Non-ideal analysis . 25 2.4.1 Impact of QL in the circuit performance . 25 2.4.2 Influence of Qu in the circuit performance . 27 2.5 Summary . 33 3 Simulations 35 3.1 Pre-layout simulations . 35 3.1.1 Lowering the QL factor . 35 3.1.2 Impact of the transistors size . 36 3.1.3 90-nm versus 350-nm . 38 3.1.4 CMCD PA cascode configuration . 40 3.1.5 Power control . 41 3.1.6 PA re-tuning . 43 3.2 Power amplifier layout . 44 3.2.1 Post-layout Simulations . 45 3.3 Summary . 47 4 Conclusion 49 4.1 Achievements . 49 4.2 Future work . 50 A Power Amplifier Layout 53 References 55 ix x CONTENTS List of Figures 1.1 Bluetooth modulation schemes. .3 1.2 Power amplifier classes and groups. .4 1.3 Linear power amplifier schematic. .5 1.4 Class-A amplifier drain current waveform (two RF cycles shown). .5 1.5 Class-B amplifier drain current waveform (two RF cycles shown). .6 1.6 Class-C amplifier drain current waveform (two RF cycles shown). .7 1.7 Efficiency of linear amplifiers. .8 1.8 Class-E power amplifier schematic. .9 1.9 Class-E drain current and voltage waveforms. .9 1.10 Class-F power amplifier schematic with 5th harmonic peaking. 10 1.11 Class-F drain current and voltage waveforms. 10 1.12 Class-F−1 power amplifier schematic with 5th harmonic peaking.
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