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Design and Analysis of Class AB RF Power Amplifier for Wireless Communication Applications

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Design and Analysis of Class AB RF Power Amplifier for Wireless Communication Applications University of Central Florida STARS Retrospective Theses and Dissertations 2002 Design and analysis of class AB RF power amplifier for wireless communication applications Mohamed El-Dakroury University of Central Florida, [email protected] Part of the Systems and Communications Commons Find similar works at: https://stars.library.ucf.edu/rtd University of Central Florida Libraries http://library.ucf.edu This Masters Thesis (Open Access) is brought to you for free and open access by STARS. It has been accepted for inclusion in Retrospective Theses and Dissertations by an authorized administrator of STARS. For more information, please contact [email protected]. STARS Citation El-Dakroury, Mohamed, "Design and analysis of class AB RF power amplifier for wireless communication applications" (2002). Retrospective Theses and Dissertations. 1498. https://stars.library.ucf.edu/rtd/1498 DESIGN AND ANALYSIS OF CLASS AB RF POWER AMPLIFIER FOR WIRELESS COMMUNICATION APPLICATIONS by MOHAMED EL-DAKROURY B.SC. Cairo University, Egypt, 1995 A thesis submitted in partial fulfillment of the requirements for the degree of Master of Science in the School of Electrical Engineering and Computer Science in the College of Engineering and Computer Science at the University of Central Florida Orlando, Florida Summer term 2002 Major Professor: Dr. Jiann S. Yuan ABSTRACT The Power Amplifier is the most power-consu!}ling. blpqk among the quil~ing blocks of RF transceivers. It is still a difficult problem to design power amplifiers, especially for linear, low voltage operation. Until now power amplifiers for wireless applications is being produced almost in GaAs processes with some exceptions in LDMOS, Si BJT, and SiGe HBT. The submicron CMOS processes for power amplifiers are under research focus since CMOS offers integration for power amplifier with rest of the transceivers blocks due to its high yield. Also CMOS process is cheap. This thesi.s report details the design process of a class AB power amplifier for GSM wireless applications using 0.35 µm CMOS process. The transmit frequency for GSM-1800 standard for handset applications is 1710 MHz - 1785 MHz. The power amplifier has been designed to deliver 2 W of minimum output power into a 50 Q load. The circuit-was designed and simulations indicated a peak power added efficiency of 47 %. ii ACKNOWLEDGMENTS Praise is to ALLAH, the lord of the worlds and peace is upon his prophet and last messenger, Muhammad (PBUH). " Glory is to You, have no knowledge except what you have taught us. Verily, it is You, the All-Knower, the All-Wise." Verse 32, Chapter Al-Baqarah, The Noble Qur'AN. It has been a great opportunity to be part of the Chip Design and Reliability Laboratory (CDRL) at the University of Central Florida. I'm honored to have had the opportunity to work with Dr. Jiann S, Yuan as my advisor. Without his technical and personal advice, this research work would not be done. I am very grateful to my committee members, Dr. Abdel Ejnioui and Dr. Taskin Kocak for their support and taking the time to serve in my committee. I'm very grateful to all UCF faculty and staff for their time and in particular Dr. T. Wu whose Microwave Circuits and Devices class was very beneficial. I am very grateful to my wife Radwa and my 14 month old daughter Sondos for their patience and encouragement. Also I would like to thank my mother, my father, my mother in low, my brothers, and my sister for their support and encouragement. iii I would like to thank all of my colleagues in the CDRL. I would like to express my particular appreciation tb Enjun Xiao, Wade Smith, and Hong Yang who supported me from simulation and circuit point of view. I also thank Li Yang, Jia Di, Weidong Kuang for their help and support. The CDRL group has been an incredibly stimulating and enjoyable group to work with. lV TABLE OF CONTENTS LIST OF FIGURES Vll 1 INTRODUCTION 1 1. 1 Motivation I 1.2 Structure of RF Transceiver System 2 1.3 Power Amplifier Design Considerations 3 1.3 .1 Output Power 3 1.3.2 Power Added Efficiency and Linearity 4 1.4• Thesis Overview 5 2 BACKGROUND 6 2.1 Definitions and Terminology 6 2.2 Power Amplifiers Configurations 7 2.2.1 Linear Classes of Power Amplifiers 8 2.2.1.1 Class· A · 8 2.2.1.2 Class B 11 2.2.1.3 Class AB 12 2.2.2 Non-linear Classes of Power Amplifiers 13 2.2.2.1 Class C 13 2.2.2.2 Class E 16 2.2.2.3 Class F 19 2.3 Linearization Techniques 21 2.3.1 Cartesian Feedback 22 2.3.2 Pre-distortion and Adaptive Pre-distortion 24 2.3.3 Feed Forward 26 2.4 Conclusion 28 3 DESIGN ARCHITECTURE OVERVIEW 29 3 .1 Choice of Process 29 3.2 Choice of Power Amplifier Class 31 V 3.3 Choice of Circuit Topology 32 3.3.1 Multi-Stage Design 32 3.3.2 Single-Ertded Topology 34 4 POWER AMPLIFIER CIRCUIT DESIGN 35 4.1 Introduction 35 4.2 Output Stage 38 4.2.1 Transistor Configuration in the Output Stage 38 4.2:2 Optimum Load Resistance Determination 40 4.2.2.1 Conjugate Match 40 4.2.2.2 Load Line Match , 41 4.2.3 Output Impedance Matching Network 43 4.3 Pre-amplification Stage 46 4.3.1 Optimum-Loading 47 4.3.2 Design of Input Matching Network 47 4.4 Inter,stage Matching Network Design 49 4.5 Final Circuit 49 4.6 SimulatiQn Results 51 4.7 Conclusion 58 5 HOT-CARRIE.8,EFFECTS ON POWER AMPLIFIER CIRCUIT 59 ' 5 .1 IntroductioJ1 59 5.. 1.1 :Mot-carriers Mechanisms 59 5.1.2 Hot-carrier Degradation 62 5 .1.3 G~te-Oxide Thickness Effect 63 5.2 PoweF Amplifier Performance Degradation due to Hot-Carrier Effect 64 6 CONCLUSION 68 REFERENCES 70 vi J:;IS'l' OF FIGURES Figure 1.1 The structure of RF system 3 Figure 2.1 General circuit topology suitable for class A, AB, B, andCPAs 9 Figure 2.2 Class A waveforms 11 Figure 2.3 Class B waveforms 12 Figure 2.4 Class AB waveforms 13 Figure 2.5 Input and output waveforms for class CPA 14 Figure 2.6 A class E stage 18 Figure 2.7 Class E waveforms 18 Figure 2.8 A typical class F stage circuit diagram 20 Figure 2.9 Class F waveforms 20 Figure 2.10 A block diagram of Cartesian feedback linearization technique 23 Figure 2.11 Block diagram of pre-distortion technique 25 Figure 2.12 Block diagram of feed forward technique 26 Figure 3.1 Multi-stage power amplifier circuit 33 Figure 4.1 Input impedance and output junction capacitance model of device 39 Figure 4.2 Schematic showing generator along with the load 40 Figure 4.3 Output voltage versus current for a conjugate and load line Match 41 Figure 4.4 Optimum loading using load line approach · 42 Figure 4.5 Output matching network 44 Figure 4.6 1t-matching network used in output matching network 45 Figure 4.7 Input matching network 48 Figure 4.8 Final circuit including all values of components 50 Figure 4.9 Simulated output power versus frequency 52 Figure 4.10 Simulated power added efficiency versus frequency 53 Figure 4.11 Simulated output power versus supply voltage 54 Figure 4.12 Simulated power added efficiency versus supply voltage 55 Figure 4.13 Power gain in dB versus frequency 56 Figure 4.14 Stability factor (K) versus frequency 57 Figure 4.15 A plot of power added efficiency versus output Power 58 Figure 5.1 A schematic diagram for hot-carrier mechanisms 60 Figure 5.2 Output power degradation due to threshold voltage and mobility degradation 65 vii Figure 5.3 Power Added Efficiency degradation due to threshold voltage and mobility degradation 66 Figure 5.4 Stability factor (K) degradation due to threshold voltage and mobility degaradation 67 viii 1 INTRODUCTION 1.1 Motivation The growth rate for the wireless communications industry is increasing due to the advanced options it offers and adds everyday which led in tum to a big demand from consumers. The annual world wide sales of cellular phones has exceeded $2.5B. With 4.5 million customers, home satellite networks comprise a $2.5B industry. The global positioning system was a $5B market in the year 2000. In Europe, the sales of the equipment and services for mobile communications had reached $30B in 1998 [1]. Some of the criteria that consumers put into their consideration when comparing between different wireless equipment are talk time, price, and size. Talk time can be interpreted to long battery life or less power consumption, which means efficiency in en&ineering terms. Price and size can be considered to some extent two different sides of a coin as both depend on the technology that is being used. Power Amplifier is the most power-consuming I block of the RF trans.ceiver. J'aole 1.1 is a summary of some common power amplifiers requirements [2]. Table 1.1 PA standards and summary AMPS IS-54/136 CDMA GSM DCS1800 TDMA (Class 4) Tx 824-850 824-850 824-850 880-915 1710-1785 Frequency MHz MHz MHz MHz MHz Eff. Rad. 600mW/ 600mW/ 250mW/ 2W/ lW/ Power 28dBm 28dBm 24dBm 33dBm 30dBm · PA power l.4W/ l.3W/ 600mW/ 3W/ l.8W/ 31.5dBm 31dBm 28dBm 35dBm, 32.5dBm Duty cycle 100% 33% 100% 12.5% .12.5%- .
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