Wideband Automatic Gain Control Design in 130 Nm CMOS Process for Wireless Receiver Applications
Wideband Automatic Gain Control Design in 130 nm CMOS Process for Wireless Receiver Applications A thesis submitted in partial fulfillment of the requirements for the degree of Master of Science in Engineering By Joseph Benito Strzelecki, B.S. Wright State University, 2013 2015 Wright State University WRIGHT STATE UNIVERSITY GRADUATE SCHOOL _August 19, 2015_______ I HEREBY RECOMMEND THAT THE THESIS PREPARED UNDER MY SUPERVISION BY Joseph Benito Strzelecki ENTITLED Wideband Automatic Gain Control Design in 130 nm CMOS Process for Wireless Receiver Applications BE ACCEPTED IN PARTIAL FULFILLMENT OF THE REQUIREMENTS FOR THE DEGREE OF Master of Science in Engineering. ___________________________________ Saiyu Ren, Ph.D. Thesis Director ___________________________________ Brian D. Rigling, Ph.D. Department Chair Committee on Final Examination ________________________________ Saiyu Ren, Ph.D. ________________________________ Raymond E. Siferd, Ph.D. ________________________________ John M. Emmert, Ph.D. ________________________________ Arnab K. Shaw, Ph.D. ________________________________ Robert E. W. Fyffe, Ph.D. Vice President for Research and Dean of the Graduate School Abstract Strzelecki, Joseph Benito, M.S.Egr, Department of Electrical Engineering, Wright State University, 2015. “Wideband Automatic Gain Control Design in 130 nm CMOS Process for Wireless Receiver Applications” An analog automatic gain control circuit (AGC) and mixer were implemented in 130 nm CMOS technology. The proposed AGC was intended for implementation into a wireless receiver chain. Design specifications required a 60 dB tuning range on the output of the AGC, a settling time within several microseconds, and minimum circuit complexity to reduce area usage and power consumption. Desired AGC functionality was achieved through the use of four nonlinear variable gain amplifiers (VGAs) and a single LC filter in the forward path of the circuit and a control loop containing an RMS power detector, a multistage comparator, and a charging capacitor.
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