UNIVERSITY of CALIFORNIA, SAN DIEGO CMOS RF Power Amplifier Design Approaches for Wireless Communications a Dissertation Submitt

UNIVERSITY OF CALIFORNIA, SAN DIEGO

CMOS RF Power Ampliﬁer Design Approaches for Wireless Communications

A dissertation submitted in partial satisfaction of the requirements for the degree Doctor of Philosophy

Electrical Engineering (Electronic Circuits and Systems)

Sataporn Pornpromlikit

Committee in charge:

Professor Peter M. Asbeck, Chair Professor Prabhakar R. Bandaru Professor Andrew C. Kummel Professor Lawrence E. Larson Professor Paul K.L. Yu

2010 Copyright Sataporn Pornpromlikit, 2010 All rights reserved. The dissertation of Sataporn Pornpromlikit is approved, and it is acceptable in quality and form for publication on micro- ﬁlm and electronically:

Chair

University of California, San Diego

2010

iii DEDICATION

To my family.

iv EPIGRAPH

”Education is what remains after one has forgotten what one has learned in school.”

— Albert Einstein

v TABLE OF CONTENTS

Signature Page...... iii

Dedication...... iv

Epigraph...... v

Table of Contents...... vi

List of Figures...... viii

List of Tables...... xi

Acknowledgements...... xii

Vita...... xiv

Abstract of the Dissertation...... xv

Chapter 1 Introduction...... 1 1.1 CMOS Technology and Scaling...... 2 1.2 Toward Fully-Integrated CMOS Transceivers...... 4 1.3 Power Ampliﬁer Design...... 5 1.4 Wireless Communication Systems...... 9 1.4.1 Digital Modulation and Multiple Access Techniques 10 1.4.2 Modern Wireless Communication Standards..... 13 1.5 Digital RF Transmitters...... 16 1.6 Dissertation Focus and Organization...... 19

Chapter 2 Stacked-FET Power Ampliﬁers...... 21 2.1 Introduction...... 21 2.2 Breakdown Mechanisms in CMOS...... 22 2.2.1 Gate Oxide Breakdown...... 22 2.2.2 Hot Carrier Degradation...... 23 2.2.3 Punch-Through...... 24 2.2.4 Drain-Bulk Junction Breakdown...... 24 2.3 Impedance transformation and Matching Network Loss... 24 2.4 Power Combining Techniques: Prior Art...... 26 2.5 Proposed Stacked-FET Design Concept...... 32 2.5.1 Basic Operation...... 32 2.5.2 Stacked-FET vs. Parallel...... 36 2.6 Alternative CMOS Technologies...... 38 2.7 Fully-Integrated Stacked-FET Linear PA Design in SOS CMOS 39

vi 2.8 Watt-Level Stacked-FET Linear PA Design in SOI CMOS. 45 2.8.1 Gate-Bias Setting...... 48 2.8.2 Fully-Integrated Design Possibility...... 51 2.8.3 Layout Approach...... 52 2.9 Measurement Results...... 54 2.9.1 CW Measurements...... 57 2.9.2 IS-95 Measurements...... 61 2.9.3 WCDMA Measurements...... 61 2.10 Summary...... 65 2.11 Acknowledgements...... 67

Chapter 3 Digitally-Modulated Power Ampliﬁers for Multi-Standard Polar Transmitters...... 68 3.1 Introduction...... 68 3.2 Direct-Digital Multi-standard Polar Transmitter...... 69 3.3 System-Level Requirements...... 73 3.3.1 Amplitude Resolution and Sampling Frequency... 73 3.3.2 AM/PM Time Alignment...... 74 3.3.3 Transmit Power Control Requirement...... 78 3.4 DPA Circuit Implementation...... 78 3.5 Layout...... 84 3.6 Experimental results...... 86 3.6.1 CW measurements...... 89 3.6.2 WCDMA/EDGE Modulation with Digital Predistor- tion...... 97 3.7 Summary...... 101 3.8 Acknowledgements...... 101

Chapter 4 Conclusion...... 102 4.1 Research Summary...... 102 4.2 Future Work...... 104

References...... 106

vii LIST OF FIGURES

Figure 1.1: CPU transistor count and feature size trend [1]...... 2 Figure 1.2: A basic radio-frequency transceiver...... 4 Figure 1.3: A simplified conventional power amplifier schematic...... 7 Figure 1.4: A device’s load-line match...... 7 Figure 1.5: Current and voltage waveforms of different linear power amplifiers.8 Figure 1.6: Current and voltage waveforms of different switching-mode power amplifiers...... 9 Figure 1.7: Constellation diagrams of (a) QPSK, (b) OQPSK, and (c) π/4-QPSK. 12 Figure 1.8: ACPR requirement for IS-95 CDMA...... 15 Figure 1.9: ACLR requirement for WCDMA...... 15 Figure 1.10: An all-digital transmitter for GSM/EDGE [2]...... 17 Figure 1.11: A current-steering-based direct-digital RF modulator for WCDMA, EDGE and WLAN [3]...... 18 Figure 1.12: A digitally modulated polar power amplifier with a 20-MHz channel bandwidth [4]...... 19

Figure 2.1: Impact ionization at the drain...... 23 Figure 2.2: Impedance transformation network: (a) an L-match network and (b) an L-match network with inductor loss...... 24 Figure 2.3: Distributed active transformer structure [5]...... 27 Figure 2.4: Cascode configuration...... 28 Figure 2.5: A self-biased cascode power amplifier [6]...... 29 Figure 2.6: Bean stalk amplifier [7]...... 30 Figure 2.7: Hittite high-voltage power amplifier [8]...... 30 Figure 2.8: Transformer-coupled input-feed techniques: (a) Parallel-input-feed stacked FET PA [9], and (b) Series-input-feed stacked HBT PA [10]. 31 Figure 2.9: A HiVP power amplifier [11]...... 32 Figure 2.10: Proposed stacked-FET PA basic structure...... 33 Figure 2.11: Effect of an external gate capacitance on a stacked FET’s source input impedance...... 34 Figure 2.12: Silicon-on-insulator CMOS technology...... 37 Figure 2.13: Silicon-on-sapphire CMOS technology...... 37 Figure 2.14: Simplified schematics of stacked NMOS transistors using different process technologies: (a) Partially-depleted SOI CMOS used in this work, (b) Bulk CMOS, and (c) Triple-well CMOS...... 38 Figure 2.15: Schematic of the fully-integrated triple-stacked FET power amplifier in SOS CMOS [12]...... 40 Figure 2.16: Simulated load lines of each FET at the output power of 20 dBm [12]. 42 Figure 2.17: Chip photograph of the fabricated SOS power amplifier [12]..... 42 Figure 2.18: Measured S-parameters by on-wafer probing [12]...... 43

viii Figure 2.19: Measured gain, PAE and DC drain current as a function of output power with single tone input at 1.88 GHz [12]...... 44 Figure 2.20: Measured ACPR and PAE performance as a function of average output power with IS-95 CDMA input signal [12]...... 45 Figure 2.21: Circuit schematic of the single-stage stacked-FET PA...... 46 Figure 2.22: Simulated DC gate-to-source voltage and DC drain-to-source voltage of each FET as a function of input power: (a) without gate-bias offsets, and (b) with proper gate-bias offsets...... 49 Figure 2.23: Simulated drain, gate, drain-to-source, drain-to-gate voltage waveforms and dynamic load lines of each FET at the saturated output power: (a) VDD = 6.5 V, and (b) VDD = 9 V...... 50 Figure 2.24: Layout diagram of stacked-FET unit cells and interconnects..... 53 Figure 2.25: Microphotograph of the fabricated stacked-FET PA...... 53 Figure 2.26: A stacked-FET PA test board...... 55 Figure 2.27: Measured gain, PAE, and output power as a function of input power with a CW input at 1.9 GHz...... 55 Figure 2.28: Measured and simulated gain, PAE, and DC current as a function of output power with a CW input at 1.9 GHz...... 56 Figure 2.29: Measured PAE as a function of output power with supply voltage variation at 1.9 GHz...... 58 Figure 2.30: Measured drain efficiency and output power at saturation as a function of frequency...... 59 Figure 2.31: Measured gain, PAE, and DC current as a function of output power with a CW input at 900 MHz...... 60 Figure 2.32: Measured ACPR and PAE performance as a function of average output power using a reverse-link IS-95 CDMA input signal at 1.9 GHz...... 62 Figure 2.33: Measured IS-95 CDMA output spectra at Pout = 28.7 dBm...... 63 Figure 2.34: Measured ACLRs and PAE performance as a function of average output power using an uplink WCDMA input signal at 1.9 GHz... 64 Figure 2.35: Measured WCDMA output spectra and ACLRs at Pout = 29.4 dBm. 65 Figure 3.1: Direct-digital polar transmitter architecture...... 71 Figure 3.2: Block diagram of the proposed multi-standard DPA...... 72 Figure 3.3: A WCDMA signal with the envelope component quantized at different resolutions...... 75 Figure 3.4: An EDGE signal with the envelope component quantized at different resolutions...... 76 Figure 3.5: Effect of envelope and phase filtering on receive-band noise of a WCDMA signal reconstruction...... 77 Figure 3.6: Proposed Transmit Power Control Strategy...... 79 Figure 3.7: Simplified DPA schematic...... 81 Figure 3.8: A binary-to-thermometer decoder schematic...... 82

ix Figure 3.9: Simulated dynamic load line of an activated unit device with increasing ACW at 1.9 GHz...... 83 Figure 3.10: Load-pull effect on an activated unit-device load line...... 83 Figure 3.11: DPA chip micrograph...... 85 Figure 3.12: Layout of a unit amplifier...... 86 Figure 3.13: Phase-modulated RF input distribution...... 87 Figure 3.14: RF output combining in a tree structure...... 88 Figure 3.15: The DPA board for measurement...... 90 Figure 3.16: Measured output power vs. ACW at 900 MHz. The input attenuator and supply variation provide average transmit power control..... 91 Figure 3.17: Measured efficiency vs. output power at 900 MHz, in log-log scale. 92 Figure 3.18: Measured efficiency vs. output power at 900 MHz...... 93 Figure 3.19: Simulated output power and efficiency vs. carrier frequency with a fixed output matching network optimized for a broadband performance...... 93 Figure 3.20: Block diagram of the simulated ideal DPD system...... 94 Figure 3.21: ACW-AM characteristic of the DPA, before and after ideal DPD... 94 Figure 3.22: Simulated output spectrum of a WCDMA-modulated signal, before and after ideal DPD...... 95 Figure 3.23: Simulated output spectrum of an EDGE-modulated signal, before and after ideal DPD...... 96 Figure 3.24: Block diagram of the polar modulation and predistortion test setup. 98 Figure 3.25: Measured EDGE output spectrum after DPD...... 99 Figure 3.26: Measured WCDMA output spectrum and ACLRs after DPD..... 99

x LIST OF TABLES

Table 1.1: Comparison of different power ampliﬁer classes...... 6 Table 1.2: Uplink speciﬁcations of some wireless communication standards [3,13] 14

Table 2.1: Comparison of parallel and Stacked-FET conﬁgurations...... 37 Table 2.2: Performance comparison of recently reported WCDMA handset power ampliﬁers...... 66

Table 3.1: Simulated and measured EDGE spectral performance comparison.. 100 Table 3.2: Measured RF output power and overall efﬁciency for EDGE and WCDMA after DPD...... 100

xi ACKNOWLEDGEMENTS

First of all, I would like to thank my advisor Professor Peter Asbeck for his invaluable guidance and support throughout my graduate studies. His work ethic and dedication are an exceptional example for any researcher, and his never-ending patience and encouragement have been a great inspiration.

I would also like to thank my thesis committee: Professor Larry Larson, Pro- fessor Paul Yu, Professor Andrew Kummel, and Professor Prab Bandaru for providing precious feedback and suggestions.

It is my pleasure to work with many incredible colleagues. I would like to thank

Dr. Jin-Ho Jeong for his mentorship on both of my projects, and thank Dr. Calogero

Presti for being a great research buddy and for many useful discussions on the DPA project. I learned so much from them during their time here. I would like to thank Don

Kimball for his generosity and inﬁnite help in the measurement lab. I also would like to thank Dr. Dongjiang Qiao, Dr. Tsai-Pi Hung, Dr. Yu Zhao, Dr. Mingyuan Li, Dr.

Jin-Seong Jeong, Dr. Jeremy Rode, my ofﬁcemate Chin Hsia, Paul Theilmann, Johanna

Yan, Toshi Nakatani, Paul Draxler, Myoungbo Kwak, and the rest of the group members.

Their support, encouragement, and friendship helped me survive my graduate career.

Part of the material in chapter2 is as it appears in ”A 33-dBm 1.9-GHz silicon- on-insulator CMOS stacked-FET power ampliﬁer,” S. Pornpromlikit, J. Jeong, C. D.

Presti, A. Scuderi, and P. M. Asbeck, in IEEE MTT-S Int. Microwave Symp. Dig., pp.

533-536, Jun. 2009, and ”A watt-level stacked-FET linear power ampliﬁer in silicon- on-insulator CMOS,” S. Pornpromlikit, J. Jeong, C. D. Presti, A. Scuderi, and P. M.

Asbeck, in IEEE Trans. Microw. Theory Tech., vol. 58, no. 1, pp. 57-64, Jan. 2010.

The contributions from the co-authors are appreciated. The author of this dissertation

xii was the primary investigator and primary author for these publications. Part of the material in chapter3 is as it appears in ”A 25-dBm high-efﬁciency digitally-modulated

SOI CMOS power ampliﬁer for multi-standard RF polar transmitters,” S. Pornpromlikit,

J. Jeong, C. D. Presti, A. Scuderi, and P. M. Asbeck, in IEEE RFIC Symp. Dig., pp.

157-160, Jun. 2009. The contributions from the co-authors are appreciated. The author of this dissertation was the primary investigator and primary author for this publication.

xiii VITA 2002 Bachelor of Science, Electrical Engineering and Computer Sci- ence, Massachusetts Institute of Technology, Cambridge, Mas- sachusetts 2004 Master of Engineering, Electrical Engineering and Computer Sci- ence, Massachusetts Institute of Technology, Cambridge, Mas- sachusetts 2004-2010 Research Assistant, Electrical and Computer Engineering, Uni- versity of California, San Diego, California 2010 Doctor of Philosophy, Electrical and Computer Engineering, Uni- versity of California, San Diego, California

PUBLICATIONS J. Jeong, S. Pornpromlikit, P. M. Asbeck, and D. Kelly, ”A 20-dBm linear RF power amplifier using stacked silicon-on-sapphire MOSFETs,” in IEEE Microw. Wireless Com- pon. Lett., vol. 16, no. 12, pp. 684-686, Dec. 2006. S. Pornpromlikit, J. Jeong, C. D. Presti, A. Scuderi, and P. M. Asbeck, ”A 900 MHz digital polar power amplifier implemented in SOI CMOS,” in IEEE Power Amplifier Symposium Dig., Jan. 2009. P. Asbeck, L. Larson, D. Kimball, S. Pornpromlikit, J.-H. Jeong, C. Presti, T.P. Hung, F. Wang, and Y. Zhao, ”Design options for high efficiency linear handset power amplifiers,” in IEEE Topical Meeting on SiRF Dig., pp. 1-4, Jan. 2009. S. Pornpromlikit, J. Jeong, C. D. Presti, A. Scuderi, and P. M. Asbeck, ”A 33-dBm 1.9-GHz silicon-on-insulator CMOS stacked-FET power amplifier,” in IEEE MTT-S Int. Microwave Symp. Dig., pp. 533536, Jun. 2009. S. Pornpromlikit, J. Jeong, C. D. Presti, A. Scuderi, and P. M. Asbeck, ”A 25-dBm high- efficiency digitally-modulated SOI CMOS power amplifier for multi-standard RF polar transmitters,” in IEEE RFIC Symp. Dig., pp. 157160, Jun. 2009. K. Takenaka, S. Pornpromlikit, C. D. Presti, A. Scuderi, and P. M. Asbeck, ”A digitally- modulated SOI CMOS asymmetrical Doherty amplifier,” in IEEE Power Amplifier Sym- posium Dig., Sep. 2009. S. Pornpromlikit, J. Jeong, C. D. Presti, A. Scuderi, and P. M. Asbeck, ”A watt-level stacked-FET linear power amplifier in silicon-on-insulator CMOS,” in IEEE Trans. Mi- crow. Theory Tech., vol. 58, no. 1, pp. 57-64, Jan. 2010.

xiv ABSTRACT OF THE DISSERTATION

CMOS RF Power Ampliﬁer Design Approaches for Wireless Communications

Sataporn Pornpromlikit Doctor of Philosophy in Electrical Engineering (Electronic Circuits and Systems)

University of California San Diego, 2010

Professor Peter M. Asbeck, Chair

This dissertation focuses on the design of CMOS power amplifiers for modern wireless handsets, where stringent linearity requirements and high power efficiency are difficult to achieve simultaneously. CMOS technology has been an attractive technology for research in fully-integrated transceivers due to its low cost and high-integration capability, as well as its continuously improving high-frequency performance. Its advantages, however, come at the cost of continuously reduced breakdown voltages, low isolation and high power loss in the substrate.

To address these limitations, a stacked-FET design technique is ﬁrst developed to systematically divide the voltage stress among several transistors connected in series, allowing the use of a larger supply voltage. The voltage swing of each stacked device is added in phase to provide a larger output power to the load without the requirement of a large impedance transformation. To investigate this technique, a fully-integrated

20 dBm RF power ampliﬁer is ﬁrst implemented using 0.25-µm silicon-on-sapphire

MOSFETs. By using triple-stacked FETs, the optimum load impedance for a 20 dBm power ampliﬁer increases to 50 Ω so impedance transformation is not required at the

xv output. Measurement of a single-stage linear power ampliﬁer shows a small-signal gain of 17.1 dB and a saturated output power of 21.0 dBm with a power added efﬁciency

(PAE) of 44.0% at 1.88 GHz. With an IS-95 code division multiple access (CDMA) modulated signal, the power ampliﬁer shows average output power of 16.3 dBm and

PAE of 18.7% with ACPR below -42 dBc.

The concept is then further demonstrated at higher voltage and power level. A single-stage quadruple-stacked-FET linear power ampliﬁer is presented using 0.28-µm

2.5-V standard I/O FETs in a 0.13-µm silicon-on-insulator (SOI) CMOS technology.

The PA is designed to withstand up to 9 V of supply voltage before reaching its breakdown limit. The measured PA achieves a small-signal gain of 14.6 dB, a saturated output power of 32.4 dBm, and a PAE of 47% at 1.9 GHz with a 6.5-V supply. Using a reverse- link IS-95 CDMA modulated signal, the PA shows an average output power of up to

28.7 dBm with a PAE of 41.2% while meeting the adjacent channel power ratio requirement. The PA also shows an average output power of up to 29.4 dBm with a PAE of

41.4% while meeting the adjacent channel leakage ratio requirement of an uplink wide- band code division multiple access (WCDMA) modulated signal. These performances are comparable to those of GaAs-based power ampliﬁers.

To fully exploit the advantages of higher-speed CMOS technology and the availability of co-integrated digital circuitry, a digital-intensive transceiver architecture is explored as an alternative in the second part of the dissertation. A single-ended digitally- modulated power ampliﬁer (DPA) is demonstrated in a 0.13-µm 1.2-V SOI CMOS technology, to be used in a multi-standard RF polar transmitter. The amplitude modulation is done by digitally controlling the number of activated unit ampliﬁers whose currents are summed at the output. The DPA is designed for multi-mode multi-band functionality

xvi by avoiding frequency-selective components, except for the final-stage output matching network. The measured DPA delivers a 24.9-dBm peak output power at 900 MHz with a maximum power efficiency of 62.7%. Similar high-efficiency performance is also exhibited at 1.92 GHz with a reconfigured matching network. By employing a digital pre-distortion technique, the DPA could meet linearity requirements for both the enhanced data rate for GSM evolution (EDGE) and WCDMA standards.

xvii Chapter 1

Introduction

Since introduced to the world more than a century ago when Marconi successfully transmitted radio signals across the Atlantic ocean in 1901, the concept of wireless communications has tremendously evolved and become an integral part of our everyday life, inﬂuencing the way people live and interact with one another, thanks to inven- tions by countless scientists and engineers from many disciplines. Edwin Howard Arm- strong’s superheterodyne receiver in 1917, the invention of transistor in 1947 by John

Bardeen, Walter Brattain and Wiiliam Shockley, Claude Shannon’s information theory in 1948, to name a few, contributed greatly to how wireless communication networks and systems are implemented today.

On the electronics side, mobile user devices have become increasingly powerful over the years. Users can now make high-quality calls, read emails, download music and watch live streaming video, all from a single highly-integrated mobile device. The development of integrated circuits, and essentially CMOS technology, is a major reason that the cost of these devices is relatively low and affordable for the public, giving rise to an explosive growth of the mobile phone market in the last few decades. In 2009, there were more that 4 billion mobile subscriptions worldwide [14].

1 2

1.1 CMOS Technology and Scaling

CMOS technology has been the predominant technology in digital integrated circuits since it was invented in 1963. As the technology advances in each generation with shrinking transistor dimensions and an increasing production yield, more transistors per unit area, and thus more functionality, can be integrated onto a chip at a lower production cost. It was ﬁrst observed by Gordon Moore in 1965 that the number of transistors on a single chip doubled every year [15]. In 1975, he updated his prediction to once every two years, which has become the guideline for the industry, as illustrated by the CPU transistor count and feature size trend lines in Fig. 1.1.

Figure 1.1: CPU transistor count and feature size trend [1].

Classical MOSFET scaling principle was ﬁrst described by Dennard in 1974

[16]. His constant-ﬁeld scaling methodology keeps short-channel effects under control 3 by scaling down the device voltages and the device dimensions, both horizontal and vertical, by the same factor κ so that the electric ﬁeld remains unchanged. As a result, the circuit speeds up by the same factor and power dissipation per circuit is reduced by

κ2. Moreover, the power density remains unchanged while the power-delay product is improved dramatically by a factor of κ3.

In reality, however, the oxide ﬁeld has been increasing over the generations and

CMOS technology has been scaled with mixed steps of constant-ﬁeld and constant- voltage principles due to the standardized power-supply voltage of earlier-generation systems and the tradeoff between leakage current and circuit speed dictated by threshold voltage [17].

Even though CMOS was originally developed purely for digital circuits, it has become an increasingly attractive technology for analog and radio-frequency (RF) circuits over the years due to its cost advantage, high-integration capability and ever- improving high-frequency performance. For example, Intel’s 45nm CMOS transistors have fT and fMAX values of more than 300 GHz. The same process also provides low- leakage transistors, high-voltage high-speed I/O transistors as well as precision resistors, precision capacitors, high-Q inductors and varactors [18].

Recently, analog and RF circuit design in CMOS is widely investigated both in academia and industry, spurred by the possibility of integrating the RF frontend and the digital baseband circuitry onto the same chip. A highly-integrated CMOS RF transceiver would result in a low production cost, a low power consumption, a better noise immunity, and the possibility of using digital signal processing (DSP) to improve RF performance. 4

1.2 Toward Fully-Integrated CMOS Transceivers

i Quadrature ADC k LNA Demodulator qk

Receiver Architecture fLO

I i k DAC Quadrature PA q Modulator k Q

Transmitter Architecture fLO

Figure 1.2: A basicVg radio-frequency transceiver.

Vds >> Vdsat Gate A basic architecture of an RF transceiver is shown in Fig. 1.2. The analog portion

n+ Source n+ Drain Electron of the receiver chain takes an RFcurrent analog signal and converts it into digital bitstreams. In the transmitter, the digital I/Q signals are convertedBuyImpact SmartDraw ionization to an!- analogpurchased signal, copies print then this frequency- document without a watermark . translated by an up-conversion mixer. TheVisit resulting www.smartdraw RF signal.com or is call finally 1-800-768 amplified-3729. by a power amplifier (PA) to the required power level before radiated through the antenna.

CMOS technology is used to fabricate virtually all digital VLSI circuits and analog precision circuits, and as of late, many analog/RF frontend functions, such as low- noise amplifier (LNA), mixer, and voltage-controlled oscillator (VCO) have been successfully implemented in CMOS. Power amplifiers, however, are commercially implemented using GaAs-based technologies, either Metal Semiconductor Field Effect Tran- sistors (MESFETs) or Heterojunction Bipolar Transistors (HBTs). The choice of using higher-performance more-expensive technologies is usually necessary for the power 5 amplifier, which is the most power-hungry component in any wireless transceiver. Inte- gration of power amplifiers in CMOS suffers from two major drawbacks: low substrate resistivity and low breakdown voltages.

Integrating a power ampliﬁer with other transceiver components and digital circuits on the same die can be harmful due to the poor substrate isolation in CMOS.

Since many CMOS processes use a low-resistivity silicon substrate, large signals from a power ampliﬁer can be conducted across the substrate and corrupt adjacent circuit blocks. In addition, the low resistivity of substrate results in low-quality factor passive components due to the energy coupled into the lossy substrate. CMOS technology also has much lower breakdown voltages compared to other technologies, especially as the device dimensions scaled down in each generation, limiting usable voltage headroom.

These drawbacks eventually result in low output power and poor power efﬁciency in power ampliﬁer design.

1.3 Power Ampliﬁer Design

Power ampliﬁers have been traditionally categorized into different classes (A, B,

C, D, E, F, etc.) based on factors such as conduction angles, input signal overdrive, and operating current and voltage waveforms. These classes are compared in Table 1.1 in terms of power efficiency and linearity, which are the most significant parameters for power amplifier design. For class A, AB and C, the input signal overdrive is relatively small and the device is operated more as a current source. A simplified schematic is illustrated in Fig. 1.3. In small-signal amplifiers, a conjugate-match load resistance is typically selected to optimize gain. In power amplifiers where large signals are involved, however, physical limits of the device both in terms of voltage and current come into 6

play. The load resistance can be selected based on the device’s load line as shown in

Fig. 1.4 to optimize for the the best power and efﬁciency. The drain voltage of the output transistor swings between ground and 2VDD depending on the input power level. The maximum RF output power that a transistor can provide is given by its power triangle,

1 P = I (V V ). (1.1) max 8 · max · max − min

The drain efficiency (ηd) and the power-added efficiency (PAE), in terms of drain efficiency and power gain G, can be calculated as,

Pout ηd = , (1.2) Pdc

P P P AE = out − in Pdc (1.3) 1 = η (1 ). d · − G

Table 1.1: Comparison of different power ampliﬁer classes

Class A AB B C D E F

Conduction angle (%) 100 50-100 50 <50 50 50 50

Max. efﬁciency (%) 50 50-78.5 78.5 100 100 100 100

Linearity Excellent Good Good Poor Poor Poor Poor

A class-A power ampliﬁer is operated in full input and output ranges with no waveform clipping, and thus, provides the best linearity. For class AB, B, and C, the conduction angle is reduced accordingly by lowering the gate bias voltage to trade-off 7

VDD

RF Choke Rop

Matching Network

Vin RL

Figure 1.3: A simpliﬁed conventional power ampliﬁer schematic.

Iout

Imax

Vout Vmin Vmax

Figure 1.4: A device’s load-line match. 8

linearity for better efficiency, as illustrated in Fig. 1.5. These classes can be referred to as linear-mode, even though linearity becomes relatively poor for a class-C power amplifier due to the severely clipped output signal. The maximum drain efficiency can be calculated as a function of the conduction angle (θ) as expressed in (1.4)[19]. For an ideal class-A power amplifier, assuming a zero on-resistance or zero knee voltage (Vmin

= 0), the maximum drain efficiency is 50% and will be higher for smaller conduction angle. The drain efficiency reaches 78.5% for a class-B power amplifier (θ = 180o).

1 θ sin(θ) V V η (θ) = − max − min . (1.4) d 4 sin(θ/2) (θ/2) cos(θ/2) · V + V − max min

Class A Class AB Class B Class C

¢ ¢ ¢ ¢

¡ ¡ ¡ I I ¡ I I

2I £

I £ θ

I £ £

t t I £ t I t

¢ ¢ ¢ ¢

¡ ¡ ¡

V V ¡ V V

2V 2V 2V 2V

V V V V

t t t t

Figure 1.5: 2: Voltage Current and and current voltage waveforms waveforms of powerof different amplifier linear in different power amplifiers. classes of operation.

For class D, E, and F, the output transistor is driven with a large input overdrive If the transistor operates for less than half of the cycle or with the conduction suchangle that smaller it operates than more 180◦, asit is a called switch, class-C and thus, operation. can be Class-C referred operation to as switching-mode is highly ef- powerficient, amplifiers. and mostly These used classes in nonlinear provide applications, high-efficiency especially nonlinear in the constant-envelope power amplification modulation where only the phase of the signal is used to convey data. Class C is not and are differed from one another by operating voltage and current waveforms that can suitable for linear operation because of strong distortions in signal amplitude. be achieved through circuit topology and harmonic termination. The current and voltage The maximum drain efficiency (η) of an amplifier can be calculated as a function

of the conduction angle by the following expression [32]

1 θ sinθ η = − (1) 4 sin(θ/2) (θ/2)cos(θ/2) − The maximum drain eﬃciency of class-A ampliﬁer (θ = 360◦) is 50% and will be

higher for smaller conduction angle toward class B (θ = 180◦; η = 78.5%) and C (θ

= 0◦; η = 100%). However, the output power to the load will drop rapidly when η approaches zero, as given by [32]

θ sinθ P − (2) out ∝ 1 cos(θ/2) −

8 VDD

RF Choke Rop 9 Matching Network waveforms of different switching-mode power ampliﬁers are shown in Fig. 1.6. The Vin RL main concept is to reduce the overlap between current and voltage waveforms across the switch to minimize power dissipation.

Current

Class-D Voltage (voltage-mode) time

Current Class-E Voltage time

Current

Voltage Class-F time

Figure 1.6: Current and voltage waveforms of different switching-mode power ampli- ﬁers.

1.4 Wireless Communication Systems

The ﬁrst- and second- generation mobile communication systems are mainly used for voice communications. While the ﬁrst-generation systems such as advanced mobile phone service (AMPS) are analog systems, the second-generation systems, introduced in late 1980s, are digital systems. There are several digital standards worldwide such as the global system for mobile communications (GSM), IS-95/98 code-division multiple-access system (CDMA), IS-136 time-division multiple-access system (U.S. 10

TDMA or D-AMPS), and the personal digital cellular (PDC) system in Japan. Among them, the European-developed GSM has been the most widely used standard in the world. To allow for data, internet, and other connectivities, new technologies such as the general packet radio system (GPRS) and the enhanced data rate for GSM evolution

(EDGE) were next introduced as 2.5-generation systems. The third-generation systems such as cdma2000-1x and wide-band code division multiple access (WCDMA) systems, were then introduced in late 1990s, providing high-speed video and multimedia services as well as larger-capacity voice communications.

1.4.1 Digital Modulation and Multiple Access Techniques

Modulation is the process of translating an original baseband signal into a band- pass signal at a high frequency suitable for transmission. In analog systems, this process can be performed by varying amplitude (AM), phase (PM) or frequency (FM) of the high-frequncy carrier. The digital equivalents of AM, PM, and FM are called amplitude shift keying (ASK), phase shift keying (PSK), and frequency shift keying (FSK), respectively. The advantages of digital modulation include greater noise immunity, more robustness to channel impairments, easier multiplexing of voice, data, and image information, and better security. Popular digital modulations are binary phase shift keying

(BPSK), M-ary phase shift keying (QPSK, OQPSK, etc.), minimum shift keying (MSK), and M-ary quadrature amplitude modulation (16 QAM and 64 QAM).

A digital baseband signal can be a binary waveform or a multi-level (M-ary) digital signal, where the original binary data stream is subdivided into groups of log2(M) bits and each group is converted to one of M possible levels. Each group of bits is called

“symbol” and the symbol rate is reduced from the original bit rate by log2(M), relax- 11 ing bandwidth requirements. When choosing a modulation scheme, there are always tradeoffs between power efficiency and bandwidth efficiency (ηBW ) defined as [20]

R η = bps/Hz, (1.5) BW BW where R is data rate in bits per second and BW is the bandwidth of the modulated

RF signal. For example, the GSM system employs a Gaussian pulse shaping minimum shift keying (GMSK) modulation, resulting in a carrier with a constant envelope. This modulation allows for the use of a high-efficiency switching-mode power amplifier. In order to increase the data rate while keeping the same bandwidth, the EDGE system is introduced using an 8-ary PSK modulation to achieve a higher bandwidth efficiency.

This modulation, however, results in a varying envelope with approximately a 3.2-dB peak-to-average ratio (PAR), requiring a lower-efﬁciency linear power ampliﬁer.

Waveforms of digital modulation schemes can be generally expressed in the following complex envelope form

M(t) = I(t) + jQ(t) = A(t)ejϕ(t), (1.6)

X I(t) = I p (t kT τ), (1.7) k I − s − k

X Q(t) = Q p (t kT τ), (1.8) k Q − s − k where I(t) and Q(t) are in-phase and quadrature envelope waveforms, respectively, and can be represented in terms of a two-dimensional constellation diagram. For examples, constellation of QPSK, OQPSK, and π/4-QPSK are illustrated in Fig. 1.7. 12

The trajectory from one constellation point to another will determine the envelope variations of the output RF signal. Notice that QPSK and OQPSK have a similar constalla- tion diagram. In QPSK, the trajectory can go through the origin of the complex plane, resulting in a changing envelope amplitude. In OQPSK, the quadrature data streams are offset in time by half the symbol period relative to each other so the phase step is only

90o and consequently the transition through the origin is avoided. ±

Figure 1.7: Constellation diagrams of (a) QPSK, (b) OQPSK, and (c) π/4-QPSK.

The modulation techniques provide the basis for transmitting signals from a transmitter to a receiver. When multiple transceivers are communicating, multiple access techniques are required. In the most simple case when only two transceivers are talking, two common approaches are time-division duplexing (TDD) and frequency- division duplexing (FDD). In TDD, the same frequency band is used for both transmit path and receive path but the system is alternating in time between transmitting and receiving. In FDD, two different frequency bands are dedicated for the transmit and receive paths with a base station acting as a translator.

Similarly, in the case of two-way communications among multiple transceivers, the frequency band can be partitioned into many channels (frequency-division multiple 13

access, FDMA), where each channel is assigned to one user, or the same frequency band can be time-shared by each user (time-division multiple access, TDMA). Another popular technique for multiple access is code-division multiple access (CDMA), where each bit of the baseband data is translated to a pre-assigned orthogonal digital code before modulation. As a result of the encoding operation, the baseband data of each user is spread over the entire available bandwidth while the spread spectra of unwanted signals can be viewed as white Gaussian noise due to their low correlation with the assigned code.

1.4.2 Modern Wireless Communication Standards

With an increasing number of emerging mobile applications and a demand for higher data rate and network capacity, it is becoming necessary for each mobile device to support multiple standards. Integrating all the hardware for these standards into the same module, however, is a challenging task due to the complexity and stringent requirements of each modern standard. In this work, we ﬁrst look at the details of some modern wireless standards and their requirements relevant to uplink transmitter design, as summarized in Table 1.2.

The EDGE system uses the existing GSM infrastructure and licenses. The channel spacing is also 200 kHz, the same as the GSM spectrum, but its data rate is triple that of GSM by using 8PSK modulation. Consequently, the PAR is 3.2 dB, instead of a constant envelope in GSM. The GSM/EDGE standard speciﬁes that the transmitter output meets error vector magnitude (EVM) and spectral mask requirements to avoid blocking the spectrum of neighboring channels. The error vector is deﬁned as the difference between the ideal constellation point and the actual transmitted constellation point. The 14

Table 1.2: Uplink speciﬁcations of some wireless communication standards [3, 13]

Standard IS-95 GSM/EDGE WCDMA

Uplink frequency 824-849 890-915 1920-1980

(MHz) (1850-1890) (1710-1910)

Downlink frequency 869-894 935-960 2110-2170

(MHz) (1930-1990) (1805-1990)

3π Modulation OQPSK GMSK/ 8 -8PSK HPSK Duplex Full-duplex Half/Full-duplex Full-duplex

FDD FDD FDD

Multiple access DS-CDMA TDMA DS-CDMA

Channel data 1.2288 Mchip/s 270.83 kbit/s 3.84 Mchip/s

clock rate

Required channel 1.25 MHz 200 kHz 5 MHz

bandwidth

Maximum average 23-30 dBm 30-33/22-26 dBm 24 dBm

output power (E2 and E3) (Class 3)

Peak-average 4.5-5.5 dB 0/3.2 dB 3.5 dB

power ratio

TX. power 73-80 dB 30 dB 74-80 dB

control range 15

RMS value of EVM should be lower than 9% and the peak value of the EVM should be lower than 30%. For the spectral mask, the most critical points are at 400 kHz and 600 kHz offsets, where the relative power needs to be below -54 dB and -60 dB respectively.3

1.6, ACPR is defined as the ratio of the leakage power measured in the adjacent

channel (channel n+1) to the transmitted power in the transmission channel (channel

n). The maximum allowable ACPRs over a 3.84MHz channel bandwidth at 5 MHz

offset (channel n+1) and 10 MHz offset (channel n+2) are -33 dBc and -43 dBc Figure 1.2: ExampleFigure of ACPR 1.8: ACPR spectrum requirement mask [2]. for IS-95 CDMA. respectively. Systems with amplitude modulation signals or multi-carrier signals generate

time-varying output power. Peak-to-average power ratio (PAR) is used to characterize

the relationship between peak power and the average power of the modulated signals.

Typically, the amplifiers used in these systems need to be operated at a backed-off

average power to avoid getting into saturation region during the peak excursions, thus

maintaining linear amplification. Figure 1.3 shows the probability distribution

functions (PDF) of three modulation schemes [5]. AMPS/GSM has constant envelopes, Figure 1.9: ACLR requirement for WCDMA. soFigure its PDF 1.6 isACPR a delta spectrum function definition located of atWCDMA peak power. systems. For π/4 QPSK and multi-carrier

(OFDM), the peak-to-average ratio is about 5-8 dB and 8-13dB, respectively. The 1.1.2The WCDMA IS-95 CDMA Handset signal Transceiver occupies a bandwidth of 1.25 MHz and has a PAR PDF indicates the amplifier stage spends very limited amount of time generating peak of 5.5 dB.A The handset WCDMA chipset has of aWCDMA bandwidth systems of 5 MHzconsists and of a PARtwo major of 3.5 blocks: dB with a one power for the non-constant envelope modulation signals, so the efficiency calculation transmitter and a receiver. The simplified schematic of a typical WCDMA handset needs special consideration. transceiver is shown in Figure 1.7, where the top path after the duplexer is the receiver

and the bottom path is the transmitter. Analog-to-Digital (A/D) and Digital-to-Analog

(D/A) converters are not shown at the baseband side. Power control, automatic

frequency control and automatic gain control are not displayed at the system level.

They are all essential for the full implementation of WCDMA systems, but ignored

16 data channel active. Moreover, the power control dynamic range specification requires the mobile transmitter to span from full power to -50 dBm. The most stringent linearity requirement for these standards is the adjacent channel power specification, which compares the desired channel power to the adjacent channel power due to noise and distortion from system nonlinearity. Fig. 1.8 and Fig. 1.9 illustrate the adjacent channel power ratio (ACPR) and adjacent channel leakage ratio (ACLR) specifications for the

IS-95 and WCDMA standards respectively.

1.5 Digital RF Transmitters

As digital circuits in advanced CMOS technologies are able to operate at higher microwave frequencies, the use of DSP becomes highly attractive in power amplifier and transmitter design. In a fully-integrated CMOS transmitter, DSP techniques can be employed to improve the overall system performance. To fully realize the advantages of higher-speed CMOS technology, the next step is to employ a more digital-intensive or all-digital transmitter architecture, where most or all of the analog building blocks are replaced by digital functionalities. An all-digital solution, in particular, would benefit from the technology scaling as well as provide high configurability to the system.

This research topic has been highly active in recent years, especially in the con- text of multi-mode multi-band transmitters, which would help facilitate an adoption of new wireless communication standards and provide global-roaming capability in a single mobile device. Multi-standard transmitters are conventionally implemented by combining several discrete transmitters, where each one is designed for a speciﬁc standard, increasing complexity and cost of the device. To solve this redundancy problem, several multi-mode polar-based digital transmitter architectures have been proposed in 17

the literature. Most of the works, however, only deliver a low output power level and still need multiple external power ampliﬁers for each frequency band.

Figure 1.10: An all-digital transmitter for GSM/EDGE [2].

In [2], an all-digital transmitter for GSM and EDGE is proposed as shown in

Fig. 1.10. The transmitter utilizes an all-digital PLL to perform the direct frequency modulation while the amplitude modulation is done by regulating the number of active

NMOS switches. It meets all the speciﬁcations for GSM with a maximum output power of 10 dBm. The EDGE spectral mask is also met with a 10-dBm margin and an RMS

EVM of 1.2%.

In [3], a multi-mode direct-digital RF modulator is implemented as shown in 18

Figure 1.11: A current-steering-based direct-digital RF modulator for WCDMA, EDGE and WLAN [3].

Fig. 1.11. In this work, the digital amplitude control is done using a segmented current steering topology. The transmitted power control range is achieved by controlling the external control voltage of the reference circuitry. The measured transmitter achieves

90 dB of power control range and meets most of the speciﬁcations for WCDMA, EDGE and WLAN, providing a maximum output power of 25 dBm with an external high-gain power ampliﬁer module.

In [4], a digitally-modulated CMOS power ampliﬁer for 64-QAM OFDM system is reported as shown in Fig. 1.12, exhibiting a 20-MHz channel bandwidth. The amplitude modulation is done by controlling the number of active unit ampliﬁers through their cascode stages. Oversampling and four-fold linear interpolation techniques are employed to suppress the spectral images from the discrete-time to continuous-time conversion of the envelope, resulting in a wide bandwidth. A PAE of 6.7% is achieved with an output power of 13.6 dBm for 64QAM OFDM signals. 19

Figure 1.12: A digitally modulated polar power ampliﬁer with a 20-MHz channel bandwidth [4].

1.6 Dissertation Focus and Organization

The main focus of this research work is to explore several design techniques that can enable the implementation of fully-integrated RF power ampliﬁers in CMOS.

As discussed in all previous sections, the power amplifier is a vital part of any wireless transmitter, consuming the most power among all the building blocks. It needs to be designed for the highest power efficiency possible to maximize the mobile device’s battery life, while meeting the output power and linearity requirements of targeted wireless communication standards. Moreover, multi-mode multi-band operations should be possible with minimum hardware redundancy. To achieve these objectives, a circuit approach is first developed to overcome the low breakdown problem in CMOS, allowing the benefits of Moore’s law to be applied at higher power level than previously possible. A new amplitude modulation scheme is then developed in the later part to simplify 20 the transceiver architecture, employing the high integration levels attainable in CMOS.

The proposed digitally-controlled technique enables direct software programmability of the transceiver output, which can facilitate multi-mode multi-band operations and pro- grammable functionality.

The dissertation consists of four chapters. The background and fundamentals of power amplifier design has been introduced in the first chapter, together with a brief discussion on modern wireless communication standards and their performance requirements related to power amplifier design.

Chapter 2 will focuses on the stacked-FET technique to address the low breakdown problem in CMOS power amplifiers. It begins by discussing breakdown mechanisms in short-channel CMOS devices. The impedance matching network design and the associated loss are then examined to illustrate how a reduced voltage headroom can lead to a lower power efficiency in power amplifiers. Next, existing power combining techniques are reviewed and the stacked-FET topology is proposed as an attractive solution. Finally, the circuit design, implementation and measurement results are presented and discussed.

In chapter 3, a new polar-based digital RF transmitter architecture will be explored for multi-mode multi-band applications. The overall transmitter architecture is

ﬁrst proposed, making use of available RF switches in an advanced silicon-on-insulator

CMOS process. Next, the system-level requirements are examined and the circuit design, implementation and measurement results are then discussed in details including possible strategies for achieving power control requirements.

Chapter 4 concludes the whole dissertation. Chapter 2

Stacked-FET Power Ampliﬁers

2.1 Introduction

CMOS technology has become a desirable choice for research on single-chip radio transceivers in recent years due to its low cost and high-integration capability.

Among other advantages, CMOS power ampliﬁers (PAs) offer the potential of reducing complexity and cost by enabling the combination of a complete transceiver and digital baseband circuitry on the same chip. However, designing a high-performance RF PA on

CMOS remains a challenging task, especially with the on-going technology scaling to deep submicron dimensions [21–23].

The critical issues for CMOS PA design are the low breakdown voltage and high knee voltage of the device, which limit the allowable drain voltage swing. Various breakdown and degradation mechanisms in submicron CMOS include gate oxide breakdown, hot carrier degradation, punch-through and drain-bulk breakdown [6, 24]. The gate oxide breakdown is a catastrophic effect that permanently damages the device while the hot carrier degradation can cause a gradual degradation in the device performance over time.

These effects should be avoided by ensuring in the design that the transistor’s drain-gate,

21 22

gate-source and drain-source voltages (VDG, VGS, and VDS) do not exceed pre-speciﬁed values [24]. To obtain high output power, a typical approach is to increase the device size for higher drain current swing, resulting in lower input impedance, and thus, more difﬁcult input matching design. More severely, the required output impedance transformation ratio from the original load impedance to 50 Ω becomes too high, especially for

Watt-level output power required in modern wireless applications, resulting in high loss in the output matching network, and thus, low efﬁciency.

2.2 Breakdown Mechanisms in CMOS

Breakdown occurs in a short-channel MOSFET when the drain voltage relative to the gate voltage and the source voltage exceeds a certain value. The resulting high electric ﬁeld can lead to various phenomena that cause a performance degradation over time or an eventual device failure. Those phenomena are discussed in this section.

2.2.1 Gate Oxide Breakdown

When a large electric field is applied across an oxide layer, significant electron tunneling can take place. The time-dependent tunneling current usually decreases grad- ually until the oxide suffers a dielectric breakdown, where the oxide layer permanently loses its property as a good insulator. This phenomena involves many physical mechanisms such as impact ionization in the oxide layer, creation of electron and hole traps in the oxide, electron and hole trapping, and creation of surface states at the oxide-silicon interface [17]. This breakdown process is especially critical in CMOS as the gate oxide thickness is reduced in each process generation. To avoid this failure, it is important to keep the gate-drain and the gate-source voltages below pre-specified values. 23

2.2.2 Hot Carrier Degradation

Under a large drain-source voltage in a short-channel MOSFET, the electric field across the channel can be extremely high. Electrons gain energy from the field as they move along the channel and possess high kinetic energy close to the drain enough to generate more electrons and holes by impact ionization as shown in Fig. 2.1. These secondary electrons and holes result in substrate current and higher drain current. The substrate current will create a voltage drop that tends to forward-bias the source junction and lower the threshold voltage. As a result, the channel current increases and the positive feedback is triggered. This process usually causes a gradual degradation in device performance but can often result in permanent damage to the MOSFET as hot carriers are injected into the oxide in the gate-drain overlap region. To prevent this degradation process, the drain-source voltage should be kept below a pre-specified value and a large drain current should be avoided when the drain-source voltage is high.

Vds >> Vdsat Gate

n+ Source n+ Drain Electron current

Impact ionization

Figure 2.1: Impact ionization at the drain.

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2.2.3 Punch-Through

Punch-through can occur when the drain-bulk depletion region extends all the

way to meet the source-bulk depletion region under a large drain-source voltage, result-

ing in a direct ﬂow of current from drain to source. This process can occur even in an

absence of a gate bias voltage and become a signiﬁcant reliability problem with a shorter

channel length.

2.2.4 Drain-Bulk Junction Breakdown

In a standard CMOS process, the bulk is connected to ground or a ﬁxed electrical

potential. The drain-bulk junction diode experiences a reverse bias proportional to the

drain voltage. Therefore, it is important to limit the drain voltage within the reverse

breakdown voltage of the drain-bulk junction diode.

Rop Lm 2.3 Impedance transformation andPA Matching Network

Cm RL Loss

Rop R`op Lm RLm Lm PA PA Vout-rms

Cm RL Cm RL

Rop

R`op (a) (b) RLm Lm PAFigure 2.2: Impedance transformation network: (a) an L-match network and (b) an L- matchVout-rms network with inductor loss. Cm RL

Rop In RF power ampliﬁer design, it is typically necessary to match a 50-Ω load 25 to a smaller impedance in order to achieve a larger output power. For a linear power ampliﬁer, the optimal impedance in terms of output power and supply voltage can be expressed as,

2 2 1 (Vmax Vmin) 1 (2Vdd Vmin) Rop = − = − . (2.1) 8 · Pout 8 · Pout To provide a 1-W output power with a 1.8-V supply and a knee voltage of 0.5

V, for example, an optimal impedance of 1.2 Ω is required. The optimal impedance becomes even smaller as the breakdown voltage is reduced further in advanced CMOS technology, resulting in high power loss in the matching network. Fig. 2.2(a) illustrates an L-match, which is the most widely used impedance transformation network with a quality factor Qm deﬁned as

s RL Qm = 1, (2.2) Rop − and the values of matching components Lm and Cm can be obtained from

Q R L = m op (2.3) m ω

Qm Cm = . (2.4) ωRL The power loss of an on-chip L-match network is generally dominated by the loss of the matching inductor, as shown in Fig. 2.2(b), due to its low quality factor QL deﬁned as

ωLm QL = . (2.5) RLm 26

At the resonance frequency, the optimal impedance becomes

Rop0 = Rop + RLm. (2.6)

The total power ﬂowing into the impedance transformation network and the power delivered to the load are

2 Vout rms Pin m = − (2.7) − Rop + RLm

2 Rop Pout m = Vout rms 2 . (2.8) − − (Rop + RLm) Consequently, the efﬁciency of the matching network and the effective impedance transformation ratio can be calculated as

QL ηm = (2.9) QL + Qm

RL rm0 = ηm = ηm rm. (2.10) · Rop · Obviously, the efﬁciency of an impedance transformation network will depend on both the quality factor of matching components and the intended impedance transformation ratio.

2.4 Power Combining Techniques: Prior Art

Due to the low breakdown voltages in CMOS, achieving a large output power with a single device leads to a high loss in the matching network as discussed in the 27

previous section. Moreover, the device is usually required to conduct a large drain cur-

rent, making the power efﬁciency more sensitive to supply parasitics. An alternative

way is to use multiple devices and their power can be combined to reach the required

output power. Several approaches exist in the literature that can combine power of mul-

tiple devices in parallel. Among them, transformer-based techniques have been widely

investigated in recent time with some excellent results [5, 24, 25]. However, most of

these techniques are only suitable for nonlinear ampliﬁcation while on-chip transform-

ers require a large die area. In [5], a fully-integrated CMOS power ampliﬁer was ﬁrst

demonstrated using slab inductors to realize an on-chip distributed active transformer

structure (DAT) as shown in Fig. 2.3. It delivers a 2-W output power at 2.4 GHz with a 374 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 37, NO. 3, MARCH 2002 41% PAE using a 2-V supply.

Fig. 6. Circular geometry power amplifier with four push–pull amplifiers and eightFigure transistors. 2.3: Distributed active transformer structure [5].

Alternatively,substrate multiplecurrent and devices power can loss be caused combined by it in will series be reduced. such that the output Third, the metal width of the inductor may be increased beyond the maximum set by the spiral geometry. With wider metal, Fig. 4. Effective impedance at the transistor drain. (a) Even harmonicvoltage signals. swing increases while avoiding any device exceeding its breakdown voltage (b) Odd harmonic signals. the series metal resistance is reduced, although capacitive limits. The mostcoupling basic to technique the substrate of this is type increased. is the cascodeThis allows conﬁguration, a better commonly optimization of the inductor and in many cases the total loss employed tocan improve be significantly gain performance reduced. in lower-frequency ampliﬁer design. As shown A slab inductor is used as drain inductor , as shown in Fig. 3, in order to control the impedances at the fundamental frequency and harmonics and also to provide a path for the dc supply current.

C. Circular Geometry Circular geometry is a means to create low-loss low- Fig. 5. Comparison of the loss mechanisms for a one-turn spiral and a slab impedance virtual ac grounds while using several power inductor. amplifier blocks simultaneously. For instance, Fig. 6 shows the primary circuits with four push–pull power amplifiers and eight transistors. By providing a short circuit between the drains at each odd This architecture allows the creation of virtual ac grounds harmonic using a simple parallel LC tank tuned to a frequency without having to connect together the sources of the pair of slightly above the fundamental frequency, the drain impedance transistors of each push–pull amplifier, as shown in Fig. 3. With will be inductive at the fundamental and will be small at odd slab inductors, this connection is physically impossible, without harmonics and large at even harmonics. If transistors are driven compromising the amplifier operation, as the slab inductors into saturation, these impedances shape the drain waveforms to create a large distance between the sources. If a long metal line perform the high efficiency class E/F operation [14]. is used to connect the sources of this pair of transistors, the B. Slab Inductor inductance of this metal will be comparable to that of the drain slab inductor. The resulting source degeneration inductor will On-chip slab inductors2 present a significantly higher seriously degrade the amplifier performance and hence should and consequently lower loss when compared to conventional be avoided. low-impedance single-turn spiral inductors. Several factors AC virtual grounds for the fundamental and all odd harmonics contribute to the higher of the slab inductors. First, the negative can be created in the corner points of the circular geometry by mutual inductance between the current through metals on the op- connecting together the sources of the transistors of the adja- posite side of the spiral are reduced. Hence, the total metal length cent push–pull amplifiers. By driving these transistors in op- to obtain the same inductance is shorter than the circumference of posite phase, as shown in Fig. 4, their source currents, which the loop. Therefore, the resultant inductor demonstrates a lower belong to different push–pull amplifiers, have the same ampli- total series metal resistance, as shown in Fig. 5. Second, the shunt tude and the opposite phase and therefore cancel each other. resistance through the substrate between the two terminals of The result is similar to connecting the sources of the pair of the inductor, and , will be higher because of the larger transistors belonging to the each push–pull amplifier with short distance between them, as illustrated in Fig. 5. Thus, the low-impedance connection. Two electrical diagrams show how 2Slab inductors are two-port inductors formed by a straight piece of metal, as four push–pull amplifiers of Fig. 7 are rearranged to form the opposed to curled metal used in one- or two-port spiral inductors. circular geometry of Fig. 8.

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in Fig. 2.4, common-source and common-gate transistors are connected in series to allow a larger voltage swing at the drain of the common-gate device. Unfortunately, the voltage stress is not equally divided between the two transistors and the common-gate transistor is stressed more, especially across its drain and gate terminals.

VDD

RF Choke

Matching Network

Vbias

Vin

Figure 2.4: Cascode conﬁguration.

To solve the uneven stress problem, a self-biased cascode structure, shown in

Fig. 2.5, was presented in [6]. The capacitor Cb is added at the gate of the cascode device to allow an RF swing and the drain-gate feedback resistor Rb is used for biasing as well as providing an attenuated RF swing at the gate due to the low-pass nature of Rb and Cb. The reported power ampliﬁer, fabricated in 0.18-µm CMOS, provides 23-dBm output power with a PAE of 42% at 2.4 GHz using a 2.4-V supply.

To combine more devices in series, one of the earliest proposed techniques is 29

Figure 2.5: A self-biased cascode power ampliﬁer [6].

the bean stalk amplifier proposed by K.J. Dean in 1964. Shown in Fig. 2.6, a ladder of resistors is used to bias and drive several BJT transistors connected in series such that the voltage stress is divided across all devices. This technique, however, is only suitable for low-frequency design since the input signal has to propagate up to the gates of all stacked devices so the devices are not well synchronized to add up in phase, degrading the output power, efficiency, and linearity. For high-frequency high-voltage applications, another technique was presented by Shifrin in 1992, illustrated in Fig. 2.7. A resistive ladder is also used in this structure for DC biasing and only the common-source device is driven by the input. Inductors are used for interstage matching. while capacitors are employed to allow RF swing at the gates of stacked devices. The reported power amplifier delivers an output power of 36 dBm with a 12-dB gain and a 20% efficiency at 4.5 GHz using three FETs [8]. 30 43

51 in 1992 [3.11]. In this case,Figure the 2.6: dc Beanbias stalkvoltage ampliﬁer is still [7]. applied in series, but the

RF output combinationFigure 3.1is in Thecascade Bean as is Stalk shown Amplifier in Figure 3.9. [3.2] The inductors used in the series networks are not used for isolation, but for interstage matching instead. Examination of Figure 3.1 shows that this amplifier is clearly intended for low frequency operation only. For high frequency operation,+Vdd the signal from • • •

the single inputRF In port wouldR 1have to propagate• • • up Rthen base Rconnectionn+1 RF Out ladder which would cause a delay in the arrival at the uppermost device. This would Figure 3.9 Hittite High Voltage Power Amplifier introduce an imbalanceFigure in 2.7:the Hittite output high-voltage and would power ampliﬁerincrease [8 ].output distortion. This could be improved to a certain extent by adding speed up capacitors to the The input to the amplifier is driven by a single common source stage, input network. which drives a cascade of common gate amplifiers. When compared to the common source amplifier, this configuration offers a much higher output 3.2 Classimpedance G Power which Amplifierconsiderably eases the matching problem common to high powerThe classRF amplifiers. G amplifier was developed by Hitachi in 1976 as a solution to Successful operation is reported for a 3 FET circuit at 4.5 GHz, with a the low efficiency problems facing the high power audio amplifiers at that time gain of 12 dB at an output power of 36 dBm and efficiency of 20 %.

3.6 Stacked FET RF Power Amplifier

Today's power amplifier designers face a problem similar to that which

led Dean to develop the bean stalk amplifier. Although the trend for commercial products is to smaller size and lower power, there is still a requirement for high power, high frequency amplifiers in both base station and satellite communications. These designs are presently dominated by the use of very large MESFET devices which are designed for high power use. Due to their large size, the input and output impedances in these devices are very low, 52 Ω Ω approaching as low as 0.5 at the input and 3 at the output, which greatly 31 increases the difficulty of the matching problem. Another issue is that costs on these devices can approachIn recent $2000 years, US there each have for been satellite many more applications. variations of device-stacking tech-

Clearly thereniques is a investigatedstrong motivation in the literature. to develop In [ 9an], aalternative 900-MHz transformer-coupled to this stacked- approach. The stackedFET PA device was reported, structure where definitely on-chip offers transformers a solution were usedto the in parallel to couple the output impedance problem, and as it allows the use of normal devices, it may input signals into series-connected FETs. A similar approach was also demonstrated offer a reduction in overall cost as well. in HBT with series input feed [10]. These transformer-coupled techniques, illustrated In one sense, the stacked FET amplifier may be considered a dual of the in Fig. 2.8(a) and Fig. 2.8(b), eliminate the synchronization problem found in the bean standard large device application in that the high level of drive current is traded stalk ampliﬁer, making it more suitable for RF applications, even though, the transform- for an increased supply voltage. An example of a four FET stack is shown in ers consume a large die area. 2808 IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES, VOL. 55, NO. 12, DECEMBER 2007 Figure 3.10 below.

TABLE II MAGNITUDE AND PHASE ERROR OF THE INPUT COUPLED Vdd LINE LADDER,RELATIVE TO Q1

• • Pout

Pin• • • • The device used is seven single two-finger 20- m devices • • combined in parallel with a 3- emitter ballast resistor in each cell to reduce the multifinger emitter collapse phenomenon [18]. • A voltage level of 3.75 V and quiescent current of 110 mA is chosen for the design. This sets the voltage of the entire ampli- •• fier at 15 V. • Due to the particular layout of the transistor, the bottom transistor Q1 has a slightly different layout compared to the other • three cells; this, in turn, causes a slight difference in the input feed signal of Q1. In fact, the magnitude of the Q1 feed is smaller than the other three cells. The phase and magnitude difference of the input coupled line ladder, relative to the first device Q1, is listed in Table II. Based on (17) and Fig. 6, the phase difference has a minimal effect on the combination efficiency of Vgg at most 2%. However, the asymmetric layout does affect the lin- Fig. 8. Simplified schematic of the HBT series-input stack amplifier. earity performance, which is demonstrated in Section II-C. This Figure 3.10 Four (a)FET Stack Amplifier (b) is also observed from the load lines. Fig. 9(a) shows the load lines of the individual transistors in an ideal simulation (lumped Inspection Figureof Figure 2.8: 3.10 Transformer-coupled shows some of input-feed the key issues techniques: in the (a) stacked Parallel-input-feed stacked components only) at 25-dBm output power; it is clear that the to a minimum to reduce the nonideal effects. Care should FET PA [9], and (b) Series-input-feed stacked HBT PA [10]. four load lines have the same shape and are nearly identical in be taken at the layout so that each cell can be easily con- size. However, once all of the components are replaced with EM nected with each other both at the input and output end. simulations, the load lines of the transistors degrade to the con- 4) Combine the cells; design the output matching network to tours shown in Fig. 9(b); in particular, the load line of Q1 is its optimum load impedance, and biasing circuits. distinctively different from the other three, which is the mani- 5) Design the input matching circuit. festation of the different layout in Q1. The voltage clipping of To validate the series-input and series-output stacked ampli- Q1 in Fig. 9(b) is also evidence that Q1 is the dominant factor in fier, a four-cell stack amplifier operating at 5–6 GHz with 1-W the earlier compression of the stacked amplifier in power mea- saturation power is designed using WIN Semiconductors’ 2- m surements. HBT process.1 A major feature of the series-input stack is that The transformer couplers are implemented using coupled the input impedance also increases with the number of cells; lines. The lines are 290 m in length, linewidth of 5 m, and therefore, it is possible to make both the input impedance and gap of 2 m. The length of the coupled line is very short com- output optimum load to near 50 at the same time to simplify pared to a quarter-wavelength line at 5 GHz, and because of the matching designs. its thin linewidth and the small spacing, the coupling is mostly A simplified schematic, excluding the matching and biasing magnetic, which can be modeled as a transformer in Fig. 2(a). circuits of the series-input stack amplifier, is shown in Fig. 8. It Based on EM simulations, the resistance in each inductor is is composed of four identical self-biased HBT devices in se- 2 , the self-inductance is 0.32 nH, is 0.23 nH, and the ries and coupled lines as the transformer coupler. Series ca- mutual inductance is 0.19 nH. pacitors are placed between the base and emitter of each tran- Circuit simulations are conducted using Agilent’s ADS soft- sistor to serve as dc blocks. Due to the layout configuration ware , and electromagnetic (EM) simulations using SONNET of the HBT device, the crossover between the transformer and [17]. Load–pull simulations at 5 GHz are conducted to deter- base–emitter represents how the coupled-line transformer ac- mine the optimum load impedance. The output power, optimum tually connects to the device, instead of an actual crossover. load impedance, and gamma of the device are listed in Table III Such a connection will change the direction of the current in with respect to the number of stacked cells. The result is con- the output coil of the linear analysis in Section II, which will sistent with the stack amplifier theory with the optimum load alter the (2)–(12) slightly, but with the same advantages of in- impedance and output-power in proportion to the number of creased input impedance, output impedance, and power combi- devices stacked. The input impedance of the amplifier also in- nation. The input is fed from the bottom up, instead of top down creased accordingly to the number of cells stacked. The four-cell in the analysis, allowing easier layout of the RF and dc pads. input impedance is around 12.5 , which is over a fourfold in- 1Online information of process at http://www.winfoundry.com crease of 2.5 of a single transistor.

Authorized licensed use limited to: Univ of Calif San Diego. Downloaded on September 11, 2009 at 15:42 from IEEE Xplore. Restrictions apply. 1320

Ultra-Broadband GaAs HIFET MMIC PA Amin K. Ezzeddine and Ho C. Huang AMCOM Communications, Inc., 22300 Comsat Drive, Clarksburg, Maryland 20871, USA (a 1)

Abstract - This paper reports the first MMIC using the HIFET (High-Voltage, High-Impedance FET) concept with very broadband power performance and small die size. This GaAs II. HIFET CONFIGURATION MMIC power amplifier has a gain of 21dB ± ldB and over 2W of P1dB over the entire 30 MHz to 2.5 GHz frequency band with The HIFET configuration is to stack up existing mature 20% efficiency, at a bias voltage of +20V. We believe that this is device, such as FET, CMOS, or GaN HEMT both DC and RF the first MMIC ever reported which achieves this combination of in series to operate at high voltages and high impedance while instantaneous bandwidth, output power, and efficiency, within a acting also as a power combiner. Fig. 1 shows an example of die size of 4 mm2. 4 identical FETs connected in series in HIFET configuration. 32 Index Terms - High-voltage techniques, Microwave devices, The positive drain bias is applied to top FET4. But the Microwave power FET amplifiers, MMIC power amplifiers, Power amplifiers, Power FETs, Power semiconductor devices. negative gate bias is applied only to bottom FETI. The shunt resistors are designed for RF feedback as well as to ensure that the gate-to-source bias of FET2, FET3 and FET4 are the same I. INTRODUCTION In [11,as26,FETI27], high-voltage/high-power, such that all FETs have (HiVP)the PAssame weredrain-to-source presented, where sev- Multi-octave bandwidth power amplifiers are needederal transistorsfor voltage. are connectedThe RF in seriesinput tois achieveonly applied high outputto bottom voltageFETI, swing.and The struc- EW, broadband software radio (such as JTRS), and the RF output is from top FET4. This arrangement has the instrumentation applications. The most popular approachture, illustratedto advantage in Fig. 2.9of,improving uses feedbackthe HIFET shunt resistorsamplification togethergain withover appropriatethe ca- date to achieve such broadband is the Traveling Wave (TW) individual FET gain because the RF input is only applied to amplifier configuration. The drawbacks with TW amplifierpacitiveare loadingFETI, of theyet gatethe nodesRF is tofrom controlthe drain voltageof FET4, swingswhich at theis gatesthe total of the stacked power of HIFET. that it has relatively low efficiency and that it requiresdevices.large chip real estate, leading to high price. Microwave and mm-wave semiconductor devices such as GaAs FET and CMOS usually have sub-micron features and Vdd=4Vds high-doping densities to achieve enough gain at high Choke REOutputRout frequencies, but resulting in low breakdown voltages. Therefore these devices have to be operated at relatively low Vg3=3Vds+VgsW voltages (< IOV). Consequently, in many applications Vd3=3 Vds requiring high voltages, designers try to increase the voltage bias of microwave circuits by connecting several devices DC Vg3=2Vds+Vgs in series but RF in parallel [1-2]. While connecting devices IC2 _ , Vd2=2 Vds DC in series helps in biasing at higher voltages, the RF impedance of the RF parallel combination becomes very low, Vg2=Vds+Vgs leading to difficulties in for broadband I E ~~~ET2(W/4) matching applications. > Recently, there have been reports [3-6] of high DC bias I t Vdl=Vds voltage operation from FET, PHEMT, SiC and GaN devices. > ET1 Match (W/4) But theses devices are either very expensive or still in the R&D stage with immature technology. Vgg In this paper, we report an innovative approach to achieve a high-voltage, broadband, low-cost MMIC PA, with state-of- the-art performance having 21dB gain, 2W output power and Fig. 1. FigureHIFET 2.9:configuration, A HiVP powerwith ampliﬁerboth DC [and11].RF in series. 20% efficiency over an instantaneous bandwidth from 30MHz to 2500MHz, with a small chip size of 4 mm2. We used the Table I illustrates the advantages of using the HIFET. The High-Voltage/High-Power configuration described in [7] to major advantages are: a). High DC bias voltage b) High RF impedance, which leads to broadband capability and high achieve this performance. We believe this is the first2.5reported Proposed Stacked-FET Design Concept on the combination of bandwidth, output power, gain, power, and c) A bonus gain of 10Logl0(N) dB over the efficiency and die size. individual FET gain, which leads to high frequency capability 2.5.1 Basic(N Operationis the number of FET in series).

The stacked-FET structure used in this work is shown in Fig. 2.10. The circuit is

0-7803-9542-5/06/$20.00 C2006 IEEE composed of a common-source input transistor and three stacked transistors connected

Authorized licensed use limited to: Univ of Calif San Diego. Downloadedin on series August 19, so 2009 that at their 20:47 from output IEEE swingsXplore. Restrictions are added apply. in phase. Unlike in a cascode conﬁguration 33

OUT

4Vm Vg4 Ci 4Ropt m4

3Vm Vg3 C3 Zs4 = 3Ropt m3

2Vm Vg2 C2 Zs3 = 2Ropt m2

Vm Zs2 = Ropt = Vm/Im IN m1

Figure 2.10: Proposed stacked-FET PA basic structure. 34

where the gate of the common-gate transistor is RF-grounded, a relatively small external gate capacitance (C2, C3, and C4) is introduced to allow an RF swing at the gate of each stacked transistor. The external gate capacitance and the gate-to-source capacitance

(Cgs) of each stacked transistor form a capacitive voltage divider to produce the proper in-phase voltage swing at the gate and drain. This approach systematically reduces the drain-gate and drain-source voltage swings of both the common-source and common- gate transistors under large signal operation, unlike in a cascode structure where the drain-gate voltage swing of the common-gate transistor becomes the bottleneck [6].

Cgd GDif

Ci Cgs vgs gmvgs ro ZL

ig S

it Zsi

Figure 2.11: Effect of an external gate capacitance on a stacked FET’s source input impedance.

A high-frequency stacked FET model is shown in Fig. 2.11, where ZL is the impedance seen by the drain of the device. Assuming that ro is large, a test voltage can be applied at the source and it follows from KCL and KVL that

(if ig) (ig) vt = − (2.11) sCi − sCgs 35

gmig it = ig + (2.12) − sCgs

gmig (vds + vt) if = + (2.13) − sCgs ZL

if (ig) vds = + (2.14) sCgd sCgs

(vt + vds) it + ig if = . (2.15) − ZL

From (2.11)-(2.15), the source input impedance Zsi of a stacked transistor can be derived as

vt Cgs + Ci + Cgd(1 + gmZL + sCgsZL + sCiZL) Zsi = = . (2.16) it (gm + sCgs)(Cgd + Ci + sCgdCiZL) In the low RF frequency range, (2.16) can be simpliﬁed by assuming that the feedback current through Cgd is negligible and the equation becomes

C 1 1 Z = (1 + gs ) ( ) si C · g k sC i m gs (2.17) Cgs 1 (1 + ) for f0 << Ft. ≈ Ci · gm The small-signal voltage gain of the PA can be derived as

gm1RL Av = (1 + sCgs2 ) (1 + sCgs3 ) (1 + sCgs4 ) gm2 · gm3 · gm4 (2.18) g 1R for f0 << F ≈ m L t

For a low frequency design where the carrier frequency (fo) is much lower than the cutoff frequency of the device (Ft), the source input impedance Zsi of a stacked 36

transistor is inﬂuenced by the value of the external gate capacitor Ci relative to its gate- source capacitance Cgs. Zs2, Zs3, and Zs4 are approximately purely-resistive and all four devices in series share the same constant current swing (Im). The values of external capacitors (C2 - C4) should be set such that Zs2, Zs3, and Zs4 are Ropt, 2Ropt, and 3Ropt, respectively, and the optimum output load impedance is 4Ropt. This ensures that each transistor has the same drain-source, drain-gate, and gate-source voltage swings while the absolute voltage swings with respect to ground increase as one moves up the ladder.

As the operating frequency approaches Ft, the reactive component of Zs2, Zs3 and Zs4 due to Cgs becomes significant. Also notice from Fig. 2.11 and (2.16) that, without assuming a low-frequency operation, Zsi is also influenced by ZL and Cgd and ZL is not necessary purely resistive. In addition, all transistors will see slightly different drain currents due to currents leaking out through Cgs. These effects result in more difficult waveform shaping to achieve high-efficiency operation on all transistors simultaneously.

2.5.2 Stacked-FET vs. Parallel

Table 2.1 compares some important parameters of PAs using parallel and stacked-

FET conﬁgurations. Compared to the n-parallel-FET PA with the same output power and DC power, the n-stacked-FET PA has n times higher voltage gain and power gain.

The input and output impedances are n times and n2 times higher, respectively, resulting in improved input and output matching bandwidths and less power loss in the output matching network. 37

Table 2.1: Comparison of parallel and Stacked-FET conﬁgurations

Parameter Unit FET n-Parallel FET n-stacked FET

Peak Drain Current I n I I m · m m Peak Drain Voltage V V n V m m · m Input Capacitance C n C C g · g g Output Impedance R Ropt n R opt n · opt Output Power 1 V I 1 V nI 1 nV I 8 · m · m 8 · m · m 8 · m · m Voltage Gain g R ng Ropt g nR H9 SOI m · opt m · n m · opt z full isolation between devices (and between SOI GATE blocks), no latch-up although very high resistivity TR. is used! (> 1 kOhm-cm!) TR. SOURCE C SOI 160nm DRAIN OX N+ Pwell N+ OX z reduced losses in high frequency range thanks TR. to high resistivity BURIED OXIDE BURIED400nm OXIDE z improvement of Q factor for inductors thanks to D high resistivity Substrate (> 1kOhm-cm) z reduced substrate coupling thanks to high resistivity Figure 2.12: Silicon-on-insulator CMOS technology. z improved FOM in digital circuits due to floating body (coupling between gate and body) and to reduced junction capacitances (min 25 % power reduction vs bulk at same speed) z ESD solution availability Figure 2.13: Silicon-on-sapphire CMOS technology. z SOI cost but must be carefully considered depending on volume and area saving

CCD CFM BU Company Confidential 38

2.6 Alternative CMOS Technologies

Buried oxide Djdb p-well HR-sub

(a)

Djdb Bulk D1 p-sub p-well n-iso Djsb D2 D3

(b) (c)

Figure 2.14: Simpliﬁed schematics of stacked NMOS transistors using different process technologies: (a) Partially-depleted SOI CMOS used in this work, (b) Bulk CMOS, and (c) Triple-well CMOS.

The partially-depleted silicon-on-insulator (SOI) and silicon-on-sapphire (SOS)

CMOS technologies, shown in Fig. 2.14(a) and Fig. 2.13 respectively, used in this work are particularly attractive for the stacked-FET technique due to their lack of body effect 39

and relatively small parasitic junction capacitance. As shown in a simpliﬁed model in

Fig. 2.14(a), body effect can be avoided by connecting the p-well of each stacked transistor to its source. By contrast, in bulk CMOS as illustrated in Fig. 2.14(b), source-body capacitance and body effect progressively reduce gain of the transistors in the upper sections of the stack. Moreover, the maximum allowable supply voltage is limited by the breakdown voltage of the drain-bulk junction diode (Djdb). An alternative solution is to use a triple-well CMOS process as shown in Fig. 2.14(c), where the p-well of each transistor can be tied to its source to avoid body effect. The n-iso layer can be tied to the supply voltage to prevent the p-well/n-iso junction diode (D2) from turning on. It should not be tied to any of the device’s terminals due to large capacitance from the n-well to the substrate. The maximum allowable supply voltage is limited in this case by the breakdown voltage of the n-iso/p-sub junction diode (D3).

2.7 Fully-Integrated Stacked-FET Linear PA Design in SOS CMOS

As a prototype [12], a fully-integrated stacked-FET linear power ampliﬁer was designed at 1.88 GHz using the Peregrine Semiconductor 0.25-µm SOS CMOS process for which the drain-to-source breakdown voltage is 2.75 V. The triple-stacked FET structure used is shown in Fig. 2.15 together with on-chip input matching and gate bias circuit. The resistors R1-R4 are used only to provide gate biasing of the three FETs. The external capacitances C2 and C3 are determined to enable each drain and source to sustain large voltage swings in a way that each FET has the same drain-source, gate-source and drain-gate voltage swings, as described in the earlier section. 1

40 A 20 dBm Linear RF Power Amplifier Using Stacked Silicon-on-Sapphire MOSFETs

Jinho Jeong, Sataporn Pornpromlikit, Peter M. Asbeck and Dylan Kelly

Out Abstract— In this letter, a fully integrated 20 dBm RF power Vgg amplifier is presented using 0.25 µm-gate silicon-on-sapphire 3Ropt (SOS) MOSFETs. To overcome the low breakdown voltage limit R of MOSFETs, a stacked FET structure is employed, where 4 3Vm transistors are connected in series so that each output voltage swing is added in phase. By using triple-stacked FETs, the C optimum load impedance for a 20 dBm power amplifier increases 3 2Ropt to 50 ohm, which is nine times higher than that of parallel FET Cgs R topology for the same output power. Measurement of a single- 3 2Vm stage linear power amplifier shows small-signal gain of 17.1 dB and saturated output power of 21.0 dBm with power added C efficiency (PAE) of 44.0 % at 1.88 GHz. With an IS-95 CDMA 2 Ropt=Vm/Im modulated signal, the power amplifier shows average output Cgs R2 V power of 16.3 dBm and PAE of 18.7 % with ACPR below -42 dBc. IN m Index Terms— MOSFET, power amplifier, silicon-on-sapphire, stacked transistors Im R I. INTRODUCTION 1

Recently, there has been intensive research on single chip Fig. 1 Schematic of triple-stacked FET power amplifier. radio transceivers using the CMOS process to reduceFigure 2.15: Schematic of the fully-integrated triple-stacked FET power ampliﬁer in packaging complexity and lower the overall system cost.SOS A CMOS [12]. transistors connected, not in parallel, but in series, to achieve CMOS RF power amplifier is one of the bottleneck high output voltage swing. Compared to the parallel components for full integration of an RF transceiver [1]~[3]. configuration, the output load impedance becomes higher and The critical issue for CMOS power amplifier design is the low the input impedance remains nearly constant as the number of breakdown voltage and high knee voltage of MOSFETs, stacked transistors increases, resulting in reduced impedance which limit the drain voltage swing [4]. Therefore, to obtain matching ratio and higher efficiency. In [5], a linear power high output power, typically many devices are connected in amplifier was developed at 900 MHz using an on-chip parallel, increasing the output current swing. However, this transformer coupled and double stacked MESFETs. Recently, results in a decrease of input impedance due to the increased high power/high voltage power amplifiers were presented gate-to-source capacitance, which makes the input matching using directly stacked FETs without transformers in [6]. In the circuit design difficult. More seriously, the required load present paper, the stacked FET topology is applied to SOS impedance is so small that the impedance transformation ratio MOSFET technology, which is promising for single chip from 50 ohm becomes too high for output powers beyond 100 radio transceivers, since high resistivity sapphire substrates mW. The resulting circuits typically have low efficiency due provide high isolation between circuit blocks and high quality to dissipation within the output matching circuits. To factor (Q-factor) passive components [7]. overcome this limit of CMOS transistors, several approaches have been proposed including cascode structure [1], II. CONCEPT OF THE PROPOSED STACKED FETS distributed active transformer [4] and stacked FET power amplifiers [5][6]. A stacked FET structure has several The triple-stacked FET structure used in this work is shown in Fig. 1 together with on-chip input matching and gate bias circuit. Unlike in [6] where a feedback resistor from the drain Manuscript received April 28, 2006. This work was supported in part by the of top FET to its gate is introduced to allow voltage swing at University of California Discovery Grant program, and in part by the Korea Research Foundation Grant (M01-2004-000-20356-0). J. Jeong, S. the gate, a capacitive voltage divider consisting of the gate-to- Pornpromlikit and P. M. Asbeck are with University of California, San Diego, source capacitance of each FET (Cgs) and an external gate CA 92092 USA (phone : 858-534-8225; fax : 858-534-0556; e-mail : capacitance (C2, C3) is utilized. The resistors R1~R4 are used [email protected]). D. Kelly is with Peregrine Semiconductor, San Diego, CA 92121 USA (e-mail : [email protected]). only to provide gate biasing of the three FETs. The external

Each FET has the 1.512-mm gate width, so the total gate width is 4.536 mm.

For linear operation, the gate bias is set to 0.4 V with drain bias of 3.9 V, so each

FET has a drain bias of 1.3 V. The optimum output load impedance for 20 dBm output power is as high as 50 ohm (3Ropt in Fig. 2.15), as a result of the triple stacked FET structure. Therefore, there is no need for output matching circuit. The load impedance would be 5.6 Ω for 20 dBm output power in a parallel FET configuration (9x lower), which requires careful output matching circuit design and causes efficiency reduction due to the high impedance transformation ratio. The input matching is implemented with a high-Q on-chip inductor and capacitor as shown in Fig. 2.15. Fig. 2.16 illustrates the simulated load lines for each FET where the three transistors show the same drain- source and gate-source voltage swing as expected, which is essential for stacked FET power amplifier design, and means that each FET delivers its maximum available power.

A photograph of the fabricated power ampliﬁer is shown in Fig. 2.17. The chip size is 0.6 mm 0.9 mm. The small signal S parameters were measured by on-wafer probing. The bias current was 52 mA which was slightly lower than the design value.

The gain is 17.1 dB at 1.88 GHz as shown in Fig. 2.18. The input return loss is better than 15.0 dB between 1.78 GHz and 2.06 GHz.

For the power measurement, the chip was mounted on a coplanar waveguide

PCB using Duroid substrate with dielectric constant of 3.38. More than 10 gold wires were bonded to the chip, to minimize inductance between chip ground and the package ground. Off-chip capacitors of 51 pF were placed at input and output to provide a DC block. The drain bias circuit consisted of a quarter-wavelength line with a 33-pF shunt 42 2

0.20 Vg=0.7V Vg=0.5V

0.15 Top FET

Middle FET 0.10 Vg=0.3V

Drain current (A) current Drain 0.05 Vg=0.1V Bottom FET 0.00 0.0 0.5 1.0 1.5 2.0 2.5 3.0

Drain-to-source voltage (V) Fig. 3 Chip photograph of the fabricated SOS power amplifier. Fig. 2 Simulated load lines of each FET at the output power of 20 Figure 2.16: Simulated load lines of each FET at the output power of 20 dBm [122 ]. dBm. FETs. Secondly, the source and drain junction capacitances of 0.20 capacitances C2 and C3 are determined to enable each drain Vg=0.7V SOS MOSFETs are relatively small and nearly constant with Vg=0.5V and source to sustain large voltage swings in a way that each respect to voltage so that the performance degradation due to FET has the same drain-to-source, gate-to-source and drain- 0.15 these capacitances is minimized in stacked FETs. Top FET to-gate voltage swings (unlike the case for cascoded FETs). Each FET has the 1.512 mm gate width, so the total gate The swings can then all be designed to be as large as possible, Middle FET Vg=0.3V width is 4.536 mm. For linear operation, the gate bias is set to 0.10 while satisfying breakdown voltage limits. The output voltage 0.4 V with drain bias of 3.9 V, so each FET has a drain bias of swings of all three FETs are combined in phase so that the 1.3 V. The optimum output load impedance for 20 dBm voltage swing at the drain of top FET is three times higher Drain current (A) current Drain 0.05 output power is as high as 50 ohm (3Ropt in Fig. 1), as a result Vg=0.1V than the maximum available drain-to-source voltage swing for of the triple stacked FET structure. Therefore, there is no need Bottom FET single FET (Vm) with constant current swing (Im), while each 0.00 for output matching circuit. The load impedance would be 5.6 FET delivers the same power. This implies that the required ohm for 20 dBm output power in a parallel FET configuration, 0.0 0.5 1.0 1.5 2.0 2.5 3.0 load impedance will be NxN times higher than that of N- which requires careful output matching circuit design and Drain-to-source voltage (V) parallelFig. 3 Chip FET photograph configuration of the fa forbricated the sameSOS power output amplifier. power [6]. causes efficiency reduction due to the high impedance Fig. 2 Simulated load lines of each FET at the output power of 20 FigureAs well 2.17: as Chip providing photograph for of thean fabricated appropriate SOS power voltage ampliﬁer swing [12]. at the transformation ratio. The input matching is implemented with dBm. gate terminals, the finite external capacitors C2 and C3 adjust a high-Q on-chip inductor and capacitor as shown in Fig. 1. theFETs. input Secondly, impedance the source of middle and drain and junctiontop FETs, capacitances so that bottom of Figure 2 illustrates the simulated load lines for each FET capacitances C2 and C3 are determined to enable each drain andSOS middle MOSFETs FETs are relativelysee the smalloptimum and nearlyload constantimpedance with for and source to sustain large voltage swings in a way that each where the three transistors show the same drain-to-source and maximumrespect to voltagevoltage so swing that the [6]. performance The optimum degradation load impedance due to FET has the same drain-to-source, gate-to-source and drain- gate-to-source voltage swing as expected, which is essential increasesthese capacitances linearly iswith minimized the number in stacked of FETs FETs. in series as also to-gate voltage swings (unlike the case for cascoded FETs). Each FET has the 1.512 mm gate width, so the total gate for stacked FET power amplifier design, and means that each The swings can then all be designed to be as large as possible, shown in Fig. 1. Since the voltage swing is amplified through FET delivers its maximum available power. eachwidth FET, is 4.536 N-stacked mm. For FETlinear provides operation, N the times gate biashigher is set voltage to while satisfying breakdown voltage limits. The output voltage 0.4 V with drain bias of 3.9 V, so each FET has a drain bias of and power gain compared to N-parallel FETs. They also have swings of all three FETs are combined in phase so that the 1.3 V. The optimum output load impedance for 20 dBm voltage swing at the drain of top FET is three times higher N times lower input capacitance. Thus, a bigger device can be IV. MEASUREMENTS output power is as high as 50 ohm (3Ropt in Fig. 1), as a result than the maximum available drain-to-source voltage swing for usedof the with triple tolerable stacked FET input structure. capacitance Therefore, to minimize there is no the need knee A photograph of the fabricated power amplifier is shown in single FET (V ) with constant current swing (I ), while each m m voltagefor output effect matching on the circuit. output The power load and impedance efficiency. would In bethis 5.6 way, Fig. 3. The chip size is 0.6 mm × 0.9 mm. The small signal S- FET delivers the same power. This implies that the required theohm stacked for 20 dBm FET output can powerovercome in a parallel two majorFET configuration, limitations of load impedance will be NxN times higher than that of N- parameters were measured by on-wafer probing. The bias MOSFET,which requires low breakdowncareful output voltage matching and high circuit knee design voltage. and current was 52 mA which was slightly lower than the design parallel FET configuration for the same output power [6]. causes efficiency reduction due to the high impedance As well as providing for an appropriate voltage swing at the value. The gain is 17.1 dB at 1.88 GHz as shown in Fig. 4. transformationIII. DESIGN OFratio. TRIPLE The input-STACKED matching MOS is PimplementedOWER AMPLIFIER with The input return loss is better than 15.0 dB between 1.78 and gate terminals, the finite external capacitors C2 and C3 adjust a high-Q on-chip inductor and capacitor as shown in Fig. 1. Based on the concept presented in the previous section, a the input impedance of middle and top FETs, so that bottom Figure 2 illustrates the simulated load lines for each FET 2.06 GHz. and middle FETs see the optimum load impedance for fullywhere integrated the three powertransistors amplifier show the was same designed drain-to-source in the 1.88 and GHz For the power measurement, the chip was mounted on a maximum voltage swing [6]. The optimum load impedance rangegate-to-source using the voltage Peregrine swing 0.25 as expected,µm SOS whichCMOS is process,essential for coplanar waveguide PCB using Duroid substrate with increases linearly with the number of FETs in series as also whichfor stacked the drain-to-sourceFET power amplifier breakdown design, andvoltage means is that 2.75 each V. A dielectric constant of 3.38. More than 10 gold wires were shown in Fig. 1. Since the voltage swing is amplified through SOSFET CMOSdelivers processits maximum has severalavailable advantages power. for stacked FET bonded to the chip, to minimize inductance between chip each FET, N-stacked FET provides N times higher voltage structures. First of all, the insulating sapphire substrate (with ground and the package ground. Off-chip capacitors of 51 pF and power gain compared to N-parallel FETs. They also have 4 resistivity above 10 ohm-cm) doesn’t introduce body effect, were placed at input and output to provide a DC block. The N times lower input capacitance. Thus, a bigger device can be which could degradeIV. the M performanceEASUREMENTS of the middle and top used with tolerable input capacitance to minimize the knee drain bias circuit consisted of a quarter-wave long line with a A photograph of the fabricated power amplifier is shown in 33 pF shunt capacitor providing 2nd harmonic short circuit. voltage effect on the output power and efficiency. In this way, Fig. 3. The chip size is 0.6 mm × 0.9 mm. The small signal S- the stacked FET can overcome two major limitations of parameters were measured by on-wafer probing. The bias MOSFET, low breakdown voltage and high knee voltage. current was 52 mA which was slightly lower than the design value. The gain is 17.1 dB at 1.88 GHz as shown in Fig. 4. III. DESIGN OF TRIPLE-STACKED MOS POWER AMPLIFIER The input return loss is better than 15.0 dB between 1.78 and Based on the concept presented in the previous section, a 2.06 GHz. fully integrated power amplifier was designed in the 1.88 GHz For the power measurement, the chip was mounted on a range using the Peregrine 0.25 µm SOS CMOS process, for coplanar waveguide PCB using Duroid substrate with which the drain-to-source breakdown voltage is 2.75 V. A dielectric constant of 3.38. More than 10 gold wires were SOS CMOS process has several advantages for stacked FET bonded to the chip, to minimize inductance between chip structures. First of all, the insulating sapphire substrate (with ground and the package ground. Off-chip capacitors of 51 pF 4 resistivity above 10 ohm-cm) doesn’t introduce body effect, were placed at input and output to provide a DC block. The which could degrade the performance of the middle and top drain bias circuit consisted of a quarter-wave long line with a 33 pF shunt capacitor providing 2nd harmonic short circuit. 43 3

30 -30 40

20 S21 -40 30 10

0 -50 20

-10 PAE (%)

S22 ACPR (dBc) -60 10 S-parameters (dB) -20 S11 -30 -70 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 5101520 Output power (dBm) Frequency (GHz) Fig. 6 Measured ACPR and PAE performance as a function of Fig. 4 Measured S-parameters by on-wafer probing. Figure 2.18: Measured S-parameters by on-wafer probing [12]. average output power with IS-95 CDMA input signal. 50 100 PAE results in high output load impedance and reduced knee nd capacitor providing40 2 harmonic short circuit. 80 voltage effect, providing high efficiency for high output The measured large signal gain and PAE are shown in Fig. 2.19 with correspond- power. SOS CMOS technology, which has a relatively small 30 60 parasitic junction capacitance and no body effect, is used for ing DC current as a function of output power at 1.88 GHz. The ampliﬁer delivers 18.3 the implementation of the stacked FET power amplifier. The dBm output power at 1-dB gain compression point with PAE of 29.2%. The saturated fully integrated single-stage SOS MOS power amplifier 20 40 delivers a maximum output power of 21.0 dBm with the high power is 21.0 dBm with the maximum PAE of 44.0%. This high efﬁciency is attributed efficiency of 44.0 % at 1.88 GHz. To the best of authors’ to the high load10 impedance and the reduced knee voltage effect of the stacked20 FET topol- Gain Drain current (mA) knowledge, this is the first reported fully integrated SOS Gain (dB) and (%) PAE ogy. Using an IS-95 CDMA signal, ACPRs were measured at 885-KHz offset from the power amplifier operating in the GHz range. 0 0 center frequency of 1.88 GHz and are shown in Fig. 2.20 together with average PAE 510152025 ACKNOWLEDGEMENT as a function of average outputOuput power. power The difference (dBm) between upper and lower side We thank Peregrine Semiconductor for the chip fabrication.

ACPRsFig. is within5 Measured 0.6 dB, gain, indicating PAE low and memory DC drain effect. current The measured as a function ACPR is belowof output power with single tone input at 1.88 GHz. REFERENCES -42 dBc (the speciﬁcation for IS-95 CDMA operation) up to an average output power [1] T. Sowlati, and D. M. W. Leenaerts, “ A 2.4-GHz 0.18-um CMOS Self- Biased Cascode Power Amplifier,” IEEE J. Solid-State Circuits, vol.38, The measured large signal gain and power added efficiency No82, pp.1318-1324, Aug. 2003. [2] N. Srirattana, P. Sen, H. -M. Park, C. -H. Lee, P. E. Allen, and J. Laskar, are shown in Fig. 5 with corresponding DC current as a “ Linear RF CMOS Power Amplifier with Improved Efficiency and function of output power at 1.88 GHz. The amplifier delivers Linearity in Wide Power Levels,” in IEEE RFIC symp., June 2005, 18.3 dBm output power at 1 dB gain compression point with pp.251-254. PAE of 29.2 %. The saturated power is 21.0 dBm with the [3] Y. Ding and R. Harjani, “ A High-Efficiency CMOS +22-dBM Linear Power Amplifier,” IEEE J. Solid-State Circuits, vol.40, No.9, pp.1895- maximum PAE of 44.0 %. This high efficiency is attributed to 1900, Sept. 2005. the high load impedance and the reduced knee voltage effect [4] I. Aoki, S. D. Kee, D. B. Rutledge, and A. Hajimiri, “ Fully Integrated of the stacked FET topology. Using an IS-95 CDMA signal, CMOS Power Amplifier Design Using the Distributed Active- Transformer Architecture,” IEEE J. Solid-State Circuits, vol.37, No.3, adjacent channel power ratios (ACPRs) were measured at 885 pp.371-383, Mar. 2002. KHz offset from the center frequency of 1.88 GHz and are [5] J. G. McRory, G. G. Rabjohn, and R. H. Jonhston, “ Transformer shown in Fig. 6 together with average PAE as a function of Coupled Stacked FET Power Amplifiers,” IEEE J. Solid-State Circuits, vol.34, No.2, pp.157-161, Feb. 1999. average output power. The difference between upper and [6] A. K. Ezzeddine and H. C. Huang, “ The High Voltage/High power lower side ACPRs is within 0.6 dB. The measured ACPR is FET,” 2003 IEEE RFIC Symp., 2003, pp. 215-218. below -42 dBc up to an average output power of 16.3 dBm [7] K. Tsui, K. J. Chen, S. Lam and M. Chan, “0.5 um Silicon-on-Sapphire and PAE of 18.7 %. Metal Oxide Semiconductor Field Effect Transistor for RF Power Amplifier Application,” Jan. J. Appl. Phys., p. 4982-4986, Vol.42, No.8, August, 2003. V. CONCLUSIONS In this paper, a fully integrated linear RF power amplifier is presented using a triple-stacked FET structure in the 0.25 µm SOS CMOS process. Instead of a parallel FET structure, the stacked FET topology utilizing capacitive voltage dividers 3

30 -30 40

20 S21 -40 30 10

0 -50 20 44 -10 PAE (%)

S22 ACPR (dBc) -60 10 S-parameters (dB) -20 S11 -30 -70 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 5101520 Output power (dBm) Frequency (GHz) Fig. 6 Measured ACPR and PAE performance as a function of Fig. 4 Measured S-parameters by on-wafer probing. average output power with IS-95 CDMA input signal. 50 100 PAE results in high output load impedance and reduced knee 40 80 voltage effect, providing high efficiency for high output power. SOS CMOS technology, which has a relatively small 30 60 parasitic junction capacitance and no body effect, is used for the implementation of the stacked FET power amplifier. The fully integrated single-stage SOS MOS power amplifier 20 40 delivers a maximum output power of 21.0 dBm with the high efficiency of 44.0 % at 1.88 GHz. To the best of authors’ 10 20 Gain Drain current (mA) knowledge, this is the first reported fully integrated SOS Gain (dB) and (%) PAE power amplifier operating in the GHz range. 0 0 510152025 ACKNOWLEDGEMENT Ouput power (dBm) We thank Peregrine Semiconductor for the chip fabrication.

FigureFig. 2.19: 5 Measured Measured gain,gain, PAE PAE and and DC drainDC currentdrain ascurrent a function as a of function output power of withoutput single tonepower input with at 1.88 single GHz tone [12]. input at 1.88 GHz. REFERENCES [1] T. Sowlati, and D. M. W. Leenaerts, “ A 2.4-GHz 0.18-um CMOS Self- Biased Cascode Power Amplifier,” IEEE J. Solid-State Circuits, vol.38, The measured large signal gain and power added efficiency No82, pp.1318-1324, Aug. 2003. [2] N. Srirattana, P. Sen, H. -M. Park, C. -H. Lee, P. E. Allen, and J. Laskar, are shown in Fig. 5 with corresponding DC current as a “ Linear RF CMOS Power Amplifier with Improved Efficiency and function of output power at 1.88 GHz. The amplifier delivers Linearity in Wide Power Levels,” in IEEE RFIC symp., June 2005, 18.3 dBm output power at 1 dB gain compression point with pp.251-254. PAE of 29.2 %. The saturated power is 21.0 dBm with the [3] Y. Ding and R. Harjani, “ A High-Efficiency CMOS +22-dBM Linear Power Amplifier,” IEEE J. Solid-State Circuits, vol.40, No.9, pp.1895- maximum PAE of 44.0 %. This high efficiency is attributed to 1900, Sept. 2005. the high load impedance and the reduced knee voltage effect [4] I. Aoki, S. D. Kee, D. B. Rutledge, and A. Hajimiri, “ Fully Integrated of the stacked FET topology. Using an IS-95 CDMA signal, CMOS Power Amplifier Design Using the Distributed Active- Transformer Architecture,” IEEE J. Solid-State Circuits, vol.37, No.3, adjacent channel power ratios (ACPRs) were measured at 885 pp.371-383, Mar. 2002. KHz offset from the center frequency of 1.88 GHz and are [5] J. G. McRory, G. G. Rabjohn, and R. H. Jonhston, “ Transformer shown in Fig. 6 together with average PAE as a function of Coupled Stacked FET Power Amplifiers,” IEEE J. Solid-State Circuits, vol.34, No.2, pp.157-161, Feb. 1999. average output power. The difference between upper and [6] A. K. Ezzeddine and H. C. Huang, “ The High Voltage/High power lower side ACPRs is within 0.6 dB. The measured ACPR is FET,” 2003 IEEE RFIC Symp., 2003, pp. 215-218. below -42 dBc up to an average output power of 16.3 dBm [7] K. Tsui, K. J. Chen, S. Lam and M. Chan, “0.5 um Silicon-on-Sapphire and PAE of 18.7 %. Metal Oxide Semiconductor Field Effect Transistor for RF Power Amplifier Application,” Jan. J. Appl. Phys., p. 4982-4986, Vol.42, No.8, August, 2003. V. CONCLUSIONS In this paper, a fully integrated linear RF power amplifier is presented using a triple-stacked FET structure in the 0.25 µm SOS CMOS process. Instead of a parallel FET structure, the stacked FET topology utilizing capacitive voltage dividers 3 45

30 -30 40

20 S21 -40 30 10

0 -50 20

-10 PAE (%)

S22 ACPR (dBc) -60 10 S-parameters (dB) -20 S11 -30 -70 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 5101520 Output power (dBm) Frequency (GHz) Fig. 6 Measured ACPR and PAE performance as a function of Fig. 4 Measured S-parameters by on-wafer probing. Figure 2.20: Measured ACPR and PAE performance as a function of average output poweraverage with IS-95 output CDMA power input with signal IS-95 [12]. CDMA input signal. 50 100 PAE results in high output load impedance and reduced knee of 16.3 dBm and PAE of 18.7%. These characteristics of linearity and efficiency are in 40 80 voltage effect, providing high efficiency for high output excellentpower. agreement SOS withCMOS what wouldtechnology, be expected which for a class-A has a amplifier relatively operating small with parasitic junction capacitance and no body effect, is used for 30 60 a signal with 4.5-dB PAPR as appropriate for IS-95 CDMA. the implementation of the stacked FET power amplifier. The fully integrated single-stage SOS MOS power amplifier 20 40 2.8delivers Watt-Level a maximum Stacked-FET output power Linear of 21.0 PAdBm Design with the in high SOI efficiency of 44.0 % at 1.88 GHz. To the best of authors’ 10 20 CMOS Gain Drain current (mA) knowledge, this is the first reported fully integrated SOS Gain (dB) and (%) PAE power amplifier operating in the GHz range. 0 0 To further investigate the application of stacked-FET technology for handset ap- 510152025 plications, a design effort wasA undertakenCKNOWLEDGEMENT to show higher output power and higher effi- Ouput power (dBm) ciencyWe (at thank the possible Peregrine cost of linearity).Semiconductor A single-stage for the stacked-FET chip fabrication. deep class-AB PA

Fig. 5 Measured gain, PAE and DC drain current as a function of was designed to operate primarily at 1.9 GHz using 0.28-µm 2.5-V standard I/O FETs output power with single tone input at 1.88 GHz. REFERENCES [1] T. Sowlati, and D. M. W. Leenaerts, “ A 2.4-GHz 0.18-um CMOS Self- Biased Cascode Power Amplifier,” IEEE J. Solid-State Circuits, vol.38, The measured large signal gain and power added efficiency No82, pp.1318-1324, Aug. 2003. [2] N. Srirattana, P. Sen, H. -M. Park, C. -H. Lee, P. E. Allen, and J. Laskar, are shown in Fig. 5 with corresponding DC current as a “ Linear RF CMOS Power Amplifier with Improved Efficiency and function of output power at 1.88 GHz. The amplifier delivers Linearity in Wide Power Levels,” in IEEE RFIC symp., June 2005, 18.3 dBm output power at 1 dB gain compression point with pp.251-254. PAE of 29.2 %. The saturated power is 21.0 dBm with the [3] Y. Ding and R. Harjani, “ A High-Efficiency CMOS +22-dBM Linear Power Amplifier,” IEEE J. Solid-State Circuits, vol.40, No.9, pp.1895- maximum PAE of 44.0 %. This high efficiency is attributed to 1900, Sept. 2005. the high load impedance and the reduced knee voltage effect [4] I. Aoki, S. D. Kee, D. B. Rutledge, and A. Hajimiri, “ Fully Integrated of the stacked FET topology. Using an IS-95 CDMA signal, CMOS Power Amplifier Design Using the Distributed Active- Transformer Architecture,” IEEE J. Solid-State Circuits, vol.37, No.3, adjacent channel power ratios (ACPRs) were measured at 885 pp.371-383, Mar. 2002. KHz offset from the center frequency of 1.88 GHz and are [5] J. G. McRory, G. G. Rabjohn, and R. H. Jonhston, “ Transformer shown in Fig. 6 together with average PAE as a function of Coupled Stacked FET Power Amplifiers,” IEEE J. Solid-State Circuits, vol.34, No.2, pp.157-161, Feb. 1999. average output power. The difference between upper and [6] A. K. Ezzeddine and H. C. Huang, “ The High Voltage/High power lower side ACPRs is within 0.6 dB. The measured ACPR is FET,” 2003 IEEE RFIC Symp., 2003, pp. 215-218. below -42 dBc up to an average output power of 16.3 dBm [7] K. Tsui, K. J. Chen, S. Lam and M. Chan, “0.5 um Silicon-on-Sapphire and PAE of 18.7 %. Metal Oxide Semiconductor Field Effect Transistor for RF Power Amplifier Application,” Jan. J. Appl. Phys., p. 4982-4986, Vol.42, No.8, August, 2003. V. CONCLUSIONS In this paper, a fully integrated linear RF power amplifier is presented using a triple-stacked FET structure in the 0.25 µm SOS CMOS process. Instead of a parallel FET structure, the stacked FET topology utilizing capacitive voltage dividers 46

TL5 Cm3

VDD

TL4 Rb4 OUT TL3 VG4

C4 Rg4 TL6

Rb3 m4

VG3 Cm4

C3 Rg3 TL7 TL8 Rb2 m3

RF In VG2

Cm5

Rg2 Rf Rb1 m2 Cm1 RL C2 Cf

TL1

TL2 IN m1

Cm2 Rg1 GND = Bond pad VG1

Figure 2.21: Circuit schematic of the single-stage stacked-FET PA. 47 available in the STMicroelectronics 0.13-µm SOI CMOS process. The overall circuit diagram is shown in Fig. 2.21. Four transistors are stacked in series, based on the topology presented in the previous section. Each transistor has the total gate width of 5 mm, so the total device gate width in the ampliﬁer is 20 mm. To avoid the device breakdown, the drain-to-source voltage of each transistor should be limited to 4.5 V (Vds breakdown = − 5 V), allowing a maximum voltage swing of 18 V at the top drain node with a 9-V drain bias. For a higher margin of safety, the PA was designed to achieve linear ampliﬁcation up to the required output power under a 6.5-V supply.

The external gate capacitances (C2 - C4) are 9 pF, 2.6 pF, and 2 pF, respectively, setting the optimum load impedances seen by each transistor. For ﬂexibility, the gate bias voltages of each stacked device are implemented by an off-chip resistive voltage divider and applied through 1-kΩ on-chip resistors. The Rf -Cf feedback circuit is introduced to improve stability. The simulated Rollett stability factor K is greater than

1 for all frequencies between DC and 50 GHz except for the frequency band from 6.4

GHz to 7.6 GHz, where stability is ensured in the simulation ( Γ < 1 and Γ < 1) | in| | out| for the designed input and output matching conditions [28].

The optimum output load impedance (4Ropt in Fig. 2.10) is 11.5 Ω, which lies in a convenient range to match to 50 Ω over broad bandwidth with high efﬁciency. The input impedance is 17.5 Ω, a comparatively large value corresponding to that of a single

5-mm transistor. The input and output matching circuits are implemented off-chip in this work to allow opportunities for varying the tuning. A high-pass L-match section, consisted of a series capacitor (Cm4) and a short stub (TL7), was used to transform the external 50-Ω load to the optimum load. The on-board drain bias circuit included a quarter-wavelength microstrip line (TL4) with a 39-pF shunt capacitor (Cm3) to ground, 48

providing a short circuit at successive even harmonics.

To achieve the highest drain efficiency when the PA is driven into saturation, the drain current can be shaped like a half-sine wave and the drain-source voltage can be shaped like a square wave such that the voltage and the current waveforms do not overlap, minimizing power dissipation in the device. This waveform-shaping scheme can be accomplished ideally by properly terminating odd harmonics with an open circuit and terminating even harmonics with a short circuit. It has also been demonstrated in the literature that properly terminating only the first few harmonics is sufficient to achieve high drain efficiency [29–31]. However, the efficiency improvement is limited in practice by the topmost transistor’s drain-source capacitance (Cds) and the bond-wire inductance, which need to be absorbed properly, as well as the fact that each stacked transistor is presented with a different load impedance. Moreover, without proper harmonic termi- nations at the gate, the input signal is not purely sinusoidal due to the nonlinear Cgs [29].

2.8.1 Gate-Bias Setting

Special consideration is needed when setting the gate bias voltages of the stacked devices (VG2 - VG4) for a high-voltage design. The DC drain current is determined by the bottom device (m1) and increases with the RF power level due to the class-AB bias setting. Since the gate bias voltages are ﬁxed by the resistive voltage divider, the source bias voltages of the stacked devices must decrease to accommodate higher DC current, resulting in an early breakdown in the topmost device and an early compression in the bottom device as illustrated in Fig. 2.22(a). A simple solution is to offset the gate bias voltages of the stacked devices properly so that all four devices have equal voltage 49

0.9 1.0 V VGS-sat 0.9 GS-sat 0.8 m2 m2 0.8 0.7 m3 m3 0.7 0.6 m4 0.6 m4 0.5 0.5 m1 m1

0.4 0.4

DC Gate-to-SourceGate-to-SourceDC DC Voltage Voltage (V)(V) DC Gate-to-SourceDC Voltage (V) DC Gate-to-SourceDC Voltage (V) -10-5 0 5 10 15 20 -10-5 0 5 10 15 20 Input Power (dBm) Input Power (dBm)

2.8 2.8

2.6 2.6 (Early breakdown) m1 m4 2.4 m3 2.4 m3 2.2 m2 2.2 m2 2.0 m4 m1 2.0 1.8 (Early compression)

1.8 1.6

DC Drain-to-SourceDrain-to-SourceDC DC Voltage Voltage (V) (V)

DC Drain-to-SourceDrain-to-SourceDC DC Voltage Voltage (V)(V) -10-5 0 5 10 15 20 -10-5 0 5 10 15 20 Input Power (dBm) Input Power (dBm)

(a) (b)

Figure 2.22: Simulated DC gate-to-source voltage and DC drain-to-source voltage of each FET as a function of input power: (a) without gate-bias offsets, and (b) with proper gate-bias offsets. 50

20 20

15 15 Vd4 V 10 d4 10 Vd3 Vd3 Vd2 5 Vd2 5 V

Vd1 d1

Drain Voltage (V) (V) Voltage Voltage DrainDrain Drain Voltage (V) Voltage Drain 0 (V) Voltage Drain 0 0.00.4 0.8 1.2 0.00.4 0.8 1.2 Time (nsec) Time (nsec)

15 15 10 10 Vg4 Vg4 Vg3 5 Vg3 5 V Vg2 0 g2 0

Vg1 Vg1

Gate Voltage (V) (V) GateGate Voltage Voltage Gate Voltage (V) Gate Voltage Gate Voltage (V) Gate Voltage -5 -5 0.00.4 0.8 1.2 0.00.4 0.8 1.2 Time (nsec) Time (nsec)

6 6 4 4 Vds Vds 2 2

0 0

Voltage (V)(V) Voltage Voltage

Voltage (V) (V) Voltage Voltage Vdg Vdg -2 -2 0.00.4 0.8 1.2 0.00.4 0.8 1.2 Time (nsec) Time (nsec)

1.5 1.5 m1 m1 1.0 m2 1.0 m2 m3 m3

0.5 m4 0.5 m4

Drain Current (A) (A) Drain Drain Current Current Drain Current (A) Drain Current Drain Current (A) Drain Current 0.0 0.0 01 2 3 4 5 01 2 3 4 5 Drain-to-Source Voltage (V) Drain-to-Source Voltage (V)

(a) (b)

Figure 2.23: Simulated drain, gate, drain-to-source, drain-to-gate voltage waveforms and dynamic load lines of each FET at the saturated output power: (a) VDD = 6.5 V, and (b) VDD = 9 V. 51 headroom close to the saturation point as shown in Fig. 2.22(b), thereby improving operation. For an n-stacked PA, the gate bias voltage of the i-th stacked device should be set as:

i 1 VGi = ( − )VDD + VGSi sat i = 2, 3, ..., n (2.19) n − where VGSi sat is the DC gate-to-source voltage of the i-th stacked device at the saturat- − ing power. Fig. 2.23(a) and Fig. 2.23(b) show the simulated drain, gate, drain-to-source, drain-to-gate voltage waveforms and dynamic load lines of each FET at the saturating output power under 6.5-V and 9-V supply voltages, respectively, illustrating that Vgs and

Vds swings for the different devices are close to one another and within the breakdown limit.

Note that the gate bias voltage of the bottom device is not a part of the resistive voltage divider and can be adjusted separately to improve gain ﬂatness for better linearity. A deep class-AB PA can exhibit good linearity over a wide dynamic range with a ”sweet-spot” gate bias voltage [31], where gain compression of AM-AM conversion due to decreasing conduction angle is properly compensated by gain expansion due to increasing drain bias current.

2.8.2 Fully-Integrated Design Possibility

One of the main advantages in using the stack-FET technique is the much lower impedance transformation ratio relative to the conventional approach, which makes a low-loss on-chip matching network possible. As an example, if the output matching is done on-chip with an on-chip inductor (Qind = 12), the drain efﬁciency factor due to matching network loss can be estimated as: 52

r r Rp 50 Qm = 1 = 1 = 1.83 (2.20) Rs − 11.5 −

Qind ηm = 86.8% (2.21) Qind + Qm ≈ The on-chip output matching network for a conventional common-source design delivering the same output power level without device stacking (Qm = 8.28) would yield a drain efﬁciency factor of only 59.2%. The stacked-FET conﬁguration is clearly an attractive technique for realizing a fully-integrated PA in the absence of low-loss passive components.

2.8.3 Layout Approach

The partial layout diagram of unit cells and interconnects is depicted in Fig. 2.24.

One metal layer is dedicated as a ground plane to minimize on-chip ground inductance.

A unit cell is composed of four gate ﬁngers with a shared silicon active area, thus effec- tively producing four stacked FETs. Each ﬁnger has its body directly tied to its source.

In this way, the body terminals float in phase with the respective sources, thus avoiding the drain-bulk breakdown as well. The drain of the top finger is then connected to one of the large drain lines, which flow from the input side to the output side of the chip in parallel with the gate distribution lines. On the other hand, the source of the bottom finger is connected directly to the ground plane through multiple vias. This distributed layout approach results in a highly compact layout with improved on-chip heat distribution and minimized parasitic components within the structure.

A microphotograph of the fabricated PA is shown in Fig. 2.25, occupying an area 53

Body-Source GND Plane G4 G3 G2 G1 connection Top Drain

G1 . . . G4

Top Drain Unit cell

G1 . . . G4

Top Drain

Figure 2.24: Layout diagram of stacked-FET unit cells and interconnects.

GND In GND In GND In GND In GND

VG2 Gate capacitors VG3

Distributed stacked-FET unit cells VG4 GND

GND Out GND Out GND Out GND Out GND

Figure 2.25: Microphotograph of the fabricated stacked-FET PA. 54

of 0.43 mm x 1.56 mm, including bond pads. The chip is made narrow to minimize drain line inductance and resistance, as well as to minimize the phase difference between the unit ampliﬁer cells closer to the input side and the ones closer to the output side.

For thermal resistance estimation, it can be assumed for simplicity that the power ampliﬁer is a single stripe heat source since device ﬁngers are distributed evenly within an area of 0.172 mm x 1.175 mm and that heat spreads at 45o into the substrate. The silicon substrate thickness is 350 µm while the buried oxide thickness is 0.4 µm, equivalent to approximately 40 µm of silicon substrate in term of thermal resistance. The overall thermal resistance can be calculated as

1 1 W + 2h L R = ln( ) (2.22) th 2κ · L W · L + 2h · W th − where W and L are the width and length of the stripe heat source, h is the substrate thickness, and κth is the thermal conductivity of the substrate. For a power ampliﬁer delivering 1-W output power with a 50% drain efﬁciency, the temperature rise relative to the ambient temperature is approximately 4o.

2.9 Measurement Results

For improved heat ﬂow and reduced bond-wire inductance, the test chip was thinned down to approximately 150 µm of substrate thickness. It was then mounted on a coplanar waveguide PCB with substrate relative dielectric constant of 3.38. Eleven bond pads were used for wire-bonding to the PCB ground. The PCB board was then attached on top of an aluminum block for heat sink as shown in Fig. 2.26. All measurements are 55

Figure 2.26: A stacked-FET PA test board.

50 35 45 Gain 30 40 PAE 35 Output power 25 30 20 25 20 15 15 10 10

5 Outputpower (dBm)

Gainand(dB) PAE (%) 5 0 0 -15 -10 -5 0 5 10 15 20 25 Input power (dBm)

Figure 2.27: Measured gain, PAE, and output power as a function of input power with a CW input at 1.9 GHz. 56

50 0.6 45 Mea. Gain 40 Sim. Gain 0.5 Mea. PAE 35 Sim. PAE 0.4 30 Mea. DC Current 25 Sim. DC Current 0.3 20

15 0.2 DC Current (A) Current DC 10 0.1

Gain (dB) and PAE (%) PAE (dB) and Gain 5 0 0 0 5 10 15 20 25 30 35 Output power (dBm)

Figure 2.28: Measured and simulated gain, PAE, and DC current as a function of output power with a CW input at 1.9 GHz. 57

referred to the PCB connectors.

2.9.1 CW Measurements

The PA was tested under a CW input at 1.9 GHz and a supply voltage of 6.5 V.

The input bias voltage was 0.42 V, resulting in a bias quiescent current of 54 mA, chosen for the best AM-AM characteristic. The measurement results are illustrated in Fig. 2.27 and Fig. 2.28 in line with the simulated results. The measured small-signal gain is 14.6 dB, with a fairly ﬂat gain roll-off. At the 1-dB compression point, the output power is

30.8 dBm with a 46.1% PAE. A maximum PAE as high as 47% is achieved at a 31.6- dBm output power, whereas the saturated output power reaches 32.4 dBm. High power efﬁciency (PAE > 40%) is also maintained over a wide range of supply voltages (4.5 V

- 9 V) with constant load impedance as shown in Fig. 2.29. To test its robustness under a high supply voltage as designed, the PA was continuously operated at the peak output power, under a 9-V supply. No performance degradation was observed after 1 week.

Fig. 2.30 shows that, with a ﬁxed matching circuitry, the saturated output power is maintained above 31 dBm and the drain efﬁciency is above 40% for the entire DCS,

PCS, and UMTS frequency bands. In addition, the PA was tested in the low frequency band at 900 MHz with a reconﬁgured matching circuitry. As illustrated in Fig. 2.31, a small-signal gain of 19.3 dB is achieved with a saturated output power of 29.5 dBm and a maximum PAE of 53%. 58

50 45 VDD = 9.0 V 40 VDD = 7.5 V 35 VDD = 6.5 V 30 VDD = 5.5 V VDD = 4.5 V 25 VDD = 3.5 V

20 PAE(%) 15 10 5 0 0 5 10 15 20 25 30 35 40 Output power (dBm)

Figure 2.29: Measured PAE as a function of output power with supply voltage variation at 1.9 GHz. 59

60 35

50 30 25 40 20 30 15 20 10 10 DCS PCS UMTS

Drainefficiency (%) 5 Outputpower (dBm) 0 0 1.65 1.7 1.75 1.8 1.85 1.9 1.95 2 2.05 Frequency (GHz)

Figure 2.30: Measured drain efﬁciency and output power at saturation as a function of frequency. 60

60 0.3 Gain (dB) 50 PAE (%) 0.25 DC Current (A) 40 0.2

30 0.15

20 0.1 DCCurrent(A)

10 0.05 Gainand(dB) PAE (%) 0 0 5 10 15 20 25 30 35 Output power (dBm)

Figure 2.31: Measured gain, PAE, and DC current as a function of output power with a CW input at 900 MHz. 61

2.9.2 IS-95 Measurements

The power ampliﬁer was tested for performance with CDMA and WCDMA signals as appropriate for handset applications. Fig. 2.32 shows the measured adjacent channel power ratio (ACPR), alternate channel power ratio (ACPR2) and PAE performance of the PA as a function of average output power using a reverse-link IS-95 CDMA signal at 1.9 GHz. The ACPR and ACPR2 were measured at 885-KHz and 1.98-MHz offsets, respectively, from the center frequency. The modulated input signal has a chip rate of 1.2288 Mc/s and a peak-average power ratio (PAPR) of 4.5 dB. The measured

ACPR is below the -42-dBc requirement up to an average output power of 28.7 dBm and a PAE of 41.2%. The measured output spectra at Pout = 28.7 dBm is shown in Fig. 2.33 where the PAPR is reduced to 3 dB and the ACPR2 is below -58 dBc, meeting the -54- dBc requirement. These results are competitive with current handset power ampliﬁers available commercially based on GaAs HBT technology.

2.9.3 WCDMA Measurements

Fig. 2.34 shows the measured adjacent channel leakage ratios (ACLRs) and PAE performance of the PA as a function of average output power using an uplink WCDMA signal at 1.9 GHz. The ACLRs were measured at 5-MHz and 10-MHz offsets from the center frequency. The modulated input signal has a chip rate of 3.84 Mc/s and a PAPR of 2.58 dB. The measured ACLR at 5-MHz offset is below the -33-dBc requirement up to an average output power of 29.4 dBm and a PAE of 41.4%. The measured output spectra at Pout = 29.4 dBm is shown in Fig. 2.35 where the PAPR is reduced to 2.08 dB 62

0 50 Upper ACPR -10 45 Lower ACPR 40 -20 Upper ACPR2 35 Lower ACPR2 -30 30 PAE -40 25 -50 -42 dBc 20 15 (%)PAE ACPR(dBc) -60 -54 dBc 10 -70 5 -80 0 5 10 15 20 25 30 35 Average Output power (dBm)

Figure 2.32: Measured ACPR and PAE performance as a function of average output power using a reverse-link IS-95 CDMA input signal at 1.9 GHz. 63

Pout = 28.7 dBm

PAPR = 3 dB

Figure 2.33: Measured IS-95 CDMA output spectra at Pout = 28.7 dBm. 64

0 50 Upper ACLR 5-MHz offset -10 Lower ACLR 5-MHz offset 45 Upper ACLR 10-MHz offset 40 -20 Lower ACLR 10-MHz offset PAE 35 -30 30 -33 dBc -40 25 -43 dBc -50 20 15 (%)PAE ACLR(dBc) -60 10 -70 5 -80 0 5 10 15 20 25 30 35 Average Output power (dBm)

Figure 2.34: Measured ACLRs and PAE performance as a function of average output power using an uplink WCDMA input signal at 1.9 GHz. 65

and the ACLR at 10-MHz offset is below -52 dBc, meeting the -43-dBc requirement.

Figure 2.35: Measured WCDMA output spectra and ACLRs at Pout = 29.4 dBm.

Table 2.2 compares the performance of recently reported WCDMA power ampli-

ﬁers for handsets. The implemented CMOS PA clearly exhibits efﬁciency and linearity performance comparable to those of GaAs-based PAs.

2.10 Summary

A single-stage stacked-FET linear PA has been demonstrated in SOI CMOS providing Watt-level output power in the GHz frequency range using 0.28-µm 2.5-V standard I/O FETs available in a 0.13-µm SOI CMOS technology. To solve the low breakdown voltage problem, the stacked-FET technique is employed to allow the use of higher supply voltage, resulting in a much lower impedance transformation ratio. The implemented SOI CMOS PA achieves 47% maximum PAE and delivers 32.4-dBm saturated output power at 1.9 GHz with a 6.5-V supply. Using a reverse-link IS-95 CDMA 66 AB AB AB AB AB 3-stage 2-stage Doherty Single-stage Linearized AB Operating class 1.9 1.95 1.95 1.95 1.95 1.95 1.75 Freq. (GHz) 3 DD 3.5 3.4 3.3 6.5 (V) N/A N/A V out P ACLR @ -36 dBc @ 26 dBm -37 dBc @ 27 dBm -38 dBc @ 28 dBm -35 dBc @ 24 dBm -38 dBc @ 28.6 dBm -33 dBc @ 23.9 dBm -33 dBc @ 29.4 dBm -38 dBc @ 28.5 dBm 9 . 30 8.5 5.3 N/A 23 22.6 14.6 (dB) Gain > 27% 29% PAE 38% 46% 31% 44.5% 41.4% 38.7% > 24 out 24 27 28 P 29.7 23.9 29.4 28.5 > (dBm) m m µ µ FET HBT HBT SiGe HBT HBT GaAs CMOS 0.5 0.13 SOI CMOS Technology InGaP/GaAs InGaP/GaAs AlGaAs/GaAs Table 2.2: Performance comparison of recently reported WCDMA handset power amplifiers [ 32 ] [ 33 ] [ 34 ] [ 35 ] [ 36 ] [ 37 ] Ref. Jager 02 Deng 05 Wang 04 Zhang 09 This work Vintola 01 Srirattana 03 67 modulated signal, the PA shows an average output power of up to 28.7 dBm with a PAE of 41.2% while meeting the ACPR requirement. Using an uplink WCDMA modulated signal, the PA shows an average output power of up to 29.4 dBm with a PAE of 41.4% while meeting the ACLR requirement. A fully-integrated single-stage stacked-FET PA has also been demonstrated in SOS CMOS as a prototype, delivering a maximum output power of 21.0 dBm with the high efficiency of 44.0% at 1.88 GHz. The stacked-FET technique is clearly an attractive solution for designing high-efficiency linear PAs in advanced deep-submicron CMOS technology where the breakdown limit is much lower than the standard supply voltage.

2.11 Acknowledgements

Part of the material in chapter2 is as it appears in ”A 33-dBm 1.9-GHz silicon- on-insulator CMOS stacked-FET power ampliﬁer,” S. Pornpromlikit, J. Jeong, C. D.

Presti, A. Scuderi, and P. M. Asbeck, in IEEE MTT-S Int. Microwave Symp. Dig., pp.

533-536, Jun. 2009, and ”A watt-level stacked-FET linear power ampliﬁer in silicon- on-insulator CMOS,” S. Pornpromlikit, J. Jeong, C. D. Presti, A. Scuderi, and P. M.

Asbeck, in IEEE Trans. Microw. Theory Tech., vol. 58, no. 1, pp. 57-64, Jan. 2010.

The contributions from the co-authors are appreciated. The author of this dissertation was the primary investigator and primary author for these publications. Chapter 3

Digitally-Modulated Power Ampliﬁers for Multi-Standard Polar Transmitters

3.1 Introduction

With the continuing development of next-generation wireless communication systems, there has been a great interest in multi-standard transmitters (TXs), which would facilitate a smooth adoption of new standards as well as provide the possibility for global roaming in a single mobile device. To reduce the cost and the system complexity, multi-mode multi-band building blocks that can handle various standards without redundant hardware are attractive. Current high-end smart phones incorporate up to 5 distinct power amplifiers to address the requirements for different communication bands and standards. The ideal solution is to have the whole system, from the digital baseband circuitry to the RF frontends, integrated onto a single CMOS chip. However, the design of a truly multi-standard CMOS TX is highly challenging, especially the integration of a multi-mode multi-band power amplifier since the PA needs to meet the stringent performance requirements of all integrated standards as well as provide highest-efficiency

68 69 operation over a wide bandwidth.

Recently, several possible solutions for CMOS multi-mode RF TX systems were reported [2,3,38,39]. The implementations in [2,3,39], however, provide low peak output power and would require one external PA with a large power gain for each frequency band. Moreover, the external PA is usually implemented by employing a conventional linear PA (class-A, AB) with a large power back-off to meet the stringent linearity requirements, resulting in much lower average power efﬁciency.

Power amplifiers with a polar architecture provide advantages for linear amplification without severely compromising power efficiency. The signal is decomposed into a constant-envelope phase-modulated RF signal and an envelope baseband component, allowing the use of a high-efficiency nonlinear PA to amplify the RF phase signal, while the envelope portion is restored at the output. For greatest flexibility, the envelope signal can be delivered to the PA as a digital signal. This approach is especially promising in the highly-integrated CMOS technology where signal generation and linearity improvement can be achieved through the use of digital signal processing as successfully demonstrated in several papers [2,4, 39].

This work aims to develop a high-efﬁciency digitally-modulated power ampliﬁer

(DPA) in a 0.13-µm 1.2-V SOI CMOS technology. The DPA is to be used as the main building block in a proposed multi-standard CMOS RF polar transmitter described in the next section.

3.2 Direct-Digital Multi-standard Polar Transmitter

The concept of polar modulation can be traced back to the Envelope Elimination and Restoration (EER) technique proposed by Kahn in 1952 [40]. In Kahn’s EER trans- 70

mitter, the power amplifier is a separate circuit block from the baseband circuitry and the upconversion mixers. The RF input signal, containing both envelope amplitude and phase modulation, is split into a constant-envelope phase signal and a low-frequency envelope signal by a limiter and an envelope detector, respectively. Both signals are then recombined in the last stage of a high-efficiency nonlinear power amplifier. In a fully integrated transmitter, however, the digital signal processing block can produce the amplitude and phase signals separately. After the recombination, the RF output waveform can be generally expressed in a polar representation as

v (t) = Re A(t)e(jϕ(t)+jωc(t)) = A(t)cos(ω (t) + ϕ(t)) (3.1) OUT { } c where ωc is the carrier angular frequency.

The envelope signal can be restored conventionally by an amplitude modulator, which modulates the supply voltage according to the envelope signal. Since the envelope signal has a much broader bandwidth than the RF signal, the amplitude modulator is required to have a broad enough bandwidth to avoid distorting the signal. The efﬁciency-bandwidth tradeoff and linearity of the amplitude modulator will directly affect the overall performance of the transmitter. In this work, we explore an alternative approach that directly uses the digital envelope signal to modulate the amplitude of the

RF output without the need for digital-analog conversion and a separate amplitude modulator.

A possible block diagram of the direct-digital polar-based transmitter architecture is depicted in Fig. 3.1. The baseband I and Q signals are up-sampled and then converted into polar amplitude and phase signals in digital domain. The phase information ϕ(t) is used to produce a phase-modulated RF input signal for the DPA. Phase 71

LPF ACW(t) I xN VCO

Phase RFOUT Q xN Modulator DPA Rect. To Polar φ(t) + PLL LPF TX. Power Control

Figure 3.1: Direct-digital polar transmitter architecture.

modulation can be done digitally by an all-digital phase-locked loop (PLL) as proposed in [2]. The envelope signal is provided to the DPA as a 10-bit digital amplitude control word (ACW).

Fig. 3.2 shows the block diagram of the proposed DPA system. The building block integrated in the DPA silicon chip is inside the dotted line. The 7 most significant bits are decoded into a thermometer code and used to control the activation of 127 unit- weighted amplifiers, which are connected in parallel. The amplifiers’ output currents are then combined at the drain to form the final RF output. The use of the binary- to-thermometer decoder helps avoid non-monotonic operation due to device mismatch.

The 3 least signiﬁcant bits of the ACW are used to control 3 binary-weighted ampli-

fiers to provide extra resolution. The DPA is designed for multi-mode multi-band functionality by avoiding frequency-selective components, except for the final-stage output matching network, which can be implemented in future research as an on-chip tunable circuit to provide highest power-efficiency for various frequency bands.

The choice of using SOI CMOS technology has several advantages over the standard bulk CMOS. The ﬁrst is the availability of high-performance RF power switches. 72

Amplitude 10 7 Binary-to-Thermometer Control Decoder Word (ACW) 3 127

Variable Supply & 1x Input Attenuator Controls Transmit Power Control (TPC) 1x

Stage Bypass 1x Phase-Modulated Reconfigurable RF Signal Output Unit Cells Matching Attenuator Network

1/2

1/4 High-Power 1/8 Gain Stage Binary Cells

DPA Silicon Chip

Figure 3.2: Block diagram of the proposed multi-standard DPA. 73

The high-resistivity substrate of the SOI CMOS also results in lower substrate coupling and lower-loss on-chip passive components. By arranging the RF switches as shown in Fig. 3.2, the DPA can be used to directly drive the antenna up to its full power (25- dBm peak output power) while an extra power ampliﬁer is switched in only when the higher power is required, resulting in much improved average efﬁciency. An example of a stage-bypass power switch has been reported in [41] on the same SOI CMOS technology, managing up to a 35-dBm input power with less than 0.35-dB insertion loss from

500 MHz through 3 GHz with high linearity.

3.3 System-Level Requirements

3.3.1 Amplitude Resolution and Sampling Frequency

As an envelope amplitude signal is generated in the digital domain, the number of bits used to represent the signal determines the minimum possible white noise ﬂoor caused by the quantization error of the signal. Theoretically, the quantization noise improves by 6.02 dB for an additional bit of resolution. In order to meet the ACLR,

EVM, and emission mask speciﬁcations for both GSM/EDGE and WCDMA with a reasonable margin, system simulations based on an idealized polar transmitter indicate that at least 7-bit resolution is required for amplitude modulation [3, 38]. In this work, the extra 3 least signiﬁcant bits are also introduced to compensate for the decrease in effective resolution due to the nonlinearity of the amplitude modulation scheme. In [38], simulations were done with a WCDMA signal sampled at 38.4 MHz and an EDGE signal sampled at 26 MHz.

The noise performance can be improved by further increasing the oversampling 74

ratio. The total quantization noise power is spread over a wider frequency range, resulting in a lower noise ﬂoor within the nyquist zone, and as the replicas of the digital signal are generated at offset frequency multiples of the sampling frequency fCLK , the

ﬁltering effect of the zero-order hold on those digital images is deﬁned as

sin(π f ) H(f) = 20 log( · fCLK ) (3.2) · π f · fCLK where f is the offset frequency from the carrier.

Fig. 3.3 shows the MATLAB-simulated output spectrum of a WCDMA signal with its envelope component quantized at different resolutions. A 5-bit resolution and a sampling rate of 122 MHz are required to meet the ACLR speciﬁcations for WCDMA.

Similarly, as shown in Fig. 3.4, an 8-bit resolution and a sampling rate of 125 MHz are required to meet the spectral mask requirement for the EDGE-modulated signal.

The receive-band noise performance is another stringent requirement as the transmitter noise contributes to the sensitivity of the receiver. With 50-dB duplexer attenuation, a receive-band noise level of below -150 dBc/Hz is generally allowed for a practical WCDMA receiver sensitivity performance. To meet this requirement, envelope and phase ﬁltering could be used to remove out-of-band spectral images and quantization noise as shown in Fig. 3.5.

3.3.2 AM/PM Time Alignment

Another critical issue for polar transmitter is the time alignment between amplitude and phase signals. As the two signals follow different paths before recombining at the output, slight time misalignments are often encountered. Such a misalignment will 75

-30

-40 PAPR: 5.4 dB # Bits 4 -50 RFBW: 3.84 MHz 5 8 6 9 Fs = 122 Msample/s -60 7 10

-70

-80

-90 Power/frequency (dBm/Hz)

-100 1.9 1.91 1.92 1.93 1.94 1.95 1.96 1.97 1.98 1.99 2 Frequency (GHz)

Amplitude Control Word ZOH 122 MHz

Ideal Phase (6.3 Gs/S) X Out

Figure 3.3: A WCDMA signal with the envelope component quantized at different resolutions. 76

-20

-40 PAPR: 3.2 dB # Bits RFBW: 2 MHz 6 -60 8 12 Fs = 125 Msample/s 10 14 -80

-100

-120 Power/frequency (dBm/Hz) -140 1.935 1.94 1.945 1.95 1.955 1.96 1.965 Frequency (GHz)

Amplitude Control Word ZOH 125 MHz

Ideal Phase (6.3 Gs/S) X Out

Figure 3.4: An EDGE signal with the envelope component quantized at different resolutions. result in the appearance of a scaled replica of the wide PM spectrum on both sides of the original signal spectrum, corrupting adjacent channels in the process. For a two- tone signal, the effect of AM/PM misalignment can be theoretically predicted and the third-order intermodulation distortion (IMD3) can be estimated as

2 2 IMD3 = (τ BW ) (3.3) π · RF where τ is the time mismatch between the amplitude and phase paths and BWRF is the bandwidth of the RF signal [38, 42, 43]. In a highly-integrated transmitter, the AM/PM time misalignment is predictable and can be compensated in the digital domain. 77

-40

-60

-80

-100

-120 Envelope Filter -140 50 MHz LPF

Power/frequency (dB/Hz) 100 MHz LPF -160 150 MHz LPF -180 1.9 1.95 2 2.05 2.1 2.15 2.2 Frequency (GHz)

Amplitude Control Word (8 Bits) ZOH 122 MHz LPF 3 Ideal Phase (6.3 Gs/S) 100 MHz LPF X Out

Figure 3.5: Effect of envelope and phase ﬁltering on receive-band noise of a WCDMA signal reconstruction. 78

3.3.3 Transmit Power Control Requirement

Modern wireless communication standards also require a large transmit power control (TPC) range (70-80 dB for WCDMA and 30 dB for GSM/EDGE) while maintaining a sufﬁcient signal quality. In this work, a transmit power control strategy is proposed as illustrated by Fig. 3.6, where the output power as a function of amplitude control word (ACW) is plotted in simulations at different power control settings.

The transmit power control will be achieved by three main components: power supply voltage variation, input attenuator, and output attenuator. Moreover, the amplitude resolution can be reduced to obtain an extra power control range. In fact, power control through amplitude resolution reduction is more power-efﬁcient and preferred over the use of attenuators wherever amplitude resolution is more than strictly needed for modulation as all unused unit ampliﬁers will be deactivated.

3.4 DPA Circuit Implementation

The simplified schematic of the DPA is illustrated in Fig. 3.7. Only one of the unit amplifiers is shown in detail. The 127 unit amplifiers and the 3 binary-weighted amplifiers are laid out in a rectangular array and connected in parallel by tree-structure input and output interconnects to minimize the phase mismatch. The driver stage of the unit amplifier is composed of a chain of digital inverters (M2 M3, M9 M14) and − − an input attenuator (R1, C1, M15 M16), which can be used to reduce the input swing − at the final stage through capacitive dividing, thus increasing the overall transmit power control range. Each unit amplifier’s activation is controlled by an enable signal (EN), which is decoded from the 10-bit ACW and synchronized through a register. A digital 79

Input Attenuator OFF Supply Voltage Sweep Output Attenuator OFF

30 20 10 0 -10 -20 -30 -40 -50 -60

Pload_dBm -70

Pout [dBm] Pout -80 -90 -100 -110 -120 0.0 0.5 1.0 1.5 2.0 2.5 loglog10(NT) [ACW]

Input Attenuator ON Supply Voltage Sweep Output Attenuator OFF

30 20 10 0 -10 -20 -30 -40 -50 -60

Pload_dBm -70

Pout [dBm] Pout -80 -90 -100 -110 -120 0.0 0.5 1.0 1.5 2.0 2.5 loglog10(NT) [ACW]

Input Attenuator ON Minimum Supply Voltage Output Attenuator Sweep

30 20 10 0 -10 -20 -30 -40 -50 -60

Pload_dBm -70

Pout [dBm] Pout -80 -90 -100 -110 -120 0.0 0.5 1.0 1.5 2.0 2.5 loglog10(NT) [ACW]

Figure 3.6: Proposed Transmit Power Control Strategy. 80

AND gate (M4 M7) is inserted at the input side of the driver stage. In this way, when − the unit ampliﬁer is deactivated, no switching power is consumed. In addition, when

EN is low, transistors M8 and M17 are turned on to further ensure that the ﬁnal power switch M1 is off and all intermediate nodes are in deﬁned states.

Fig. 3.8 shows the circuit diagram of the implemented 10-bit decoder. All 10 bits are ﬁrst synchronized at the input and the 7 most signiﬁcant bits (MSBs) are fed to the

7-bit binary-to-thermometer decoder while the 3 least signiﬁcant bits (LSBs) are kept undecoded to control the 3 binary ampliﬁer cells. The 3 undecoded bits are fed through synchronized delay lines that match the delay of the binary-to-thermometer decoder.

The 7-bit binary-to-thermometer decoder is designed as a row-column matrix decoder [44–46]. The decoding logic consists of two steps. First, the digital input bits are split into two groups and decoded into thermometer-coded signals by a 4-bit row decoder and a 3-bit column decoder. The logic circuit in each matrix cell then determines whether to activate the corresponding unit ampliﬁer based on the row and column positions.

Thermometer code has several advantages over binary-weighted code. When the digital input increases by 1 LSB, only one more unit amplifier is activated. Conse- quently, the RF output is always increasing as the digital input increases, guaranteeing monotonicity. Moreover, the glitch problem is also much improved. For example, the code transition from ’0111111’ to ’1000000’ causes only one more unit amplifier to switch ON in a thermometer-coded system while in a binary-coded system, all unit amplifiers will be switched.

All transistors are 0.13-µm 1.2-V FETs, except for the ﬁnal power switch, which 81 … … … VDD1 Att1 . M4 . . . . R1 EN . . . . RF M5 M6 M8 M9 M11 M13 OUT M2 M15 PM ...... M1 Signal M3 M7 . C1 . M10 . M12.M14 . .M16 .M17 . 50 Ω Att2 … … … EN to unit and binary cells Vdec 127 3 Vdec

Binary-to-Thermometer Q Decoder D CLK 7 3 CLK ACW DPA Silicon Chip

Figure 3.7: Simpliﬁed DPA schematic.

is a 0.28-µm 2.5-V standard I/O FET. The supply voltage (VDD1) for the driver stage is

1.2 V, while the ﬁnal-stage drain bias (VDD2) is varied between 0.5 V and 2.1 V to provide average transmit power control. A 50-Ω termination is placed after the input pad to have deﬁned input impedance and driving power. The input is DC-biased at

0.6 V and an RF input power of at least 5.5 dBm is needed to create a 1.2-V full-swing input signal. In a fully-integrated transmitter system, however, the DPA would be driven directly by the phase-modulated RF output of the PLL.

The amplitude-modulation mechanism of the DPA can be explained by looking at the load line of a unit device (ﬁnal-stage switch). When activated, the unit device is hard-switched as its input swings between VDD1 and ground, and its load line tracks the device I-V curve (VGS = VDD1 = 1.2 V) as illustrated by the simulation in Fig. 3.9.

To simplify the analysis, an idealized device model is assumed. When only 82

Q Q Q Column Decoder 5 4 3

3-Bit Decoder MSB B1 B0

t1 t2 t3 t4 t5 t6 t7 Vdec

C1 C2 C3 C4 C5 C6 C7 C8 Vdec

t1 R2 Q6 B0

t2 R3 Q7 B1

t3 R4 Q8 B2

t4 R5 Q9 MSB

t5 R6 EN1 ... t R 6 7 EN127

t7 R8

t8 R9

t9 R10

t10 R11

t11 R12

t12 R13 Col

t13 R14

Row DQ

t14 R15 Next Row clk

t15 R16 clk Row Decoder Row Negated 4-Bit Decoder

Decoding Matrix

B0...B9 Q0...Q9 Clock Q0...Q2 DQ CLK DQDelay EN1/2 Distribution Input EN1/4 Reg.s EN1/8 Buffered Synchr. Delay Block

Figure 3.8: A binary-to-thermometer decoder schematic. 83

VGS = 1.2 V ACW = 8 ACW = 208 (n = 1) VGS = 1.1 V (n = 26) VGS = 1.0 V

VGS = 0.9 V

VGS = 0.8 V

VGS = 0.7 V

VGS = 0.6 V

ACW = 1016 (n = 127)

Figure 3.9: Simulated dynamic load line of an activated unit device with increasing ACW at 1.9 GHz.

ID Triode region Active region Rn = n·RL ID,max

ID ID ID RL

VDS Vk VDD2 n

Figure 3.10: Load-pull effect on an activated unit-device load line. 84

one unit device is activated, the device sees a load resistance RL and supplies a peak current ID,max. As the number of activated unit ampliﬁers (n) increases, however, each unit device sees a larger load resistance of n R due to the active load-pull effect · L and the device load line is rotated accordingly as shown in Fig. 3.10. The DPA can be described as operating in two separate regions depending on the number of activated unit devices. When n is small, each unit device operates entirely in its active region and acts as a constant current source. Consequently, the total RF output current is linearly proportional to n. The output power and efﬁciency can be derived as

1 P = (I2 R ) n2 (3.4) out 8 · D,max L ·

2 Pout 1 ID,maxRL p = ( ) n Pout (3.5) PDC 8 · VDD2IDC,unit · ∝ In the actual devices, however, other device effects such as channel-length modulation introduce AM distortion. When n is large, the unit device will eventually enter its triode region (VDS,min < Vk) and the RF current supplied by each device diminishes with the increasing n. As a result, the total output power delivered to the load saturates.

3.5 Layout

A die micrograph of the PA is shown in Fig. 3.11. The chip was fabricated in a

0.13-µm SOI CMOS technology. The total die area is 1.12 x 1.2 mm2, including pads.

A unit ampliﬁer layout is shown in Fig. 3.12, where the driver, the input attenuator and the power devices are highlighted. The phase-modulated RF input signal is distributed to all unit ampliﬁers in a tree structure as illustrated in Fig. 3.13 to minimize the phase 85

VDD1 ACW Bit 5-9 Att.

Decoder GND GND

IN DPA core OUT GND GND

Decoder

ESD ACW Bit 0-4 clk Vdec VDD1

Figure 3.11: DPA chip micrograph. 86

difference between the unit ampliﬁer cells. Similarly, the RF output lines are combined as shown in Fig. 3.14 using the 2 topmost metal layers.

Driver

Power Device

Input Attenuator

Figure 3.12: Layout of a unit ampliﬁer.

3.6 Experimental results

The chip was mounted directly on a printed circuit board with off-chip output matching components, designed such that the DPA operation approaches a high- efﬁciency class-E mode. A photograph of the measured DPA board is depicted in

Fig. 3.15. The DPA is also designed to operate reliably according to a recent study on

FET degradation under RF stress in CMOS PAs [47]. In this case, the peak drain-source voltage is limited to 5 V in the simulation. 87

Unit Amplifier

Figure 3.13: Phase-modulated RF input distribution. 88

Unit Amplifier

Figure 3.14: RF output combining in a tree structure. 89

3.6.1 CW measurements

Power measurements were performed under continuous-wave (CW) operation with a 900-MHz carrier frequency and a slowly varying ACW. Fig. 3.16 shows the monotonic variation of output power with ACW. The DPA delivered 24.9-dBm maximum output power with 62.7% maximum power efﬁciency, as well as achieving 43.9 dB of amplitude modulation (29 dB from the 7 most signiﬁcant bits). The input attenuator and supply variation together provided approximately 16 dB of transmit power control range.

Fig. 3.17 and Fig. 3.17 illustrate the measured relationship between power ef-

ﬁciency and output power in log-log scale and linear scale, respectively. The power efﬁciency is approximately proportional to the square root of the output power as described in the previous section.

Traditionally, power ampliﬁers are characterized both by drain efﬁciency and

PAE, along with gain. In this work, the input signal is a digital signal driven into a 50-Ω load with an overall power of 5.5 dBm. The input impedance would be much higher in an integrated system, and thus, the power dissipated would be very small.

With a large supply voltage and without input attenuation, the amplitude modulation is highly nonlinear due to the device operating in two regions as explained in the previous section. When the input attenuator is activated, however, the amplitude modulation becomes much more linear as the unit devices operate mostly in their active region as current sources. The worst-case phase distortion is measured to be lower than

21o. Both the amplitude and phase distortions can be corrected in the baseband using an 90

Figure 3.15: The DPA board for measurement. 91

Supply Variation

Input Atten. ON Input Atten. OFF

Figure 3.16: Measured output power vs. ACW at 900 MHz. The input attenuator and supply variation provide average transmit power control.

adaptive digital predistortion (DPD).

Similar performance is obtained in the measurement at other carrier frequencies by reconfiguring the output matching network. Moreover, a further simulation shows that it is also possible to design an optimized matching network to achieve relatively high efficiency operation (> 40%) over a very broad bandwidth, albeit with slightly lower output power, as shown in Fig. 3.18. However, this possibility is limited in the measurement due to excessive drain capacitance, which reduces the optimum operating frequency range. With an output matching network optimized at 1.92 GHz, the DPA delivered 23.31-dBm maximum output power with 36.7% overall efficiency.

To linearize the DPA, an ideal digital predistortion system is ﬁrst simulated in 92

Supply Variation

Input Atten. OFF Input Atten. ON

Figure 3.17: Measured efﬁciency vs. output power at 900 MHz, in log-log scale. 93

60 Input Atten. OFF Input Atten. ON 50

20 Efficiency [%] Efficiency Supply Variation 10

0 -20 -10 0 10 20 30 Output Power [dBm]

Figure 3.18: Measured efﬁciency vs. output power at 900 MHz.

Figure 3.19: Simulated output power and efﬁciency vs. carrier frequency with a ﬁxed output matching network optimized for a broadband performance. 94

Modulated Signal Polynomial PM Generation ACW Output Curve fitting DPA LUT from Spectrum + Back- measured data Analyzer interpolation

Predistorted Output Predistorted Amplitude ACW

Figure 3.20: Block diagram of the simulated ideal DPD system.

Figure 3.21: ACW-AM characteristic of the DPA, before and after ideal DPD. 95

MATLAB based on the measured steady-state ACW-AM transfer characteristic of the

DPA. The block diagram of the simulated system is illustrated in Fig. 3.20, where only

ACW-AM nonlinearity is compensated and ACW-PM characteristic is assumed to be ideal. The simulated ACW-AM characteristic of the DPA before and after ideal DPD is shown in Fig. 3.21 on a normalized linear scale. Notice that the lowest output power range is mapped to a much wider ACW range after the DPD, resulting in a resolution loss; while the resolution is much ﬁner in the highest ACW range.

−10

−20 Before DPD

−30

−40 After DPD Power Spectral Density (dB) −50 Input −60 −20 −15 −10 −5 0 5 10 15 20 Frequency offset (MHz)

Figure 3.22: Simulated output spectrum of a WCDMA-modulated signal, before and after ideal DPD.

The generated EDGE and WCDMA input signals have PAPRs of 3.3 dB and

3.4 dB, and their simulated output spectra, before and after ideal DPD, are shown in 96

Before DPD −10

−20 After DPD

−30

Power Spectral Density (dB) Input −40

−50 −1 −0.8 −0.6 −0.4 −0.2 0 0.2 0.4 0.6 0.8 1 Frequency offset (MHz)

Figure 3.23: Simulated output spectrum of an EDGE-modulated signal, before and after ideal DPD. 97

Fig. 3.23 and Fig. 3.22, respectively. The EDGE input signal used here, however, is a short-length variation of the real EDGE signal and will not conform to the spectral mask specifications outlined in Chapter1. The simulations show a 2 dB and a 5-8 dB degradation on the spectral performance for EDGE and WCDMA, respectively, after ideal DPD. These results show that the effective resolution is sufficient to meet the specifications.

3.6.2 WCDMA/EDGE Modulation with Digital Predistortion

Fig. 3.24 shows the demonstration system used to evaluate the performance of the DPA with practical modulated signals. An adaptive digital predistortion (DPD) loop

[43] was employed to linearize the ampliﬁer. Some advantages of adaptive DPD are that loop stability is much easier to maintain and it is relatively simple to implement with digital signal processing. The DPD system needs to be adaptive since both the AM-AM and AM-PM distortions can change with different power control settings.

First, the baseband signal is split into AM and PM components, which are time- aligned and predistorted based on the signal fed back from the output. A semi-automatic process is used to obtain accurate time mismatch information between AM and PM components. The AM signal is then fed to the DPA as a 10-bit ACW input. The PM component is used to modulate a 52-MHz digital IF carrier, which is subsequently up- converted, amplified and filtered before being fed to the DPA RF input. The RF output of the DPA is then fed back to the signal-generation system at the input through a down- converter, a low-pass filter, and a digital-IF receiver. The whole system is clocked at

207.36 MHz.

The output spectrum after DPD is shown in Fig. 3.25 for a short-length EDGE 98

207.36 MHz Phase Adjustment

ACW

AM Resolution Power Control

LO A 10 I, Q

Signal Pre Amp. Digital PM Modulated φ DAC RFOUT Rect. To Polar Rect. To Predistortion + Time Alignment DPA Up Conv. BPF LO 52-MHz PM Adaptation 52-MHz IF Feedback Gain I, Q ADC PC + Logic Analyzer Digital IQ LPF Down Conv. + Pattern Generator Down Conv.

Figure 3.24: Block diagram of the polar modulation and predistortion test setup. signal at 1.92 GHz. As summarized in Table 3.1, the measured spectral performance after DPD is in line with the simulated performance. The measured output power is

19.98 dBm with 31.83% overall efﬁciency. The DPA is also tested at 915 MHz, exhibiting a similar spectral performance with a much higher output power and efﬁciency, as summarized in Table 3.2.

For a WCDMA signal at 1.92 GHz, the measured output power is 19.26 dBm with 30.28% overall efficiency after DPD. The ACLR is -30.3 dBc and -43.32 dBc at 5 MHz and 10 MHz, respectively. The measured ACLR at 5-MHz offset frequency violates the -33-dBc specification due to the limited frequency response of the amplifier- cell commutation. Without sufficient driving power (due to excessive ACW interconnect parasitics), the turn-on and turn-off transients can be relatively slow compared to the envelope rate. The resulting memory effect degrades AM/PM time-alignment accuracy 99

and DPD performance in WCDMA, where the envelope bandwidth is much larger.

Figure 3.25: Measured EDGE output spectrum after DPD.

Figure 3.26: Measured WCDMA output spectrum and ACLRs after DPD. 100

Table 3.1: Simulated and measured EDGE spectral performance comparison.

Relative power after DPD 400-kHz offset 600-kHz offset

Simulation -47.7 dBc -52.9 dBc

Measurement -52.5 dBc -54.3 dBc

Table 3.2: Measured RF output power and overall efﬁciency for EDGE and WCDMA after DPD. Modulated signal RF output power Efﬁciency

EDGE 22.69 dBm 51.75%

(915 MHz)

EDGE 19.98 dBm 31.83%

(1.92 GHz)

WCDMA 19.26 dBm 30.28%

(1.92 GHz) 101

3.7 Summary

A high-efficiency single-ended digitally-modulated power amplifier has been demonstrated in a 0.13-µm 1.2-V SOI CMOS technology. It reliably delivers a 24.9- dBm peak output power with a maximum power efficiency of 62.7% at 900 MHz, as well as exhibits multi-band functionality with a reconfigured matching network. The

10-bit resolution provides more than 40 dB of amplitude modulation; while the integrated input attenuator and supply variation together provide 16 dB of transmit power control range. By employing an adaptive digital pre-distortion technique, the DPA could meet linearity requirements for both the EDGE and WCDMA standards. The implemented DPA, together with the proposed polar architecture, is an attractive solution for the next-generation multi-standard RF transmitter design.

3.8 Acknowledgements

Part of the material in chapter3 is as it appears in ”A 25-dBm high-efﬁciency digitally-modulated SOI CMOS power ampliﬁer for multi-standard RF polar transmitters,” S. Pornpromlikit, J. Jeong, C. D. Presti, A. Scuderi, and P. M. Asbeck, in IEEE

RFIC Symp. Dig., pp. 157-160, Jun. 2009. The contributions from the co-authors are appreciated. The author of this dissertation was the primary investigator and primary author for this publication. Chapter 4

Conclusion

4.1 Research Summary

The low breakdown voltage limit is one of the most critical problems in realizing high-efﬁciency linear power ampliﬁer in CMOS technology, especially with the on-going technology scaling to deep submicron dimensions. A state-of-the-art CMOS device would require a large impedance transformation ratio to deliver enough output power, resulting in high loss in the matching network. As preserving battery life and meeting linearity requirements have been priorities in mobile handsets, power ampli-

ﬁers are commercially implemented using more expensive GaAs-based technologies.

This dissertation proposes a stacked-FET topology as an attractive solution to the breakdown limit problem. The voltage stress is equally divided among several transistors connected in series such that the output voltage swing is added in phase, allowing the use of a much higher supply voltage. Several design issues are highlighted and discussed including proper gate biasing of stacked devices and output matching network design.

By using the proposed design technique, excellent power efﬁciency and linearity performance comparable to those of GaAs-based power ampliﬁers can be achieved in CMOS

102 103 at GHz frequency range. To demonstrate the concept, single-stage stacked-FET power ampliﬁers are implemented using alternative CMOS processes to avoid the body effect and excessive junction capacitances.

A fully integrated class-A power ampliﬁer is implemented in 0.25-µm SOS

CMOS as a prototype, delivering a maximum output power of 21.0 dBm with the high efﬁciency of 44.0% at 1.88 GHz. By using triple-stacked FETs, the optimum load impedance increases to 50 Ω so impedance transformation is not required at the output. The input matching network is also included on-chip. The ampliﬁer meets the

ACPR speciﬁcation for IS-95 CDMA operation up to an average output power of 16.3 dBm and PAE of 18.7%. To meet the Watt-level output power required in modern standards, a deep class-AB power ampliﬁer has been implemented and investigated using

0.28-µm 2.5-V standard I/O FETs available in a 0.13-µm SOI CMOS technology. The ampliﬁer achieves 47% maximum PAE and delivers 32.4-dBm saturated output power at

1.9 GHz with a 6.5-V supply. Using a reverse-link IS-95 CDMA modulated signal, the ampliﬁer shows an average output power of up to 28.7 dBm with a PAE of 41.2% while meeting the ACPR requirement. Likewise, the ampliﬁer meets the ACLR requirement of the uplink WCDMA with an average output power of up to 29.4 dBm and a PAE of

41.4%. In addition, the ampliﬁer has been tested in the low frequency band at 900 MHz with a reconﬁgured matching circuitry. A small-signal gain of 19.3 dB is achieved with a saturated output power of 29.5 dBm and a maximum PAE of 53%.

In the second part of the dissertation, a polar-based digital-intensive transceiver architecture is explored for multi-mode multi-band applications. A 10-bit single-ended

DPA is demonstrated in a 0.13-µm 1.2-V SOI CMOS technology, where the amplitude modulation is done by digitally controlling the number of activated unit amplifiers 104 whose currents are summed at the output. The DPA is operated as a pseudo class-E amplifier at full power while its efficiency rolls off with decreasing output power similar to a class-B amplifier. The measured DPA delivers a 24.9-dBm peak output power at 900

MHz with a maximum power efficiency of 62.7%. Similar high-efficiency performance is also exhibited in the high band with a reconfigured matching network. Moreover, by employing an adaptive digital pre-distortion technique, the DPA could meet linearity requirements for both the EDGE and WCDMA standards. This work demonstrates that the possibility of co-integrating high performance digital transistors with the CMOS power amplifier enables multi-band multi-standard applications with the addition of only one extra component in the external matching.

4.2 Future Work

The research work described in this dissertation represents starting points for several future researches and developments. First, the proposed stacked-FET technique provides a mean to achieve high output power with lower loss in matching network due to high impedance transformation. Since the RF input signal only drives the bottom transistor, instead of simultaneously being fed to all series-connected devices, the synchronization problem among devices is eliminated. However, each device will see a different drain current waveform due to current leakage through gate capacitances, especially at high frequency, making it difficult to achieve high efficiency though current and voltage waveform engineering. In fact, waveform shaping through harmonic impedance tuning is already difficult in the stacked-FET structure as the influence of output matching circuitry diminishes down the ladder. To achieve high efficiency, the signal waveform across the drain and source terminals of each device could be carefully 105 engineered by adding tuning components between the device connections.

In the second part of the dissertation, we show that a compact transmitter can be implemented all in the digital domain with excellent performances. However, a recon-

figurable matching network is still necessary to produce a true multi-mode multi-band transmitter system. Moreover, meeting the linearity and the wide transmitted-power control requirements for modern wireless standards is still a challenge. The amplitude modulation of the DPA is intrinsically nonlinear and requires an adaptive DPD system to work properly. In this regard, integrating an adaptive DPD system with the DPA on the same chip could be worthwhile. Other suitable linearization techniques could also be investigated. In addition, automatic time alignment between the amplitude and phase paths is another difficult task that needs to be addressed. For power control, a combination of supply voltage variation, ACW resolution reduction, input and output RF attenuators is proposed in this work to provide transmitted-power control range. Alter- natively, other techniques such as Doherty [48] and outphasing power combining [49] can be introduced. In an outphasing configuration, the outphasing angle between the two amplifiers can be employed to provide extra power control range in the low power mode, in addition to the proposed power control strategy. By combining a pair of DPAs to form a complete transmitter, the output power is doubled and the external high-power amplifier could possibly be eliminated. The Doherty DPA is, in itself, another attractive research topic, providing an improved efficiency for a wide power range, which is essential for modern communication standards with high PAPR, while offering digital controllability. References

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