LDMOS Versus Gan RF Power Amplifier Comparison Based on the Computing Complexity Needed to Linearize the Output

Article LDMOS versus GaN RF Power Amplifier Comparison Based on the Computing Complexity Needed to Linearize the Output

Raúl Gracia Sáez 1 and Nicolás Medrano Marqués 2,*

1 Research and Development Department, Teltronic S.A.U., Malpica Industrial Area, Zaragoza 50016, Spain; [email protected] 2 Electronics and Communication Department, University of Zaragoza, Faculty of Physics, Zaragoza50009, Spain * Correspondence: [email protected] Received: 13 September 2019; Accepted: 30 October 2019; Published: date Article Abstract: In orderLDMOS to maximize versus the GaNefficiency RF of Power telecommunications Amplifier Comparison equipment, it is necessary that the radio frequencyBased (RF) on power the Computingamplifier is situated Complexity as closely Needed as possible to to its compression point. This makes its responseLinearize nonlinear, the Output and therefore it is necessary to linearize it, in order to minimize the interference that nonlinearities cause outside the useful band (adjacent channel). The system Raúl Gracia Sáez 1 and Nicolás Medrano Marqués 2,* used for this linearization occupies a high percentage of the hardware and software resources of the 1 Research and Development Department, Teltronic S.A.U., Malpica Industrial Area, 50016 Zaragoza, Spain; [email protected] equipment, so it is interesting to minimize its complexity in order to make it as 2 Electronics and Communication Department, University of Zaragoza, Faculty of Physics, simple as possible.50009 This Zaragoza, paper Spain analyzes the differences between the laterally diffused MOSFET (LDMOS) and gallium* Correspondence: nitride [email protected] (GaN) power amplifiers, in terms of their nonlinearity graphs, and in terms of the greaterReceived: or 13 Septemberlesser difficulty 2019; Accepted: 30of October linearization. 2019; Published: A 1 November correct 2019 choice of power amplifier will allow for minimizationAbstract: In of order the to maximizelinearization the efficiency system, of telecommunications greatly simplifying equipment, it is the necessary complexity that of the final design. the radio frequency (RF) power amplifier is situated as closely as possible to its compression point. This makes its response nonlinear, and therefore it is necessary to linearize it, in order to minimize the interference that nonlinearities cause outside the useful band (adjacent channel). The system Keywords: linearization;used for this linearization power amplifier; occupies a high predistortion; percentage of the hardware LDMOS; and software GaN. resources of the telecommunication equipment, so it is interesting to minimize its complexity in order to make it as simple as possible. This paper analyzes the differences between the laterally diffused MOSFET (LDMOS) and gallium nitride (GaN) power amplifiers, in terms of their nonlinearity graphs, and in 1. Introduction terms of the greater or lesser difficulty of linearization. A correct choice of power amplifier will allow for minimization of the linearization system, greatly simplifying the complexity of the final design.

In order to increaseKeywords: linearization;efficiency power and amplifier; to meet predistortion; the telecommunications LDMOS; GaN standards, many different techniques [1] have been proposed and employed to extend the linear range of the power amplifier (PA) response in radiofrequency (RF) communications: crest factor reduction (CFR), feedback linearization, feedforward1. Introduction linearization, predistortion techniques, envelope elimination and restoration (EER), linearIn order amplification to increase efficiency using and to meetnon thelinear telecommunications components standards, (LINC), many diandfferent combined Analog techniques [1] have been proposed and employed to extend the linear range of the power amplifier (PA) Locked Loop Universalresponse in Modulator radiofrequency (RF)(CALLUM). communications: crest factor reduction (CFR), feedback linearization, The most commonlyfeedforward linearization, used linearization predistortion techniques, systems envelope are elimination those that and restoration use predistortion (EER), linear techniques to amplification using nonlinear components (LINC), and combined Analog Locked Loop Universal linearize the powerModulator amplifier (CALLUM). (Figure 1). The most commonly used linearization systems are those that use predistortion techniques to linearize the power amplifier (Figure1).

Figure 1. Basis of Predistortion Techniques. Figure 1. Basis of Predistortion Techniques.

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The objective of the predistorter is to correct the nonlinearity that is introduced by the amplifier by distorting the input signal x(t) to be amplified, so that the PA output presents a behavior that is proportional to the input signal x(t) (Figure1), minimizing the nonlinear distortion and hence improving the corresponding adjacent channel power (ACP). The ACP is the part of the frequency spectrum of the signal generated in our channel that interferes with the adjacent frequency channels [1]. The reduction of the ACP allows for transmissions at higher RF power levels using the same amplifier, therefore increasing its efficiency. Many techniques have been developed to implement the predistorter: Volterra series [2], Memory Polynomials [3], Wiener and Hammerstein models [4], Lookup Tables (LUTs) [5], Neural Networks [6], Neural–Fuzzy systems [7], Genetic Algorithms [8], etc. A lot of engineers face every day the problem of having to linearize a power amplifier, employing a limited number of computational resources, and discovering that not all of the amplifiers can be linearized using the same techniques. The aim of this work is to show how to simplify the design of the linearization system by means of the correct choice of power amplifier. It will be shown that the variation of the output power versus the input power must be deeply analyzed before the amplifier selection. This will decrease the number of computational resources required to linearize the system and to meet the telecommunication standards. This paper is structured as follows. Section2 presents the materials and methods that were used in the elaboration of this work. Section 3.1 describes how a predistorter works. Section 3.2 shows a comparison between laterally diffused MOSFET (LDMOS) and gallium nitride (GaN) power amplifiers. Section 3.3 presents a comparison of the required hardware and software resources to implement predistorters for LDMOS and GaN power amplifiers. Section 3.4 shows the obtained results of linearizing an LDMOS and a GaN amplifier using a Multilayer Perceptron Neural Network Digital Predistorter (DPD). Finally, Section4 presents the conclusions of this work.

2. Materials and Methods The following power ampliﬁers were considered in this paper:

- PD57006S-E: an LDMOS ampliﬁer manufactured by ST Microelectronics, with the following characteristics:

- Output power: 5 W - Power supply: 28 V - Gain: 14.8 dB -E ﬃciency: 50% - NPTB00004A: a GaN ampliﬁer manufactured by MACOM, with the following characteristics:

- Output power: 6 W - Power supply: 28 V - Gain: 15 dB -E ﬃciency: 62%

The OMAP-L138, manufactured by Texas Instruments, was used to implement the predistortion techniques. It is a low-power DSP (Digital Signal Processor) + ARM (Advanced RISC Machine) processor capable of working at a clock frequency of 456 MHz. The neural networks that we used in this paper were trained using the Matlab Neural Network Toolkit. TETRA was selected as the telecommunication standard to modulate the input signal of the power ampliﬁers. TETRA is a 25 KHz bandwidth digital standard designed for professional radio communications. Electronics 2019, 8, 1260 3 of 11

3. Results

3.1. Predistortion Technique Figure2 shows the typical Gain (G) and E ﬃciency (η) curves for an LDMOS power ampliﬁer Figure 2 shows the typical Gain (G) and Efficiency (η) curves for an LDMOS power amplifier (model PD57006S-E manufactured by ST Microelectronics). (model PD57006S-E manufactured by ST Microelectronics). As Figure 2 shows, as the output power increases, the efficiency of the amplifier also increases, up to a maximum value from which the gain begins to fall. The power output compression point (P1dB) is the output power that generates a gain compression of 1 dB in the amplifier. As the output power of the amplifier approaches the P1dB, the amplifier enters into the nonlinear operation region, distorting the output signal. Since the device must be as efficient as possible, the PA is configured to work near the P1dB of the amplifier, and therefore it will be necessary to apply a linearization technique in order to minimize the nonlinear distortion. One of these linearization techniques is predistortion. As can be seen in Figure 1, the predistorter module modifies the input signal of the PA in order to pre-correct its nonlinearity. For this, the predistorter operation should be as similar as possible to the inverse function of the PA transfer function. There are different techniques to estimate the PA transfer function (Figure 3), and one of the most commonly used is the Memory Polynomial method.

Figure 2. Measured characteristics of a LDMOS power ampliﬁer (PA) (model PD57006S-E, ST FigureMicroelectronics) 2 and the polynomial approximations.

As Figure2 shows, as the output power increases, the e fficiency of the amplifier also increases, up to a maximum value from which the gain begins to fall. The power output compression point (P1dB) is the output power that generates a gain compression of 1 dB in the amplifier. As the output power of the amplifier approaches the P1dB, the amplifier enters into the nonlinear operation region, distorting the output signal. Since the device must be as efficient as possible, the PA is configured to work near the P1dB of the amplifier, and therefore it will be necessary to apply a linearization technique in order to minimize the nonlinear distortion. One of these linearization techniques is predistortion. As can be seen in Figure1, the predistorter module modifies the input signal of the PA in order to pre-correct its nonlinearity. For this, the predistorter operation should be as similar as possible to the inverse function of the PA transfer function.Figure There 2. Measured are different characteristics techniques of to a estimateLDMOS thepowe PAr transferamplifier function (PA) (model (Figure PD57006S-E,3), and one ST of the mostMicroelectronics) commonly used and is thethe Memorypolynomial Polynomial approximations. method.

Figure 6

Figure 3. Generic predistortion scheme.

The Memory Polynomial model consists of: 𝑦𝑛 𝑎 𝑝𝑛𝑚|𝑝𝑛𝑚| (1) where K is the order of the polynomial model and M is the memory depth.

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The Memory Polynomial model consists of:

K 1 M 1 X− X− k y(n) = a p(n m) p(n m) (1) km − − k=0 m=0 where K is the order of the polynomial model and M is the memory depth. When the signal bandwidth is wide (hundreds of kHz), the memory eﬀect of the PA becomes When the signal bandwidth is wide (hundreds of kHz), the memory effect of the PA becomes relevant, requiring it to be taken into account. Otherwise, when the signal bandwidth is narrow relevant, requiring it to be taken into account. Otherwise, when the signal bandwidth is narrow (<100 (<100 kHz), the memory eﬀect is negligible (M = 1) and therefore (1) can be reduced to: kHz), the memory effect is negligible (M = 1) and therefore (1) can be reduced to: K 1 X− k 𝑦y𝑛(n)𝑎= ak𝑝p(𝑛n|) 𝑝p(𝑛n|) . (2) (2) k=0 Thus, the transfer function of the PA is modeled as a polynomial, and its inverse function is used as the transfer function of the predistorter module. The feedback path path in in Figure Figure 3 provides memory compensation compensation (if (if necess necessary)ary) and and allows allows for for a continuousa continuous compensation compensation loop loop against against changes changes in in the the PA PA transfer transfer function function due due to to temperature, frequency, oror powerpower supplysupply variations.variations. This predistortionpredistortion technique technique requires requires the the transfer transf functioner function to be to recalculated be recalculated periodically, periodically, adding addingcomplexity complexity to the design, to the duedesign, to the due required to the required hardware hardware and software and resources.software resources. Therefore, Therefore, reducing reducingthe degree the of thedegree polynomial of the polynomial model of the model PA becomes of the PA mandatory becomes tomandatory minimize to the minimize used resources the used to resourcesobtain the to transfer obtainfunction, the transfer for whichfunction, correct for which selection correct of the selection PA will of be the pivotal, PA will as willbe pivotal, be seen as in will the benext seen sections. in the next sections.

3.2. LDMOS LDMOS versus GaN Power Amplifiers Amplifiers Until the appearance of GaN amplifiersamplifiers (around(around 2005), LDMOS amplifiersamplifiers had dominated the market of high-power RF transmissions at frequencies below 2 GHz due to their low cost. The only competitors were the gallium arsenide (GaAs) amplifie amplifiersrs that allowed for higher frequencies, but at low power-transmission levels andand withwith higherhigher cost.cost. Currently, although the improvements in LDMOS amplifieramplifier characteristics allow for frequency ranges up to 22 GHz, GaN-based amplifiers amplifiers [[9]9] achieveachieve frequencies up to 30 GHz at power densities up to fivefive times higher, althoughalthough at higherhigher pricesprices thanthan LDMOSLDMOS devices.devices. Figure 44 shows shows thethe LDMOSLDMOS and GaN transistor structures.

Figure 4. LDMOS and gallium nitride (GaN) transistor structures.

The main advantage of GaN is its higher power density. This is due to a band gap between the conduction and valence bands (Figure5 5)) thatthat isis higherhigher thanthan inin LDMOSLDMOS technologies,technologies, whichwhich providesprovides both high breakdown voltages and power densities.

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Figure 5.5. Band gap for LDMOS and GaN.

A comparison between LDMOSLDMOS andand GaNGaN technologiestechnologies isis shownshown inin TableTable1 .1. Higher power density allows for GaN power amplifiers to operate at higher temperatures, Table 1. Comparison between LDMOS and GaN technologies. therefore simplifying heat-sink and cooling requirements. The lower input capacitance (gate-source capacitance,LDMOS Cgs) of GaN power GaN amplifiers results in lower amplitude modulationMaximum frequencyto phase modulation (AM-PM) 22 GHz distortion values 30 GHz [10] than LDMOS. This, together with a lowerPower output density capacitance (drain-source 2 W/ mmcapacitance, Cds) 10 Wand/mm the higher input and output resistancesEﬃ (Rinciency and at P1dBRout), makes input and 60%output impedances 70% for the GaN power amplifiers higher, thereforeBandwidth allowing for simpler and 500lower MHz loss circuits 2500 and MHz wide bandwidth matching networks.Maximum Currently, temperature this makes the GaN PAs more Lower widely used than Higher the LDMOS devices Breakdown voltage Lower Higher for broadband applications.Maximum operating voltage Lower Higher Nevertheless, LDMOS Cgstransistors are still more widely Higher used than GaN LowerPAs in some specific applications, such as wirelessCds infrastructures, low-power Higher battery-operated transceivers, Lower small cells, and some microwave links, mainlyRin because LDMOS devices Lower can use plastic packaging—significantly Higher reducing their cost. In addition,Rout LDMOS transistors are more Lower robust against impedance Higher mismatching, Maximum RF power 1.5 kW 1 kW which makes them preferablePrice in the aforementioned application Lower fields. Higher Robustness against impedance mismatches Higher (65:1) Lower (20:1) Table 1. Comparison between LDMOS and GaN technologies.

Higher power density allows for GaN power amplifiers LDMOS to operate GaN at higher temperatures, therefore simplifying heat-sinkMaximum and cooling frequency requirements. 22 GHz 30 GHz The lower input capacitancePower (gate-source density capacitance, Cgs) 2 W/mm of GaN 10 power W/mm amplifiers results in lower amplitude modulationEfficiency to phase at modulation P1dB (AM-PM) distortion60% values 70% [10] than LDMOS. This, together with a lower outputBandwidth capacitance (drain-source capacitance,500 MHz 2500 Cds) MHz and the higher input and output resistances (RinMaximum and Rout), temperature makes input and output Lower impedances Higher for the GaN power amplifiers higher, therefore allowingBreakdown for simpler voltage and lower loss circuits Lower and wide Higher bandwidth matching networks. Currently, thisMaximum makes theoperating GaN PAsvoltage more widely Lower used than Higher the LDMOS devices for broadband applications. Cgs Higher Lower Nevertheless, LDMOS transistorsCds are still more widely usedHigher than GaNLower PAs in some specific applications, such as wireless infrastructures,Rin low-power battery-operatedLower Higher transceivers, small cells, and some microwave links, mainly becauseRout LDMOS devices canLower use plastic Higher packaging—significantly reducing their cost. In addition,Maximum LDMOS RF transistors power are more robust 1.5 kW against 1impedance kW mismatching, which makes them preferable in the aforementionedPrice applicationLower fields. Higher If we analyze the typical characteristics of a GaN PA, modelHigher NPTB00004A Lower manufactured by Robustness against impedance mismatches MACOM (Figure6), we observe that it has a smoother transition(65:1) into the(20:1) saturated region than a LDMOS PA (Figure2). If we analyze the typical characteristics of a GaN PA, model NPTB00004A manufactured by MACOM (Figure 6), we observe that it has a smoother transition into the saturated region than a LDMOS PA (Figure 2).

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Electronics 2019, 8, 1260 6 of 11 Figure 2

Figure 6. Measured characteristics of a GaN PA (model NPTB00004A, MACOM) and the Figurepolynomial 6 approximations.

As will be seen in Section 3.3, this smoother transition can be critical in order to determine the linearization system complexity. Since there are not generic equations for the Gain and for the Eﬃciency of LDMOS and GaN transistors, we can approximate these equations for the transistor models selected in this paper (Table2).

Table 2. Approximated equations for the selected LDMOS and GaN transistors. Gain is expressed in dB, Eﬃciency is expressed in percentage, and Pout (Output Power) is expressed in Watts.

LDMOS (PD57006S-E) GaN (NPTB00004A) 4 3 2 Gain = 0.00001Pout + 0.0006Pout 0.015Pout + 3 2 − − Gain = 0.00004Pout 0.002Pout 0.0074Pout + 15.035 0.1817Pout + 14.221 − − E f f iciency = 2 3 2 E f f iciency = 0.0245P + 2.1901Pout + 8.8977 0.0025P 0.1518P + 3.8583Pout + 5.3202 − out out − out

3.3. Complexity Analysis of the Linearization System (LDMOS vs. GaN)

In order to compare the linearization complexity1 of GaN and LDMOS power ampliﬁers [11], we can draw their output power versus input power. Figures7 and8 show the experimental input–output transfer functions and polynomial approximations for LDMOS and GaN, respectively, for diﬀerent polynomial orders. Electronics 2019, 8, 1260 7 of 11

Figure 7. Output power versus input power for an LDMOS PD57006S-E ampliﬁer (continuous line) Figure 7. Outputand the power polynomial versus approximation input power (dash line) for whenan LDMOS the polynomial PD57006S-E order is changed amplifier (top: order(continuous 2, line) and the polynomialmiddle: order approximation 3, bottom: order 4).(dash line) when the polynomial order is changed (top: order 2, middle: order 3, bottom: order 4).

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Figure 8. Output power versus input power for a GaN NPTB00004A ampliﬁer (continuous line) and Figure 8. Outputthe polynomial power approximation versus input (dash power line) when for a the Ga polynomialN NPTB00004A order is changed amplifier (top: order (continuous 2, bottom: line) and the polynomialorder 3).approximation (dash line) when the polynomial order is changed (top: order 2,

bottom: orderAs 3). can be seen in Figure8, a third-order polynomial is enough to model GaN PAs with an error level below 0.1%, while a fourth-order polynomial is required for LDMOS amplifiers (Figure7), As can achievingbe seen anin errorFigure of 0.6%. 8, a third-order Therefore, it can polynomial be assumed thatis enough GaN amplifiers to model will requireGaN PAs a lower with an error level belownumber 0.1%, ofwhile coefficients a fourth-order and computing polynomial resources to implement is required a predistortion for LDMOS linearization amplifiers technique (Figure 7), than LDMOS devices will. achieving an errorThis higherof 0.6%. complexity Therefore, needed toit linearizecan be theassumed LDMOS amplifiersthat GaN is due amplifiers mainly to the will hump require the a lower number of coefficientsLDMOS characteristically and computing presents resources before the powerto implement output saturation a predistortion (Figure2), compared linearization to the technique than LDMOSGaN devices PA’s smoother will. shape. This difference can be also observed when comparing Figures2 and6. Furthermore, the GaN PA’s smoother behavior near the transition into saturation means that GaN This higher complexity needed to linearize the LDMOS amplifiers is due mainly to the hump amplifiers can operate closer to the saturated region, where efficiency is higher and distortion slowly the LDMOSincreases characteristically as the device approachespresents saturation.before the This power allows output GaN amplifiers saturation to operate (Figure nearer 2), to the compared to the GaN PA’sP1dB smoother point. shape. This difference can be also observed when comparing Figures 2 and

6. 3.4. Power Amplifier Complexity Comparison Furthermore, the GaN PA’s smoother behavior near the transition into saturation means that A comparison of the complexity required in the linearization of the output power between LDMOS GaN amplifiersand GaN can PAsoperate was carried closer out to by the analyzing saturated the resources region, necessary where toefficiency meet the standard is higher TETRA and distortion slowly increasesspecifications as the [ 12device]. For this,approaches a multilayer saturati perceptronon. (MLP)This neuralallows network GaN amplifiers DPD was selected to operate as nearer to the P1dB predistorterpoint. technique. This technique has previously shown its advantages compared to classical predistortion techniques [13]. The MLP DPD distorts the PA input signal, providing a correction to the amplifier output nonlinearities (Figure9), thus improving the ACP of the output signal. 3.4. Power Amplifier Complexity Comparison A comparison of the complexity required in the linearization of the output power between LDMOS and GaN PAs was carried out by analyzing the resources necessary to meet the standard TETRA specifications [12]. For this, a multilayer perceptron (MLP) neural network DPD was selected as predistorter technique. This technique has previously shown its advantages compared to classical predistortion techniques [13]. The MLP DPD distorts the PA input signal, providing a correction to the amplifier output nonlinearities (Figure 9), thus improving the ACP of the output signal. The MLP consists of nonlinear output processors arranged in layers, whose interconnections are reinforced or weakened through a training process to attain a configuration that achieves the suitable nonlinearity compensation. To perform the comparison, two PAs with similar features were selected for their linearization: a MACOM NPTB00004A (GaN technology) and an ST PD57006S-E (LDMOS technology).

Electronics 2019, 8, x; doi: FOR PEER REVIEW www.mdpi.com/journal/electronics An MLP consisting of one hidden layer with 20 processors using the hyperbolic tangent output function was trained to provide the predistortion values required to extend the linear range of the power amplifier output [13]. The single processors in input and output layers both provide linear transfer functions. Neural network training is performed using the Levenberg–Marquardt algorithm [14]. The neural network configuration can be seen in Figure 10. The results can be seen in Table 3, where a TETRA signal has been used as input signal, and the output power of both amplifiers has been obtained, increasingElectronics 2019 ,the8, 1260 input power to obtain at the output a power 1.5 dB less than9 the of 11 P1dB.

Figure 9. Digital predistorter (DPD) technique using a neural network. An MLPFigure consisting 9. Digital of one predistorter hidden layer (DPD) with 20 tec processorshnique using using thea neural hyperbolic network. tangent output function was trained to provide the predistortion values required to extend the linear range of the power The MLP consists of nonlinear output processors arranged in layers, whose interconnections are amplifier output [13]. The single processors in input and output layers both provide linear transfer reinforced or weakened through a training process to attain a configuration that achieves the suitable functions. Neural network training is performed using the Levenberg–Marquardt algorithm [14]. The nonlinearity compensation. neural network configuration can be seen in Figure 10. The results can be seen in Table 3, where a To perform the comparison, two PAs with similar features were selected for their linearization: TETRA signal has been used as input signal, and the output power of both amplifiers has been a MACOM NPTB00004A (GaN technology) and an ST PD57006S-E (LDMOS technology). obtained, increasing the input power to obtain at the output a power 1.5 dB less than the P1dB. An MLP consisting of one hidden layer with 20 processors using the hyperbolic tangent output function was trained to provide the predistortion values required to extend the linear range of the power amplifier output [13]. The single processors in input and output layers both provide linear transfer functions. Neural network training is performed using the Levenberg–Marquardt algorithm [14]. The neural network configuration can be seen in Figure 10. The results can be seen in Table3, where a TETRA signal has been used as input signal, and the output power of both amplifiers has been obtained, increasingFigure the input 9. Digital power predistorter to obtain (DPD) at the tec outputhnique ausing power a neural 1.5 dB network. less than the P1dB.

Figure 10. Neural network configuration.

According to the results shown in Table 3, the proposed MLP architecture does not sufficiently improve the linear behavior of the LDMOS PA output power. So, the number of processors in the hidden layer should be increased to achieve the required ACP improvement, similar to that of the

GaN amplifier. The corresponding results are shown in Table 4. As can be seen, a single hidden-layer neural network is not capable of achievingFigureFigure 10.10. Neurala suitable network linearization configuration.configuration. for an LDMOS PA. Therefore, an additional hidden layerTable 3. isAdjacent defined channel in powerthe MLP (ACP) improvementstructure usingto obtain a 20 neuron the neural expected network. ACP improvement. (Table 5). According to the results shown in Table 3, the proposed MLP architecture does not sufficiently improve the linear behavior of the LDMOS PA outputNTPB00004A power. So, the number PD57006S-E of processors in the hidden layerOutput should 1dB be compression increased to point achieve (P1dB) the required 36.5 ACP dBm improvement, 37.5 similar dBm to that of the TableGaN amplifier.3. Adjacent TheOutput channelcorresponding Power power @ 925 results MHz(ACP) are improvemenshown in Table 35 dBmt 4.using As can a be20 se neuronen, 36 a dBm single neural hidden-layer network. neural network isE notfficiency capable @ Output of achieving Power a suitable linearization 50% for an LDMOS 40% PA. Therefore, an additional hidden layerACP is improvement defined in the MLP structure to 12NTPB00004A obtain dB the expected 10.5PD57006S-E ACP dB improvement. (TableOutput 5). 1dB compression point (P1dB) 36.5 dBm 37.5 dBm AccordingOutput to the results Power shown @ 925 in Table MHz3, the proposed MLP 35 dBm architecture does 36 not dBm su ffi ciently improve theTable linear 3. Adjacent behavior channel of the power LDMOS (ACP) PA improvemen output power.t using So, a 20 the neuron number neural of network. processors in the Efficiency @ Output Power 50% 40% hidden layer should be increased to achieve the required ACPNTPB00004A improvement, PD57006S-E similar to that of the GaN amplifier. The correspondingOutputACP 1dB improvement compression results are shown point in(P1dB) Table 4. As 36.5 can dBm 12 be seen,dB a single 37.5 dBm hidden-layer 10.5 dB neural network is not capableOutput of achieving Power a suitable@ 925 MHz linearization for 35 an dBm LDMOS PA. 36 Therefore, dBm an additional hidden layer is defined in the MLP structure to obtain the expected ACP improvement. (Table5). Table 4. ACP improvementEfficiency when varying @ Output the Power number of neurons 50% of the neural 40% network in the selected ACP improvement 12 dB 10.5 dB LDMOS amplifier.

Table 4. ACP improvementNumber when of varying neurons the number ACP of neurons improvement of the neural network in the selected LDMOS amplifier. 20 10.5 dB Number of neurons ACP improvement 30 20 10.511 dB dB 40 or more30 11 11.2 dB dB 40 or more 11.2 dB Electronics 2019, 8, x; doi: FOR PEER REVIEW www.mdpi.com/journal/electronics Electronics 2019, 8, x; doi: FOR PEER REVIEW www.mdpi.com/journal/electronics Electronics 2019, 8, 1260 10 of 11

Table 4. ACP improvement when varying the number of neurons of the neural network in the selected LDMOS ampliﬁer.

Number of Neurons ACP Improvement 20 10.5 dB 30 11 dB 40 or more 11.2 dB

Table 5. Neural network structures required to obtain the same ACP improvement for the selected LDMOS and GaN ampliﬁers.

Neurons in 1st Hidden Layer Neurons in 2nd Hidden Layer ACP Improvement NTPB00004A 20 - 12 dB PD57006S-E 18 6 12 dB

The increment in the number of hidden layers and processors drastically increases the complexity of the solution, which can be compared to the increase in the order of the polynomial model previously shown in Section 3.3. Predistorting the input signal using the MLP-based technique adds a time delay in the signal output. In the case of the selected GaN, the proposed architecture using 20 neurons in a single hidden layer running in an L138 OMAP (Open Multimedia Applications Platform) at a clock frequency of 456 MHz supposes a delay in the output signal of 15 ms (6500 clock cycles). In the case of the selected LDMOS, for the proposed architecture using 18 neurons in the ﬁrst hidden layer and six neurons in the second hidden layer, the number of clock cycles required to calculate the neural network output under the same aforementioned conditions is 8500, corresponding to a time delay of 20 ms. Therefore, we could conclude that to achieve a similar timing delay, in the case of the LDMOS PA the DSP frequency should be increased to over 610 MHz. Table6 shows these results.

Table 6. Required resources to linearize with a neural network.

GaN LDMOS Number of cycles to linearize with the neural network 6500 8500 Necessary DSP frequency to linearize in 15 ms 456 MHz 608 MHz

4. Discussion This paper shows the need to select the technology of the amplifier in order to correctly linearize its output through the available resources. We will have to evaluate whether the available resources are capable of linearizing the power amplifier, taking into account that a GaN amplifier is easier to linearize than an LDMOS amplifier, due basically to the smoother transition into saturation of the GaN amplifiers.

Author Contributions: Conceptualization, R.G.S.; methodology, R.G.S., N.M.M.; software, R.G.S.; validation, R.G.S., N.M.M.; formal analysis, R.G.S., N.M.M.; investigation, R.G.S., N.M.M.; resources, R.G.S., N.M.M.; data curation, R.G.S., N.M.M.; writing—original draft preparation, R.G.S.; writing—review and editing, R.G.S., N.M.M.; Visualization, R.G.S., N.M.M.; supervision, R.G.S., N.M.M.; project administration, R.G.S., N.M.M.; funding acquisition, N.M.M. Funding: This work was supported by the MINECO-FEDER, UE (TEC2015-65750-R) Research Project. Acknowledgments: The authors would like to thank the firm Teltronic SAU for the collaboration in the development of the tests that have been described in this article. The authors would also like to thank the Aragon Institute for Engineering Research (I3A) of the University of Zaragoza for providing technical support. Conflicts of Interest: The authors declare no conflicts of interest. The founding sponsors had no role in the design of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript; and in the decision to publish the results. Electronics 2019, 8, 1260 11 of 11

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