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Standard Cell Library Design and Optimization with CDM for Deeply Scaled Finfet Devices

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Standard Cell Library Design and Optimization with CDM for Deeply Scaled Finfet Devices Standard Cell Library Design and Optimization with CDM for Deeply Scaled FinFET Devices. by Ashish Joshi, B.E A Thesis In Electrical Engineering Submitted to the Graduate Faculty of Texas Tech University in Partial Fulfillment of the Requirements for the Degree of MASTER OF SCIENCES IN ELECTRICAL ENGINEERING Approved Dr. Tooraj Nikoubin Chair of Committee Dr. Brian Nutter Dr. Stephen Bayne Mark Sheridan Dean of the Graduate School May, 2016 © Ashish Joshi, 2016 Texas Tech University, Ashish Joshi, May 2016 ACKNOWLEDGEMENTS I would like to sincerely thank my supervisor Dr. Nikoubin for providing me the opportunity to pursue my thesis under his guidance. He has been a commendable support and guidance throughout the journey and his thoughtful ideas for problems faced really been the tremendous help. His immense knowledge in VLSI designs constitute the rich source that I have been sampling since the beginning of my research. I am especially indebted to my thesis committee members Dr. Bayne and Dr. Nutter. They have been very gracious and generous with their time, ideas and support. I appreciate Dr. Nutter’s insights in discussing my ideas and depth to which he forces me to think. I would like to thank Texas Instruments and my colleagues Mayank Garg, Jun, Alex, Amber, William, Wenxiao, Shyam, Toshio, Suchi at Texas Instruments for providing me the opportunity to do summer internship with them. I continue to be inspired by their hard work and innovative thinking. I learnt a lot during that tenure and it helped me identifying my field of interest. Internship not only helped me with the technical aspects but also build the confidence to accept the challenges and come up with the innovative solutions. I have the great pleasure working with Dr. Li. He helped me understanding the intricacies of the Analog Designs which further strengthen my interest towards mixed signal design and verification. His guidance to his students goes well beyond the regular duty of the course instructor. I am highly indebted and thankful to my family, Dr. Surinder Kumar Joshi, Mrs. Renu Joshi and Ashinder Joshi for their continual moral support, encouragement and confidence in me, without whom it was not possible. Lastly, to all my friends, thank you for your understanding and encouragement in many moments of crisis. I cannot list all the names here, but you are always on my mind. ii Texas Tech University, Ashish Joshi, May 2016 TABLE OF CONTENTS ACKNOWLEDGEMENTS ........................................................................................... ii TABLE OF CONTENTS .............................................................................................. iii ABSTRACT .................................................................................................................. vi LIST OF TABLES ....................................................................................................... vii LIST OF FIGURES .................................................................................................... viii 1. INTRODUCTION ..................................................................................................... 1 1.1 Motivation ....................................................................................................... 1 1.1.1 Why do need Low Power ......................................................................... 1 1.1.2 Why Improve the Standard Cell Based Design flow ............................... 1 1.2 Contribution of the Thesis ............................................................................... 2 1.3 Organization of the Thesis .............................................................................. 2 2. DIGITAL DESIGN FLOW ....................................................................................... 3 2.1 Full Custom Design Flow ................................................................................ 3 2.2 Semi-Custom Design Flow ............................................................................. 4 2.2.1 Introduction .............................................................................................. 4 2.2.2 ASIC Cell based design flow ................................................................... 4 2.2.3 Advantages and Limitations of ASIC ...................................................... 5 2.2.4 Application and Trends ............................................................................ 5 2.2.5 Standard Cell library design in Industry .................................................. 6 2.3 Power Dissipation in the CMOS Circuits ........................................................ 6 2.3.1 Dynamic Power ........................................................................................ 6 2.3.1.1 Hazards and Glitch Power .................................................................... 7 2.3.2 Short Circuit Power Dissipation .............................................................. 8 2.3.3 Leakage Power Dissipation ...................................................................... 9 3. FinFET vs PLANER BULK MOSFET DEVICES .................................................. 12 3.1 I-V Characteristics ......................................................................................... 13 3.2 Drain Induced Barrier Lowering ................................................................... 14 3.3 Subthreshold Swing ....................................................................................... 15 4. CDM LOGIC STYLE .............................................................................................. 17 4.1 CDM with Complementary Outputs Cells .................................................... 17 iii Texas Tech University, Ashish Joshi, May 2016 4.2 Feedback and Correction Mechanism ........................................................... 18 4.3 Performance comparison in CDM and CMOS for complementary outputs . 19 4.3.1 AND-NAND gate implemented in CDM and CMOS ........................... 19 4.3.2 OR-NOR gate implemented in CDM and CMOS Logic Style .............. 22 4.3.3 3-Input AND-NAND gate in CMOS and CDM Logic Style ................. 25 4.3.4 3-Input NOR-OR gate implemented in CMOS and CDM Logic Style . 28 4.4 Power Saving with CDM .............................................................................. 30 4.5 CDM with Single Output Cells ..................................................................... 31 4.5.1 AND Gate............................................................................................... 33 4.5.2 OR gate................................................................................................... 34 4.5.3 3-Input AND gate in CDM single output logic style ............................. 36 4.5.4 3-Input OR Gate ..................................................................................... 37 4.5.5 Half Adder Comparison ......................................................................... 39 4.5.6 Full Adder Comparison .......................................................................... 40 4.5.7 4:2 Compressor comparison ................................................................... 42 4.5.8 4 bit by 4 bit Multiplier .......................................................................... 43 4.6 Data Analysis ................................................................................................ 45 5. SINGLE OUTPUT CDM STANDARD CELL LIBRARY DESIGN ..................... 47 5.1 Standard Cell Library Design Flow ............................................................... 49 5.2 Benchmark Circuits ....................................................................................... 50 5.3 Synthesis Results with CDM standard cell library ........................................ 51 5.4 Data Analysis ................................................................................................ 54 5.5 Binary to BCD Converter .............................................................................. 56 5.5.1 Binary to BCD converter in CBLD ........................................................ 57 5.5.1.1 Introduction ........................................................................................ 57 5.5.1.2 Binary to BCD converter architecture ................................................ 58 5.5.1.3 Synthesis Results ................................................................................ 59 5.5.1.4 Synthesis Results with CDM standard cell library ............................. 63 6. CONCLUSION AND FUTURE WORK................................................................. 66 Appendix A .................................................................................................................. 68 DESIGN COMPILER SCRIPT ................................................................................ 68 C-CMOS LOGIC CELL NETLIST ......................................................................... 69 CDM LOGIC CELL NETLIST ............................................................................... 70 iv Texas Tech University, Ashish Joshi, May 2016 SILICON SMART STANDARD CELL LIBRARY CHARACTERIZATION SCRIPT .................................................................................................................... 76 References .................................................................................................................... 80 v Texas Tech University, Ashish Joshi, May 2016 ABSTRACT In this thesis, we propose the new methodology to implement
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