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Eg, Nangate 15 Nm Standard Cell Library Nanosystem Design Kit (NDK): Transforming Emerging Technologies into Physical Designs of VLSI Systems G. Hills, M. Shulaker, C.-S. Lee, H.-S. P. Wong, S. Mitra Stanford Massachusetts University Institute of Technology Abundant-Data Explosion “Swimming in sensors, drowning in data” Wide variety & complexity Unstructured data 0 40K 0 ExaB (Billionsof GB) 2006 Year 2020 Mine, search, analyze data in near real-time Data centers, mobile phones, robots 2 Abundant-Data Applications Huge memory wall: processors, accelerators Energy Measurements Genomics classification Natural language processing 5% 18 % 0% 0% … 95 82 % % Compute Memory Intel performance counter monitors 2 CPUs, 8-cores/CPU + 128GB DRAM 3 US National Academy of Sciences (2011) 4 Computing Today 2-Dimensional 5 3-Dimensional Nanosystems Computation immersed in memory 6 3-Dimensional Nanosystems Computation immersed in memory Increased functionality Fine-grained, Memory ultra-dense 3D Computing logic Impossible with today’s technologies 7 Enabling Technologies 3D Resistive RAM Massive storage No TSV 1D CNFET, 2D FET Compute, RAM access thermal STT MRAM Ultra-dense, Quick access fine-grained 1D CNFET, 2D FET vias Compute, RAM access thermal 1D CNFET, 2D FET Silicon Compute, Power, Clock compatible thermal 8 Nanosystems: Compact Models Essential 3D Resistive RAM nanohub Massive storage 1D CNFET, 2D FET Compute, RAM access thermal STT MRAM Quick access m-Cell 1D CNFET, 2D FET Compute, RAM access thermal 1D CNFET, 2D FET Compute, Power, Clock thermal 9 Compact Models: Insufficient Alone Design for Realistic Systems Wire parasitics Inter-module interface circuits Routing congestion Application-dependent workloads Multiple clock domains Cache architecture Memory access patterns Processor vs. memory … Sleep mode & sleep transistors High performance vs. low power SRAM retention Dynamic power vs. leakage power DRAM refresh Placement utilization 10 Example: OpenSparc T2 Processor Core Design for Realistic Systems Wire parasitics Inter-module interface circuits Routing congestion Application-dependent workloads Multiple clock domains Cache architecture Memory access patterns Processor vs. memory … Sleep mode & sleep transistors High performance vs. low power SRAM retention Dynamic power vs. leakage power DRAM refresh Placement utilization 0.5 FinFET CNFET energy/cycle (nJ) preferred corner 0.05 0.2 1 5 clock frequency (GHz) 11 Example: OpenSparc T2 Processor Core Design for Realistic Systems Wire parasitics Inter-module interface circuits Routing congestion Application-dependent workloads Multiple clock domains Cache architecture Memory access patterns Processor vs. memory Timing variations Sleep mode & sleep transistors High performance vs. low power Noise immunity SRAM retention Dynamic power vs. leakage power Energy variations DRAM refresh Placement utilization Functional yield … 0.5 FinFET CNFET + variations CNFET energy/cycle (nJ) preferred corner 0.05 0.2 1 5 clock frequency (GHz) 12 Variation-Aware Nanosystem Design CNFET + variations co-optimized processing & design 0.5 FinFET CNFET energy/cycle (nJ) preferred corner 0.05 0.2 1 5 clock frequency (GHz) 13 Our Nanosystem Design Kit (NDK) • Available: nanohub.org 14 Accessing the NDK • Link . https://www.nanohub.org/groups/nanosystems • File . ndk_v2016-12-13.tar 15 NDK: Tool Dependencies • Tools . Synopsys CAD tools: lc_shell, dc_shell, icc_shell, Milkyway, StarRC . Cadence CAD tools: spectremdl . common unix utilities: sed, grep, cat, ... Matlab . perl 16 NDK: Tool Dependencies • External resources (free download) . Compact model . E.g., virtual source CNFET model . Process Design Kit (PDK) . E.g., NanGate 15 nm standard cell library . Register-Transfer Level (RTL) hardware description . E.g., OpenSparc T2 processor core 17 Installing the NDK 1. untar ndk_v2016-12-13.tar 2. Set environment variables . $SVNROOT, $NDK, $DATAROOT, $XT 3. Download external resources . Compact model, PDK, RTL 4. Run installation scripts . bash scripts inside $NDK/install 18 NDK User Guide directory structure within $NDK Case Study: CNFET Processor Core OpenSparc T2 SoC core1 core2 core3 core4 thermal core5 core6 core7 core8 www.opensparc.net + CNFET compact model thermal thermal 20 Carbon Nanotube FET (CNFET) carbon nanotube (CNT) d~1nm sub-lithographic CNT pitch gate oxide 21 NDK: High-Level Overview experimental data+ compact models + variations 3 data metallic model m) semiconducting μ (mA/ D I 0 CNTs 0 VDS (V) 0.4 physical layouts + full system + design targets Delay Noise immunity Energy Yield NanGate 15 nm Library OpenSparc T2 SoC + wire parasitics + wire parasitics … 22 Variation-Aware NDK: 2 Steps Step 1) Library characterization . Parasitic extraction . SPICE analysis using compact models Step 2) VLSI circuit EDP optimization a) Synthesis, place & route, power/timing b) Rapidly quantify variations 23 Variation-Aware NDK: 2 Steps Step 1) Library characterization . Parasitic extraction . SPICE analysis using compact models Step 2) VLSI circuit EDP optimization a) Synthesis, place & route, power/timing b) Rapidly quantify variations 24 Step 1) Library Characterization Required Inputs compact model module vscnfet_1_0_1(D,G,S); 25 NDK User Guide open Graphical User Interface (GUI) 1. Open SystemVariations GUI (run ‘SystemVariations’ from Matlab terminal) This is the “StepStruct”, it is a comma separated variable (.csv) file you can edit in libreoffice (or excel) NDK User Guide load configuration “StepStruct” Browse for example StepStruct file, which contains technology information such as gate length, contact length, gate oxide thickness, gate oxide dielectric constant, etc. The example one is for carbon nanotube field-effect transistors (CNFET), browse for: ‘$SVNROOT/cnfet_modeling/SystemVariations/SPICE_deck _gen/cnfet_macro/n07_cnt_pex_top_end_lg09_lc09_lx12_s 04_d17_r03_k10/VDD500mV/lvt/pex/BaseParameters.csv’, it will load all the fields into the GUI NDK User Guide run configuration “StepStruct” a) You can click “Run SPICE StepStruct” to run the circuit simulation (using Cadence spectremdl) associated with this StepStruct. The SystemVariations GUI generates a spectre netlist, runs it, and then loads & plots the output. This particular file will show the current- voltage (I-V) characteristics, the capacitance-voltage (C-V) characteristics, and some other key device-level parameters for CNFET b) Run single step c) It will take ~1 minute to run the simulation, you can see the spectre output in the Matlab command window NDK User Guide example FET characteristics: I-V, C-V Here are example I-V, C-V, and CNFET parameters ID vs. VDS ID vs. VGS ION & IEFF vs. VDD CGS vs. VGS CGS vs. VDD device parasitics: resistance & capacitance NDK User Guide other compact models wrapper model to hook into NDK compact model instantiation Step 1) Library Characterization Required Inputs compact model + physical layouts AOI222_X1 module vscnfet_1_0_1(D,G,S); module vscnfet_1_0_1(D,G,S); NanGate 15nm Library 31 NDK User Guide view in virtuoso Standard cell layout for AOI21_X1 in NanGate 15 nm library NDK User Guide .macro.lef file This is the .macro.lef file, it contains information on the locations of the wires in each standard cell, as well as standard cell area and pin locations NDK User Guide .tech.lef file You can open the input .lef files in a text editor: N7_3X2Y2Z_P42_mint.tech.lef and N7_3X2Y2Z_P42_mint.macro.lef This is the .tech.lef file, it contains information on the via pitch, width, spacing, height, as well as the metal layers (width, pitch, min spacing, etc.) NDK User Guide .itf file You can open the input .itf file from the text editor, it contains information about the resistance and capacitance of the wires and vias on each layer, as well as the inter-layer dielectrics (dielectric constant and spacing) example .itf specification NDK User Guide extracted netlist Example: AOI21_X1 (NanGate 15 nm OCL) extracted parasitics (R & C) from standard cell layouts FET instances (instantiating NDK wrapper) Step 1) Library Characterization Required Inputs compact model + physical layouts + variations metallic semiconducting CNTs AOI222_X1 module vscnfet_1_0_1(D,G,S); NanGate 15nm Library 37 NDK User Guide CNT variations parameters • Parameterize measured CNT spacing variations: 2 σspacing –––––––2 = 0.5 μspacing 0.1 CNTs 0.08 0.06 0.04 probability 0.02 0 0 0.2 0.4 0.6 0.8 1 inter-CNT spacing: s (µm) NDK User Guide variations: other compact models switch statement in Matlab based on compact model function call + processing: compact-model dependent (instructions on how to add new functions for new variations based on new compact models) Step 1) Library Characterization compact model physical layouts variations metallic semiconducting AOI222_X1 CNTs characterize timing/power libraries automatic SPICE deck generation & analysis 40 NDK User Guide generate Power/Timing configuration “StepStruct” a) Click “Generate NOMINAL Leakage/Cin/Timing StepStructs”, this will create a spectre simulation for many different standard library cells to characterize leakage current, input capacitance, timing, and power for the standard cell library b) For ‘Choose SPICE StepStruct file for cell type: comb’, select ‘template_LeakageCinTiming_Ioff_retarget.mdl’ NDK User Guide select variations parameters Choose the parameters for ‘Input for cnfet_macro’: NOMINAL: Number of Monte Carlo trials = 1, IDC = 0, pm = 0, pRs = 0, pRm = 1 VARIATIONS: trials = 100, IDC = 0.5, pm = 0.10, pRs = 1%, pRm = 99.99% NDK User Guide select load capacitance & input slew vectors Choose the default
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