3 ASIC INDUSTRY TRENDS

ASSPs AND ASICs

The term ASIC (Application Specific IC) has been a misnomer from the very beginning. ASICs, as now known in the IC industry, are really customer specific ICs. In other words, the gate array or standard cell device is specifically made for one customer. ASIC, if taken literally, would mean the device was created for one particular type of system (e.g., a disk-drive), even if this device is sold to numerous customers and/or is put in the IC manufacturer’s catalog.

Currently, a device type that is sold to more than one user, even if it is produced using ASIC tech- nology, is considered a standard IC or ASSP (Application Specific Standard Product). Thus, we are left with the following nomenclature guidelines (Figure 3-1).

ASIC: A device produced for only one customer. PLDs are included as ASICs because the customer “programs” that device for its needs only. CSIC: What ASICs should have been called from the beginning. Some companies differentiate an ASIC from a CSIC by who completes or is responsible for the majority of the IC design effort. If it is the IC producer, the part is labeled a CSIC, if it is the end-user, the device is called an ASIC. This term is not currently used very often in the IC industry. ASSP: A relatively new term for ICs targeting specific types of systems. In many cases the IC will be manufactured using ASIC technology (e.g., gate or linear array or standard cell techniques) but will ultimately be sold as a standard device type to numerous users (i.e., put into a product catolog). If the end-user helped the IC producer design the ASSP, that user is typically given a market leadtime (i.e., window of opportunity) to use the device before it is made available to its competitors. CSP: Customizable Standard Products are 70 to 90 percent standard with 10 to 30 percent of the chip available for user-specified logic, memory, or peripheral functions.

Source: ICE, "Status 1996" 19181A

Figure 3-1. ASIC Industry Terminology

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One problem many IC producers have run into while producing ASSPs is that in order to provide the optimum part, the IC producer must understand the system application at least as well as the end-user. Because this system-level expertise is not easy to acquire, most ASSP vendors have formed close relationships or partnerships with end-users. In this way, the IC vendor and end- user work closely together early in the system design cycle in order to properly define the ASSP device.

In general, as standard ICs take aim at ever finer segments of the marketplace, they ultimately evolve into ASSPs. In other words, at some point in time there could be very few standard ICs; most devices produced would be aimed at specific system needs. An example would be certain DRAMs architecturally optimized for a hand-held telecom system, laptop PC, or HDTV set. This is precisely the direction the IC industry is now heading.

Figure 3-2 shows some of the devices that National Semiconductor considers ASSPs. As IC pro- ducers customize their devices for specific system needs, the list of ICs labeled as ASSPs contin- ues to expand. In 1995, Sharp Corporation plans to release an ASSP product based upon the 33MHz ARM RISC 32-bit MPU core. The ARM ASSP will include a 480x320 monochrome LCD controller, 115-kbaud serial data infrared transceiver, write-back cache controller, on-board SRAM optimized for real-time interrupt, and pulse-width modulators. As was mentioned earlier, 20 years from now there may be few “standard” ICs produced.

• Mainframe connectivity solutions • FDDI devices • Local area network (LAN) ICs • Telecommunications products (e.g., CODECs) • Graphics ICs • Mass storage devices • Real-time clocks • DRAM management ICs • Floppy-disk devices • UARTs

Source: ICE, "Status 1996" 17776

Figure 3-2. Sampling of ASSPs from National Semiconductor

Although the 1995 ASIC market is estimated to have been $15.7 billion, the ASSP-type products (which are part of the special purpose MOS Logic category) are taking away some of its momen- tum (Figure 3-3). Overall, the ASIC market (not including full custom) is forecast to follow total IC industry growth rates fairly closely.

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8 7.63

7

28% 5.98 6

5 4.74 26%

4 3.75 26%

3 Billions of Dollars

2

1

0 1992 1993 1994 1995 (EST) Year Source: ICE, "Status 1996" 20204A

Figure 3-3. Special Purpose MOS Logic Market (1992-1995)

Does the proliferation of ASSPs and more customer-specific standard products mean an end to the ASIC market? No. This is because most of the pros and cons of ASICs versus ASSPs or standard products still exist.

The primary advantage of ASSPs or standard products is the ability to immediately (most of the time) purchase the ICs and get the system to market quickly. However, ASIC devices allow the system producer to differentiate its product from the competition. The result is that many times the system producer is able to gain marketshare and/or better profit margins.

In some cases standard products and ASICs are merging in an attempt to offer the benefits of both approaches. In 1993, TI announced that it was merging an enhanced version of its standard fixed- point TMS320C25 DSP chip and 15,000 usable and customizable 0.8-micron CMOS gate-array gates on one device. Thus, the user is able to take advantage of well characterized high-perfor- mance DSP circuitry while at the same time adding unique features to give its system a differen- tial advantage over its competitors. TI estimated that 30 percent of its total DSP IC sales in 1995 would be in customizable version form.* This percentage was expected to rise to 50 percent in 2000.

* Through 1995 TI’s belief in the success of its customizable DSP was well founded. TI’s big jump in gate array sales in 1994 and 1995 was greatly due to the success of its gate array DSP program.

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Another grey area is where Cirrus Logic takes one of its ASSP ICs and customizes a portion of it for one of its customers. Typically only about 5-10 percent of the new design is customized for the end-user. This “tweaked” device is still normally classified as an ASSP since the majority of the circuitry is still ASSP-based.

There is no question that the IC industry will continue to evolve toward devices that are specifi- cally suited for the customers’ needs. ICE believes that various versions of ASICs and ASSPs will co-exist to help serve those needs in the most economical and efficient manner possible.

ASIC Definitions

Some basic definitions and classifications are shown below in order to define what ICE means when using the various terms used to describe today’s ASIC devices. ASIC stands for Application Specific Integrated Circuit and according to ICE’s definition includes gate arrays, standard cells (sometimes called cell-based), full custom, and programmable logic devices (PLDs). These devices are classified as either semicustom, custom, or PLDs. Formal definitions are given in Figure 3-4.

I. Semicustom IC - A monolithic circuit that has one or more customized mask layers, but does not have all mask layers customized, and is sold to only one customer. Gate Array - A monolithic IC usually composed of columns and rows of transistors (organized in blocks of gates). One or more layers of metal interconnect are used to customize the chip. Sometimes called an uncommitted logic array (ULA). Linear Array - An array of transistors and resistors that performs the functions of several linear ICs and discrete devices. II. Custom IC - A monolithic circuit that is customized on all mask layers and is sold to only one customer. Standard Cell IC - A monolithic IC that is customized on all mask levels using a cell library that embodies pre-characterized circuit structures. ICs that are designed with a silicon compiler are included in this category. Most "embedded" arrays are included in this category. Full Custom IC - A monolithic IC that is at least partially "handcrafted". Handcrafting refers to custom layout and connection work that is accomplished without the aid of a silicon compiler or standard cells. Source: ICE, "Status 1996" 13660E

Figure 3-4. ASIC Definitions

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III. Programmable Logic Device (PLD) - A monolithic circuit with fuse, antifuse, or memory cell-based circuitry that may be programmed (customized), and in some cases, reprogrammed by the user (in- system or prototype form). Simple PLD (SPLD) - Usually a PAL or PLA, typically contains less than 750 logic gates. Complex PLD (CPLD) - A hierarchical arrangement of multiple PAL-like blocks. Field Programmable Gate Array (FPGA) - A PLD that offers fully flexible interconnects, fully flexible logic arrays, and requires functional placement and routing. Electrically Programmable Analog Circuit (EPAC) - A PLD that allows the user to program and reprogram basic analog functions.

Source: ICE, "Status 1996" 13660E

Figure 3-4. ASIC Definitions (continued)

ICE does not include ASSPs in its ASIC market figures. An example of an ASSP part that is not classified as an ASIC by ICE is Hitachi’s H8/300H Series of microcontrollers. Although the H8/300H user is able to customize this MCU using an extensive Hitachi cell library, the finished devices are almost always allowed to be sold to other Hitachi customers after a certain period of time (Motorola has a similar program using its 68HC05 MCUs).

In mid-1994, Motorola announced its FlexCore program that allows the end-user to use Motorola’s 32-bit MPUs as cores in cell-based designs. This program is significantly different from its, and Hitachi’s, MCU ASSP offerings in that the finished devices will most likely stay proprietary to the original customer. Thus, these devices are considered to be standard cell ASICs.

The FlexCore-type ASIC program* is a prime example why ASSPs will not eliminate the market for ASICs. As was mentioned earlier, ASSPs will still hold an advantage in time-to-market, but they will never be able to compete with the product differentiation capability of robust ASIC offer- ings such as FlexCore.

Another ASIC segment that needs additional clarification and discussion is the PLD category. ICE includes under the generic term PLD the simple bipolar fuse-programmable PAL devices (e.g., the 22V10) produced by AMD, TI, and National, the complex programmable (CPLD) devices (that typically have configurable macrocells, multiple feedback paths, etc.) that are usually MOS mem- ory cell-based, and what are called field programmable gate arrays (FPGAs). Figure 3-5 compares the architectures of a typical CPLD and a typical FPGA.

* Zilog has a similar program for its Z80 MCU devices.

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SPLD SPLD Block Block

Global Bus

SPLD SPLD Block Block

CPLD

Interconnect

Logic Block

I/O Cell

FPGA

Source: CICC 1995/ICE, "Status 1996" 20205

Figure 3-5. CPLD Versus FPGA Structures

The FPGAs are produced using MOS memory cell (and thus are usually reprogrammable) or anti- fuse technology. The physical (e.g., line lengths) and electrical characteristics of the interconnects are unknown before programming, just like a gate array.

As was shown, the PLD classification now encompasses a broad range of products and most peo- ple in the IC industry are aware that the term PLD is no longer synonymous with the nearly obso- lete bipolar fuse-programmable PAL.

Another definitional clarification that should be mentioned is in the standard cell category. Many of the standard cell designs produced in the ASIC industry use a combination of pre-characterized and “handcrafted” circuit structures. ICE categorizes an ASIC that has 50 percent or more of its circuitry composed of cells as a standard cell IC. If less than 50 percent of the circuitry is from pre- characterized cells (with the majority of the design being handcrafted), the IC is considered a full custom ASIC.

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Another device that deserves some further discussion is the embedded array ASIC. When design- ing with this device, the customer first identifies any megacell functions that will be needed. The ASIC producer optimizes the layout of the cell-based design and then begins producing base wafers. While the base wafers are being fabricated, the customer is finishing design work for the uncommitted random logic area (gate array portion) that was set aside in the initial design. After the base wafer is finished being processed, the gate array area of the base wafer is metallized.

The ultimate goal of the parallel random logic design and cell-based wafer fabrication efforts of the embedded array program is to shorten the turnaround time encountered with standard cell devices. Many embedded array producers are achieving turnaround times very close to those of gate arrays.

Although both standard cell and gate array design and fabrication techniques are used on the embedded array, because all of the mask layers of the device are customized for the user, ICE will classify the embedded array ASICs (e.g., VLSI Technology’s Flex-Arrays) as standard cells.

Throughout “Status 1996” ICE uses AVAILABLE, TOTAL OR RAW GATES terms such as available, total, raw, The number of unconnected gates on a device. and usable when referring to gate USABLE GATES densities. Figure 3-6 shows the def- The number of gates that can typically be interconnected implementing an "average" design. Usable gate count will initions followed by ICE in regard to always be less than the number of available, total, or raw gates. gate count. Typical usable gate Source: ICE, "Status 1996" 16779 counts for various ASICs are shown in Figure 3-7. Figure 3-6. Gate Count Definitions

ASIC Type Usable Gate Percentage

Double-Level Metal MOS PLD 30 - 50

Triple-Level Metal MOS PLD 60 - 70

Double-Level Metal Channelled Gate Array 85 - 95

Double-Level Metal Channelless Gate Array 40 - 50

Triple-Level Metal Channelless Gate Array 60 - 70

Five-Layer Metal Channelless Gate Array 75 - 85

Standard Cell 85 - 95

Full Custom 100

Source: ICE, "Status 1996" 16780B

Figure 3-7. Sampling of Usable Gate Counts

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As total gate densities have increased, the IC manufacturer has had to go to a greater number of interconnect levels (i.e., metal layers) to keep die size and usable gate counts manageable. This has been especially evident with the new triple-level metal PLDs. As will be discussed, the new PLD technologies are helping reduce PLD die size dramatically, and in turn, significantly reduce manufacturing costs.

Of course the move to a greater number of metal layers comes with cost and complexity problems. With an increasing number of ASIC designs being pad limited (i.e., the die size is dictated by the number of I/O pads rather than the logic gate area) the move to more layers of metal has pro- ceeded very slowly in the ASIC user base.

ASIC Product Lifecycle

Figure 3-8 shows the 1995 location of each of the major ASIC families on the product lifecycle curve. It is interesting to note that most of the classifications still reside on the growth side of the curve. As the ASIC market matures, the majority of the ASIC product types will be in or approaching the maturity stage of their lifecycles in the late 1990’s.

Low density (i.e., less than 10,000 gates) gate arrays are considered to be in the saturation/decline stage. In 1995, many gate array vendors were shying away from accepting designs for low gate count arrays. As veteran IC buyers know, once products enter the latter stages of the lifecycle, price becomes a secondary concern to availability. Likewise, slow bipolar TTL PALs are quickly losing marketshare and are now in the decline stage. As shown, replacement products for the slow bipolar TTL PAL and low density gate array, such as MOS PLDs, are currently in the intro- duction or growth/maturity stage.

THE LOGIC MARKET

An analysis of the logic market provides a good background to the study of the ASIC market since a vast majority of ASIC products perform some basic logic function within a system. Approximately 20 percent of 1994 and 1995 worldwide IC output was for some form of logic device.

Figure 3-9 shows the logic trends by technology. The most obvious trend shown on the graph is the tremendous growth of CMOS logic. In eight years (1987-1995), CMOS technology grew from 55 percent of the logic market to 85 percent. On the other hand, older technologies such as NMOS and bipolar are quickly being phased out. ECL technology, after maintaining about eight percent of the logic marketshare for several years, declined to around three percent in 1995 and is forecast to drop to a smaller marketshare percentage through the year 2000. Many of the better perfor- mance characteristics of ECL and other older technologies have been replicated in CMOS and BiCMOS technologies in recent years. These two technologies will dominate not only the logic market (98 percent in the year 2000), but all digital IC production in the foreseeable future.

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Introduction Growth Maturity Saturation Decline and Obsolescence

4.5ns TTL PLD ECL PLD 5ns TTL PLD 7ns TTL PLD EPLD >10ns TTL PLD EPAC 10ns TTL PLD EEPLD Flash-PLD SRAM-PLD Antifuse PLD Full CMOS Gate Array CMOS Gate Array Custom (≥500,000 Gates) (≥100,000 and <500,000 Gates) CMOS Gate Array (≥20,000 and <100,000 Gates) Mixed CMOS Gate Array Analog/Digital (≥10,000 and <20,000 Standard Cell Gates) Digital CMOS Gate Array Standard Cell (<10,000 Gates) ECL Gate Array (≥20,000 Gates) ECL Gate Array (≥5,000 and <20,000 Gates) GaAs Gate Array ECL Gate Array BiCMOS Analog (<5,000 Gates) Gate Array Arrays GaAs Standard Cell Mixed Analog Digital Arrays

Source: ICE, "Status 1996" 11642Q

Figure 3-8. 1995 ASIC Products Lifecycle

Displayed in Figure 3-10 are the average selling prices (ASPs) for logic devices during the past 12 years. The TTL SSI/MSI segment of logic devices has remained essentially flat since the mid- 1980’s. Meanwhile, MOS logic ASPs increased in the late 1980’s, stayed flat for several years, then took off in 1994 and 1995 due to greater sophistication and implementation of ASIC logic products in systems. Overall ASPs for logic devices pretty much mirrored what took place with the MOS logic segment.

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100

90 23%

80

55% 70 18%

CMOS 60 NMOS 82% 85% 8% 93%* 50 ECL 51% 40 10%

30 8% 4% Percent of Total Logic Market <1% TTL and Other Bipolar 4% 27% 20

5% 10 BiCMOS <1% 4% 10% 8% 3% 0 2% 1982 1987 1995 2000 $3.3B $11.6B $24.5B $50.0B 1994 $19.7B *Includes 1% for GaAs Source: ICE, "Status 1996" 12875N

Figure 3-9. Logic Market Trends

2.00

1.80 TTL SSI/MSI MOS Logic 1.60 Total Logic

1.40

1.20

1.00 ASP ($)

0.80

0.60

0.40

0.20

0.00 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 (EST) Year

Source: WSTS/ICE, "Status 1996" 20197A

Figure 3-10. Average Selling Price for Logic Devices

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ASIC MARKET FORECAST

ICE segments the ASIC market into three areas—semicustom (MOS and bipolar gate arrays and linear arrays), custom (cell-based and full custom), and programmable logic devices (including FPGAs). A detailed look at the five-year history (1991-1995) of these segments is given in Figure 3-11. Semicustom, custom, and PLD ASIC marketshares remained about the same through the first half of the decade. However, there was more movement of product marketshares within each segment during the time period (e.g., standard cell and full custom in the “total custom” segment swapped places).

1992/1991 1993/1992 1994/1993 1995/1994 1991 1992 1993 1994 1995 1991-1995 Segment Percent Percent Percent Percent ($M) ($M) ($M) ($M) ($M) CAGR (%) Change Change Change Change MOS Gate Arrays 2,845 2% 2,915 22% 3,555 24% 4,410 22% 5,395 17% Bipolar Gate Arrays 1,000 –10% 905 –13% 790 –19% 640 14% 730 –8% Total Gate Arrays 3,845 –1% 3,820 14% 4,345 16% 5,050 21% 6,125 12% Linear Arrays 165 12% 185 11% 205 7% 220 7% 235 9% Total Semicustom 4,010 0% 4,005 14% 4,550 16% 5,270 21% 6,360 12% MOS Standard Cell 2,065 10% 2,280 20% 2,745 33% 3,660 28% 4,700 23% Bipolar Standard Cell 55 18% 65 15% 75 20% 90 –22% 70 6% Total Standard Cell 2,120 11% 2,345 20% 2,820 33% 3,750 27% 4,770 22% Full Custom 2,625 1% 2,650 2% 2,700 1% 2,725 1% 2,750 1% Total Custom 4,745 5% 4,995 11% 5,520 17% 6,475 16% 7,520 12% Bipolar PLDs 335 –16% 280 –18% 230 –33% 155 –23% 120 –23% Simple MOS PLDs 310 0% 310 27% 395 –9% 360 6% 380 5% Complex MOS PLDs 90 44% 130 69% 220 36% 300 77% 530 56% FPGAs 170 32% 225 53% 345 33% 460 63% 750 45% Total MOS PLDs 570 17% 665 44% 960 17% 1,120 48% 1,660 31% Total PLDs 905 4% 945 26% 1,190 7% 1,275 40% 1,780 18% Total ASIC 9,660 3% 9,945 13% 11,260 16% 13,020 20% 15,660 13%

Source: ICE, "Status 1996" 20198A

Figure 3-11. 1991-1995 ASIC Market

Figure 3-12 shows ICE’s forecast of the ASIC market through the balance of the decade. ICE believes the overall 1995 ASIC market grew 20 percent. The catalyst for future ASIC growth will be strong MOS PLD and MOS standard cell sales.

The MOS PLD market is made up of simple and complex PLDs and FPGAs. It is one segment that is dominated more and more by high-speed performance and low cost-per-gate attributes. Whether EPROM- or EEPROM-based PLDs, or newer antifuse or flash-based PLDs, many strides have been taken to advance the PLD market. Whether in the field or at a manufacturer’s site, pro- gramming a logic device for a specific user application has become a popular way to customize a product.

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1996/1995 1997/1996 1998/1997 1999/1998 2000/1999 1996 1997 1998 1999 2000 1991-2000 1995-2000 Segment Percent Percent Percent Percent Percent ($M) ($M) ($M) ($M) ($M) CAGR (%) CAGR (%) Change Change Change Change Change MOS Gate Arrays 15% 6,200 13% 7,000 15% 8,050 17% 9,400 18% 11,100 16% 16% Bipolar Gate Arrays –18% 600 –25% 450 –24% 340 –26% 250 –26% 185 –17% –24% Total Gate Arrays 11% 6,800 10% 7,450 13% 8,390 15% 9,650 17% 11,285 13% 13% Linear Arrays 2% 240 2% 245 4% 255 4% 265 4% 275 6% 3% Total Semicustom 11% 7,040 9% 7,695 12% 8,645 15% 9,915 17% 11,560 12% 13% MOS Standard Cell 21% 5,700 17% 6,650 23% 8,180 23% 10,050 25% 12,550 22% 22% Bipolar Standard Cell 7% 75 7% 80 6% 85 6% 90 11% 100 7% 7% Total Standard Cell 21% 5,775 17% 6,730 23% 8,265 23% 10,140 25% 12,650 22% 22% Full Custom 2% 2,800 2% 2,850 2% 2,900 2% 2,950 2% 3,000 1% 2% Total Custom 14% 8,575 12% 9,580 17% 11,165 17% 13,090 20% 15,650 14% 16% Bipolar PLDs –25% 90 –22% 70 –14% 60 –17% 50 –20% 40 –21% –20% Simple MOS PLDs –5% 360 –3% 350 –4% 335 –4% 320 –6% 300 0% –5% Complex MOS PLDs 27% 675 23% 830 28% 1,060 29% 1,365 30% 1,775 39% 27% FPGAs 21% 905 19% 1,075 27% 1,365 28% 1,750 30% 2,275 33% 25% Total MOS PLDs 17% 1,940 16% 2,255 22% 2,760 24% 3,435 27% 4,350 25% 21% Total PLDs 14% 2,030 15% 2,325 21% 2,820 24% 3,485 26% 4,390 19% 20% Total ASIC 13% 17,645 11% 19,600 15% 22,630 17% 26,490 19% 31,600 14% 15%

Source: ICE, "Status 1996" 20199A

Figure 3-12. 1996-2000 ASIC Market Forecast

The future of the total custom segment (specifically, the standard cell market) also appears bright in ICE’s ASIC forecast. ICE anticipates the standard cell market more than doubling from an esti- mated $4.8 billion in 1995 to approximately $12.7 billion in the year 2000. In fact, ICE forecasts that the MOS standard cell market will be the largest ASIC product category (surpassing MOS gate arrays) beginning in 1998.

With few exceptions, growth in most product areas appears promising through the year 2000. However, if the word “bipolar” is associated with a category, it spells doom. The mainstream IC market has moved away from bipolar-based products toward MOS-based technology. As a result, bipolar gate arrays and bipolar PLDs are forecast to be the poorest performing of all ASIC seg- ments.

Despite the ASIC market forecast calling for sustained growth, the ASIC market will represent only nine percent of the total worldwide IC market in the year 2000. This will be down from 12 percent of the IC market in 1995 and 21 percent of the IC market in 1991.

Perhaps a better way of determining the performance of the ASIC market is to view cumulative annual growth rates (CAGRs, Figure 3-13). Here, the “hot” markets such as complex PLDs, FPGAs, MOS standard cells, and MOS gate arrays are exposed. At the same time, the demise of bipolar ASICs is evident as well. The total ASIC market is forecast to grow at a healthy 15 percent CAGR through the end of the decade, with four categories equaling or bettering that performance and six categories not growing at the same rate as the overall market.

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1991-2000 1991-1995 1995-2000 Product CAGR (%) CAGR (%) CAGR (%)

Complex PLDs 39 56 27 FPGAs 33 45 25 MOS Standard Cell 22 23 22 MOS Gate Arrays 16 17 16 Total ASIC 14 13 15 Bipolar Standard Cell 7 6 7 Linear Arrays 6 9 3 Full Custom 1 1 2 Simple PLDs — 5 –5 Bipolar PLDs –21 –23 –20 Bipolar Gate Arrays Ð17 Ð8 Ð24

Source: ICE, "Status 1996" 20195A

Figure 3-13. ASIC Product CAGRs

At one time (1986) full custom products accounted for more than half of ASIC marketshare. Now, though this segment is growing ever so slightly in terms of dollars, it is being replaced by devices such as standard cells. Full custom ASICs are forecast to represent only nine percent of total ASIC product marketshare in the year 2000 (Figure 3-14). Supercomputer manufacturers and the mili- tary are the best examples of full custom users. Since overall military spending is down and with supercomputer power in desktop systems, it stands to reason that there will be less demand for full custom devices. Meanwhile, standard cell devices, which held 31 percent ASIC marketshare in 1995, are forecast to account for 40 percent in the year 2000.

PLDs PLDs* 7% Gate and 11% Linear Arrays Full Custom Gate and 1986 30% 17% 1995 Linear Arrays $4.7B $15.7B 41% Full Custom 52% Standard Standard Cell Cell 31% 11%

Full Custom 9%

PLDs* Standard Cell 14% 2000 40% $31.6B Gate and Linear Arrays 37%

*FPGAs 5% in 1995, 7% in 2000. Source: ICE, "Status 1996" 16278J

Figure 3-14. ASIC Product Marketshare

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As touched upon earlier, the market forecast for MOS standard cell and gate array devices appears promising, but other older technologies are forecast to continue their trek toward obsolescence. In Figure 3-15, forecasts for several logic technologies are shown—and most are in a steady decline. The graphs point out that most designers (and users) have made the switch to MOS technologies to achieve the desired effects of their ASIC devices. Of the non-MOS segments, only TTL/Other Logic still shows some signs of life. This mainstream technology of a few years ago was used in numerous applications and remained a rather large market even in 1995. Due to its sheer size and relatively widespread use, this market segment will be the slowest to decline.

1,000 2000 1000 905 1,730 Ð10% 1,630 1,620 790 1,505 800 1500 1,455 Ð6% Ð13% 730 Ð1% 640 Ð3% 19% Ð19% 600 14% 1000 400 500 Millions of Dollars

Millions of Dollars 200

0 0 1991 1992 1993 1994 1995 1991 1992 1993 1994 1995 (EST) (EST) Year Year TTL/Other Standard Logic Market Bipolar Gate Array Market

500 400 500 335 400 Ð22% 390 300 280 Ð16% 315 230 Ð19% Ð18% 300 200 155 Ð36% 200 Ð33% 200 120 150 Ð25% 100 Ð23% Millions of Dollars

Millions of Dollars 100

0 0 1991 1992 1993 1994 1995 1991 1992 1993 1994 1995 (EST) (EST) Year Year Bipolar PLD Market NMOS Logic Market

6000 5,000 4,700 5,395 5000 4,410 4,000 3,660 22% 28% 4000 3,555 3,000 2,745 2,915 24% 3000 2,845 2,280 33% 22% 2,065 2% 20% 2,000 10% 2000

Millions of Dollars 1000 Millions of Dollars 1,000

0 0 1991 1992 1993 1994 1995 1991 1992 1993 1994 1995 (EST) (EST) Year Year MOS* Gate Array Market MOS* Standard Cell Market *Includes BiCMOS and GaAs Source: ICE, "Status 1996" 18928D

Figure 3-15. Selected 1991-1995 Logic Markets

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Quarterly market size for each of the four main ASIC products is shown in the next several charts. In Figure 3-16, the MOS gate array market is shown as a gradually upward sloping curve. Recent history shows this market performing best during the second and third quarters of each year.

1,300

1,200

1,100

1,000

900

800

Dollars (Millions) 700

600

500

400 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q (EST) 1989 1990 1991 1992 1993 1994 1995 Year Source: WSTS/ICE, "Status 1996" 17778J

Figure 3-16. Quarterly MOS Gate Array Market (1989-1995)

The MOS standard cell market is shown on a quarterly basis in Figure 3-17. Much more dramat- ic growth characterized this segment during the past few years. Besides being used in more wide- spread applications, the sizable market increase for standard cells might be explained in the fact that many companies re-classified their full custom devices as standard cell products in 1994 and 1995.

Figure 3-18 portrays the rise in quarterly MOS PLD sales dating back to 1989. For the time peri- od shown, this market steadily increased. At least it did so until severe pricing pressures kept the market size flat from 3Q93 through 2Q94. New product offerings from several suppliers helped revive the MOS PLD market in late 1994 and throughout 1995.

Meanwhile, the theme for bipolar ASIC devices—in this case, for bipolar PLDs—is repeated in Figure 3-19. Since 1989, the bipolar PLD market has dropped steeply. This market shows a ten- dency to rebound slightly every once in a while, but overall, the trend is still down.

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950

850

750

650

550 Dollars (Millions) 450

350

250 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q (EST) 1992 1993 1994 1995

Source: WSTS/ICE, "Status 1996" Year 18930E

Figure 3-17. Quarterly MOS Standard Cell Market (1992-1995)

500

450

400

350

300

250

200 Dollars (Millions)

150

100

50

0 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q (EST) 1989 1990 1991 1992 1993 1994 1995 Year

Source: WSTS/ICE, "Status 1996" 18929E

Figure 3-18. Quarterly MOS PLD Market (1989-1995)

3-16 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Industry Trends

130

120

110

100

90

80

70

60 Dollars (Millions) 50

40

30

20 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q 1Q 2Q 3Q 4Q (EST) 1989 1990 1991 1992 1993 1994 1995 Year Source: WSTS/ICE, "Status 1996" 17777K

Figure 3-19. Quarterly Bipolar PLD Market (1989-1995)

TOP TEN ASIC VENDOR SALES

Before listing any ASIC vendor sales, it should be noted that the ICE ASIC sales estimates do not include standard products designed from standard cell libraries or with silicon compilers. Only gate and linear arrays, full custom, and standard cell devices not listed in a catalog, as well as PLDs, are considered ASICs.

Figure 3-20 provides a list of the top 10 ASIC (not including full custom) suppliers for 1995. With total ASIC sales of $1.27 billion, NEC held on to the top spot on the leading ASIC supplier list in 1995. NEC posted strong gate and linear array sales, but also made an effort to strengthen its stan- dard cell sales as well. In doing so, it captured just under 10 percent of the total ASIC market.

ICE estimates that LSI Logic moved ahead of Fujitsu into the number two spot in the 1995 ASIC ranking. LSI Logic’s standard cell ASIC sales have increased from $105 million in 1993 to an esti- mated $555 million in 1995. It would not be surprising to see LSI Logic overtake NEC as the worldwide leading ASIC vendor in 1996!

A newcomer to the top ten ASIC ranking in 1995 is Xilinx*, the longtime leader in the FPGA mar- ketplace. ICE believes that Xilinx has a chance of passing Hitachi in ASIC sales in 1996.

* Longtime ASIC top ten vendor VLSI Technology slipped out of the top ten ranking in 1995 with $440 million in ASIC sales.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-17 ASIC Industry Trends

Total Gate And Standard Percent Of 1995 PLD** Sales Company ASIC Sales Linear Array Cell Sales Total ASIC Rank ($M) ($M) Sales ($M) ($M) Market 1 NEC 1,265 925 340 — 10% 2 LSI Logic 1,170 615 555 — 9% 3 Fujitsu 1,165 940 225 — 9% 4 Toshiba 870 635 235 — 7% 5 TI 843 490 315 38 7% 6 AT&T 831 94 655 82 6% 7 Hitachi 575 500 75 — 4% 8 Xilinx 530 — — 530 4% 9 Motorola 490 355 125 10 4% 10 Symbios 445 35 410 — 3% Top Ten Total 8,184 4,589 2,935 660 63% Other Suppliers 4,726 1,771 1,835 1,120 37% Total Market 12,910 6,360 4,770 1,780 100% Top Ten 63% 73% 61% 37% 63% Marketshare *Not including full custom **Includes FPGA Sales Source: ICE, "Status 1996" 20194A

Figure 3-20. 1995 Top Ten ASIC Leaders

Also in the top 10 list is Symbios Logic, Inc. Symbios is the former NCR facility in Colorado that was purchased (and renamed) by Hyundai. In purchasing the NCR ASIC business, Symbios (Hyundai) became an immediate contender in the worldwide ASIC market.

GATE AND LINEAR ARRAY SUPPLIERS

Displayed in Figure 3-21 are the top gate array manufacturers and their sales for 1994 and 1995. Four companies, Fujitsu, NEC, Toshiba, and LSI Logic, accounted for about 50 percent of all gate array sales in 1995. The top ten gate array suppliers accounted for 80 percent of sales. In the case of the top four players, each has been a steady player in the gate array business for many years. A new entry into the top ten gate array ranking in 1995 was IBM. The figures listed for IBM are only its merchant sales and do not include internal transfers.

At the number six position in 1995 was TI. It reported an increase in gate array sales of 46 percent during the year. This large increase was partly due to it providing customizable DSP devices. TI will build a device that features its DSP core surrounded by gate array technology. While this can be labeled as either a DSP or an ASIC, ICE classifies the product as an ASIC device.

Of the 35 companies listed in the gate array supplier chart, eight posted flat or declining revenue in 1995. Some, such as Raytheon were phasing out of the bipolar gate array business. Meanwhile, Siemens was phasing out of the MOS gate array market.

3-18 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Industry Trends

1995/1994 1995 1995 1994 Sales ($M) 1995 Sales ($M, EST) Company Percent Percent Rank MOS Bipolar Total MOS Bipolar Total Change Marketshare 1 Fujitsu 550 250 800 645 295 940 18 15.3 2 NEC 685 50 735 830 65 895 22 14.6 3 Toshiba 525 — 525 635 — 635 21 10.4 4 LSI Logic 575 — 575 615 — 615 7 10.0 5 Hitachi 305 115 420 360 140 500 19 8.2 6 TI 335 — 335 490 — 490 46 8.0 7 Motorola 182 125 307 200 155 355 16 5.8 8 IBM 80 — 80 160 — 160 100 2.6 9 Mitsubishi 139 — 139 155 — 155 12 2.5 10 Samsung 90 — 90 155 — 155 72 2.5 11 VLSI Technology 108 — 108 130 — 130 20 2.1 12 GEC Plessey 93 8 101 121 — 121 20 2.0 13 S-MOS/Seiko 75 — 75 105 — 105 40 1.7 14 Oki 78 — 78 87 — 87 12 1.4 15 SGS-Thomson 80 — 80 83 — 83 4 1.4 16 AMI 38 — 38 61 — 61 61 1.0 17 AT&T 50 10 60 50 10 60 — 1.0 18 Matsushita 44 — 44 53 — 53 20 0.9 19 National 39 — 39 42 — 42 8 0.7 20 ROHM 36 — 36 40 — 40 11 0.7 21 AMCC 12 28 40 14 25 39 –3 0.6 22 Symbios 32 — 32 35 — 35 9 0.6 23 Sanyo 28 — 28 31 — 31 11 0.5 24 Sharp 30 — 30 30 — 30 — 0.5 25 Atmel 6 — 6 30 — 30 400 0.5 26 Siemens* 5 25 30 3 25 28 –7 0.5 27 Vitesse** 25 — 25 27 — 27 8 0.4 28 Orbit 12 — 12 27 — 27 125 0.4 29 MHS 22 — 22 26 — 26 18 0.4 30 Ricoh 19 — 19 21 — 21 11 0.3 31 Sony*** 15 5 20 20 — 20 — 0.3 32 Chip Express 10 — 10 20 — 20 100 0.3 33 Kawasaki Steel 10 — 10 15 — 15 50 0.2 34 LG Semicon 10 — 10 10 — 10 — 0.2 35 Raytheon*** — 15 15 — 5 5 –67 0.1 Others 67 9 76 69 10 79 4 1.2 Total 4,410 640 5,050 5,395 730 6,125 21 100.0 *Phasing out CMOS gate arrays **GaAs ***Phasing out bipolar gate arrays Source: ICE, "Status 1996" 13636P

Figure 3-21. Merchant Gate Array Leaders

Gate arrays have found their way into more small, electronic sets with advanced functions. Speed and low power, two of the most preferred performance characteristics in ICs, are especially desired in gate arrays. Manufacturers have been quick to respond to these needs while adding density as well. Typically, 0.8-micron technology is used to manufacture the majority of gate arrays. However, companies have pushed the process technology envelope to 0.5 micron and smaller for the more-than-one-million-gate gate arrays that have been built in limited quantities. Some research prototype gate arrays have been built using 0.2-micron technology.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-19 ASIC Industry Trends

It seems gate array implementation has grown as the average number of gates per device has increased. As recently as five years ago, average gate array density was in the 10,000-gate range. In 1995, ICE estimates that 90 percent of all gate arrays were shipped with greater than 10,000 gates. More specifically, ICE believes that 40 percent of gate arrays were shipped with between 20,000 and 50,000 gates in 1995 (Figure 3-22). By the year 2000, ICE anticipates the majority of gate arrays will have an average usable gate count closer to 100,000 gates.

≤10K Gates 10% 10K - 20K Gates >50K Gates 1995 30% 20% $5.4B 20K - 50K Gates 40%

Source: ICE, "Status 1996" 18931D

Figure 3-22. 1995 MOS Gate Array Market by Gate Count (Usable)

Placing large numbers of gates on a gate array has not been an insurmountable hurdle. Many companies have developed gate arrays with over one million available gates. At these densities, it becomes increasingly possible to incorporate large-scale circuitry in a single chip. Circuit den- sity and manufacturing have brought gate arrays to a higher level of acceptance and integration. The biggest challenges facing designers of these “mega” gate arrays are test and packaging issues.

The gate array market by region is shown in Figure 3-23. In 1995, the increased value of the yen helped Japan become the largest market for gate arrays. Japan had a 35 percent share of the MOS gate array market in 1994 (estimated at 40 percent in 1995), while the North American market was 39 percent in 1994 (estimated at 36 percent in 1995).

In the year 2000, ICE expects the North American and Japanese markets to remain the largest for gate array products. Pacific Rim countries, excluding Japan but including Korea, Taiwan, and oth- ers, will garner an increasing percentage of marketshare.

The trend toward MOS technology (CMOS and BiCMOS) will continue in the gate array market (Figure 3-24). In some cases, designers and manufacturers will take advantage of the low power consumption and high speed characteristics of BiCMOS technology in the coming five years. However, CMOS technology continues to be refined to the point where it can perform at a level approaching BiCMOS. Therefore, it will continue to expand as the preferred technology when building gate arrays.

3-20 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Industry Trends

ROW ROW 1% 2%

Europe North Europe North 10% America 9% America 18% 23% 1995 2000

Japan Japan 65% 72%

Total Bipolar Market = $730M Total Bipolar Market = $185M

ROW Europe ROW Europe 10% 14% 12% 15% North 1995 North 2000 America Japan America 36% 40% 35% Japan 38%

Total MOS Market = $5.4B Total MOS Market = $11.1B

ROW Europe ROW Europe 9% 14% 12% 15% North 1995 North 2000 America America Japan 34% Japan 34% 43% 39%

Total Market = $6.1B Total Market = $11.3B

Source: ICE, "Status 1996" 8881X

Figure 3-23. Worldwide Digital Gate Array Market by Region

BiCMOS Bipolar GaAs 8% 2% 2% BiCMOS 9% Bipolar 12%

1995 2000

CMOS* CMOS 80% 87%

Total Market = $6.1B Total Market = $11.3B *Includes GaAs Source: ICE, "Status 1996" 8870Z

Figure 3-24. Digital Gate Array Market by Process Technology

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-21 ASIC Industry Trends

In contrast, bipolar’s share of the gate array market is forecast to slide from 12 percent in 1995 to two percent in the year 2000. This steep drop is due to the slumping military IC market as well as the replacement of ECL arrays in large-scale computing systems with GaAs, BiCMOS, and CMOS ICs.

The worldwide gate array market by end use is segmented in five categories and shown in Figure 3-25. Data processing applications are where most gate arrays were destined in 1995. By the year 2000, the picture will not change much. Data processing and telecom applications will expand slightly, while other applications decline. The military segment will be a smaller player despite the fact the Defense Department is very encouraged about further incorporating gate arrays into its systems.

Telecom Telecom 19% 21% Data Data Industrial Processing 1995 Processing 2000 Industrial 13% 55% 58% 11%

Consumer Consumer 10% 9% Military Military 3% 1%

Total Market = $6.1B Total Market = $11.3B Source: ICE, "Status 1996" 9933T

Figure 3-25. Gate Array Market by Application

Linear arrays put the functions of several analog ICs and discrete products onto a single chip. Most linear arrays consist of bipolar transistors and resistors, but can also include capacitors, junc- tion field-effect transistors, and Schottky diodes.

Linear arrays have had a difficult time gaining significant market acceptance. One reason for this is design difficulties. Other concerns include noise isolation, isolating the substrate, interfacing the chip with external circuitry, and keeping NRE costs and schedules short. Also, the lack of stan- dardized test methods has traditionally been a stumbling block for linear ASICs.

The leading linear array manufacturers and their sales are provided in Figure 3-26. For the sec- ond straight year sales of linear arrays increased only seven percent. The “other” category showed a steep decline due to Micro Linear and Raytheon phasing out their analog array busi- nesses.

3-22 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Industry Trends

1993 1994 1995 1995/1994 1995 1995 Company Sales Sales Sales Percent Percent Rank ($M) ($M) ($M, EST) Change Marketshare

1 Maxim 32 38 42 11 18 2 SGS-Thomson 30 35 38 9 16 3 AT&T 22 26 34 31 14 4 NEC 20 25 30 20 13 5 GEC Plessey 22 18 20 11 9 6 Ricoh 12 15 17 13 7 7 Universal 11 12 13 8 6 8 Gennum 7 10 12 20 5 9 Exar 8 9 10 11 4 10 Cherry 7 8 9 13 4 — Others 34 24 10 –58 4 — Total 205 220 235 7 100 Source: ICE, "Status 1996" 13649Q

Figure 3-26. Linear Array Leaders

STANDARD CELL SUPPLIERS

Leading standard cell ASIC manufacturers and their 1994 and 1995 sales numbers are shown in Figure 3-27. AT&T and LSI Logic were the only companies that posted more than 10 percent mar- ketshare in 1995. It should be noted that, being a former “captive” supplier, AT&T did a lot of internal business. The internal business represented approximately 30 percent of its total standard cell sales in 1995.

LSI Logic moved from sixth place in 1994 to second place in 1995! Given LSI’s recent standard cell sales surge, it is likely to capture the number one ranking in 1996.

Similar to the gate array ranking, IBM’s standard cell figures only include its merchant sales. ICE expects that IBM will break into the top ten standard cell sales ranking in 1997.

Five companies among the 38 listed increased sales by triple-digit amounts in 1995. Among them was LSI Logic, which saw its standard cell business increase 124 percent. LSI Logic took several steps to improve its product line, including its first move into the mixed-signal arena. Its first mixed-signal standard cells focus on data-conversion cells, but will be expanded over time to include a wide range of functions. LSI claims an advantage in the mixed-signal market because it manufactures its devices using a digital CMOS process designed to keep costs down.

Motorola increased its cell-based ASIC sales 116 percent in 1995, mostly by using its FlexCore pro- gram to grow its standard cell business. FlexCore combines a standard product with functions desired by a user to create a quasi-application-specific chip. FlexCore takes Motorola’s 68000-fam-

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-23 ASIC Industry Trends

ily core processor and allows a designer to integrate desired features such as up to 100,000 gates of custom logic, memory, and peripheral modules. It is a feature that is very attractive and very well understood by the design community. Customers get what looks like an ASIC device, but uses industry-standard third-party design tools. The bottom line for Motorola was a very nice gain in standard cell sales.

1995/1994 1995 1995 1994 Sales ($M) 1995 Sales ($M, EST) Company Percent Percent Rank MOS Bipolar Total MOS Bipolar Total Change Marketshare 1 AT&T 600 — 600 655 — 655 9 13.7 2 LSI Logic 248 — 248 555 — 555 124 11.6 3 Symbios 322 — 322 410 — 410 27 8.6 4 NEC 260 — 260 340 — 340 31 7.1 5 TI 345 — 345 315 — 315 –9 6.6 6 VLSI Technology 262 — 262 310 — 310 18 6.5 7 Toshiba 173 — 173 235 — 235 36 4.9 8 Fujitsu 180 5 185 220 5 225 22 4.7 9 Alcatel Mietec 159 — 159 166 — 166 4 3.5 10 Motorola 58 — 58 125 — 125 116 2.6 11 SGS-Thomson 64 — 64 100 — 100 56 2.1 12 IBM 40 — 40 100 — 100 150 2.1 13 Matsushita 68 — 68 98 — 98 44 2.1 14 AMS 75 — 75 97 — 97 29 2.0 15 Exar 74 — 74 95 — 95 28 2.0 16 GEC Plessey 75 65 140 45 35 80 –43 1.7 17 Harris 60 15 75 54 26 80 7 1.7 18 Hitachi 30 — 30 75 — 75 150 1.6 19 Sharp 50 — 50 55 — 55 10 1.2 20 National 58 — 58 50 — 50 –14 1.0 21 ES2 36 — 36 48 — 48 33 1.0 22 Ricoh 40 — 40 45 — 45 13 0.9 23 Atmel — — — 45 — 45 N/A 0.9 24 LG Semicon 18 — 18 40 — 40 122 0.8 25 Mitsubishi 31 — 31 35 — 35 13 0.7 26 S-MOS/Seiko 31 — 31 35 — 35 13 0.7 27 Dialog 27 — 27 33 — 33 22 0.7 28 MHS 22 — 22 26 — 26 18 0.5 29 Triquint* 20 — 20 25 — 25 25 0.5 30 Samsung 15 — 15 25 — 25 67 0.5 31 Hughes 20 — 20 24 — 24 20 0.5 32 Sanyo 20 — 20 24 — 24 20 0.5 33 AMI 17 — 17 23 — 23 35 0.5 34 Oki 15 — 15 20 — 20 33 0.5 35 Siemens** 20 — 20 15 — 15 –25 0.4 36 Kawasaki Steel 10 — 10 15 — 15 50 0.3 37 Elex 11 — 11 14 — 14 27 0.3 38 ABB Hafo 9 — 9 11 — 11 22 0.2 Others 97 5 102 97 4 101 –1 2.1 Total 3,660 90 3,750 4,700 70 4,770 27 100.0 *GaAs **Phasing out of standard cell business Source: ICE, "Status 1996" 13638N

Figure 3-27. Standard Cell IC Leaders

3-24 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Industry Trends

In the number three position was Symbios Logic, Inc. (formerly NCR). It increased its standard cell business 27 percent in 1995. It continued to emphasize its cell-based library—one that is 0.5 micron and based on a 3V optimized, triple-level metal, CMOS process providing functionality that is 20 percent faster and consumes 50 percent less power than the company’s previous best- performing standard cell family.

Overall, the standard cell market grew 27 percent in 1995 and is forecast to continue to grow at a strong pace through the balance of the decade.

As shown in Figure 3-28, CMOS standard cells dominated the market in 1995 and are forecast to do so again in the year 2000. As in the gate array market, there will likely be marginal increases in the use of BiCMOS technology. Even GaAs technology may see a small increase in use through- out the industry. However, CMOS devices will dominate.

CMOS CMOS 93% 91%

1995 2000

GaAs BiCMOS Bipolar 1% Bipolar 4% GaAs BiCMOS <1% 2% 2% 6%

Total Market $4.8B Total Market $12.7B Source: ICE, "Status 1996" 12907P

Figure 3-28. Standard Cell Market by Process Technology

The worldwide standard cell market by geographic sector is displayed in Figure 3-29. In 1994, Japan’s share of the standard cell market was 35 percent; 34 percent in North America. In 1995, Japan’s share grew, while it slipped for North America. There is no denying that Japanese firms performed well in the 1995 standard cell market, but some of the 1995 growth in the Japanese mar- ket is attributable to the rise in the value of the yen. Continuing through the year 2000, the ROW region will gain additional marketshare, at the expense of the Japanese region.

The 1995 and 2000 standard cell markets by application are provided in Figure 3-30. Much like the gate array market, data processing and telecom will continue to be the leading consuming seg- ments for standard cell devices through the year 2000. Marginal expansion is forecast for the con- sumer/auto sector. Automobiles are incorporating ever-increasing electronic sophistication into their systems and standard cells will be a big part of that business. Meanwhile, the industrial and military segments will decline to account for slightly more than three percent by the year 2000.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-25 ASIC Industry Trends

ROW ROW 8% 11% Japan North Japan 38% North 35% America 1995 America 2000 30% 30% Europe Europe 24% 24%

Total Market = $4.8B Total Market = $12.7B Source: ICE, "Status 1996" 10403V

Figure 3-29. Worldwide Standard Cell Market by Region

Telecom Telecom Data 30% Data 33% 1995 2000 Processing Processing 51% 48% Industrial 4% Industrial 3%

Consumer/Auto Consumer/Auto Military 14% Military 16% 1% <1% Total Market = $4.8B Total Market = $12.7B Source: ICE, "Status 1996" 12906N

Figure 3-30. Standard Cell Market by Application

Within the standard cell segment is the mixed-mode (or mixed-signal) cell-based market. Figure 3-31 lists the top mixed-mode standard cell suppliers and their sales for 1994 and 1995.

Rising performance and increasing integration has opened up new avenues for mixed-signal ASICs. Accordingly, the number of companies involved in the mixed-signal market keeps grow- ing. The mixed-signal market used to be the playground of the small or mid-size company. In 1993, Alcatel Mietec was the leading mixed-signal supplier. More recently, some large firms have seen the value of being a part of this market and have moved in. AT&T (the largest supplier in 1995), Symbios, TI, and SGS-Thomson are four large corporations that saw their mixed-mode sales increase nicely in 1995. Overall, the mixed-signal market grew 22 percent in 1995.

The mixed-mode standard cell market forecast is shown in Figure 3-32. ICE estimates that mixed- mode devices accounted for 26 percent of the $4.8 billion standard cell market in 1995. By the year 2000, mixed-mode devices are forecast to increase to 30 percent of the $12.7 billion standard cell market. That amounts to a 26 percent cumulative annual growth rate over the five-year period.

3-26 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Industry Trends

1993 1994 1995 1995/1994 1995 1995 Mixed-Signal 1995 Company Sales Sales Sales Percent Percent Total Standard Percent Rank ($M) ($M) ($M, EST) Change Marketshare Cell of Total 1 AT&T 96 138 170 23 14 655 26 2 Alcatel Mietec 116 130 130 — 11 166 78 3 Symbios 70 90 125 39 10 410 30 4 TI 70 86 115 34 9 315 37 5 GEC Plessey 88 120 75 –38 6 80 94 6 AMS 46 58 74 28 6 97 76 7 Exar 19 48 72 50 6 95 76 8 SGS-Thomson 18 30 50 67 4 100 50 9 Harris 26 36 48 33 4 80 60 10 NEC 10 25 45 80 4 340 13 — Others 211 249 326 31 27 2,432 13 — Total 770 1,010 1,230 22 100 4,770 26

Source: ICE, "Status 1996" 20400

Figure 3-31. Mixed-Signal Standard Cell Leaders

Digital Digital 74% 70% 1995 2000 $4.8B $12.7B

Mixed-Mode Mixed-Mode 26% 30%

Source: ICE, "Status 1996" 15431L

Figure 3-32. Mixed-Mode Standard Cell Market Forecast

PLD SUPPLIERS

The top players in the PLD market and their sales for 1994 and 1995 are shown in Figure 3-33. The numbers displayed do not include software and development system sales. This list is dominat- ed by North American companies (nine of the top ten). In fact, the nine U.S. suppliers shown in the list accounted for 95 percent of the 1995 PLD market. There are several small-to-medium size companies that vigorously compete for PLD marketshare. Firms such as Xilinx (which, with an aggressive strategy, took over the leading position in 1994), Altera, Lattice, and Actel have all found a particular niche in the marketplace.

Lively competition in the PLD market led to at least three “marginal” players announcing their intentions to exit the PLD market in 1994 and 1995. National started by proclaiming that it stopped taking new orders for programmable logic. Next, Intel announced that it sold its pro- grammable logic business to Altera for $50 million in cash and stock. Lastly, Actel declared that it purchased the FPGA business of its second-source partner, Texas Instruments.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-27 ASIC Industry Trends

1995/1994 1995 1995 1994 ($M) 1995 ($M, EST) COMPANY PERCENT PERCENT RANK MOSBIPOLAR TOTAL MOS BIPOLAR TOTAL CHANGE MARKETSHARE

1 Xilinx 305 — 305 530 — 530 74 30 2 Altera* 181 — 181 355 — 355 96 20 3 AMD 178 92 270 242 73 315 17 18 4 Lattice 120 — 120 165 — 165 38 9 5 Actel 68 — 68 100 — 100 47 6 6 AT&T 43 — 43 82 — 82 91 5 7 Cypress 64 — 64 81 — 81 27 4 8 TI 40 43 83 5 33 38 –54 2 9 Atmel 16 — 16 30 — 30 88 2 10 Philips 3 18 21 10 13 23 10 1 Others** 102 2 104 60 1 61 –41 3 Total 1,120 155 1,275 1,660 120 1,780 40 100 1Does not include software and development system sales. *Purchased Intel's PLD business in 1994. **National is phasing out both MOS and bipolar PLDs by the end of 1995. Source: ICE, "Status 1996" 13601P

Figure 3-33. PLD Sales Leaders1

The competition never sleeps in the PLD market. During 1994 and 1995, suppliers continued to battle for increased marketshare by adding special features or making devices faster or more com- plex. The result was a steep decline in prices. For example, in 2Q95, Cypress Semiconductor announced price reductions of as much as 40 percent on many of its CPLDs and FPGAs. Cypress has an advantage over many other PLD suppliers in that it owns several wafer fabs. Therefore, it has the flexibility to adjust manufacturing schedules to meet PLD demand and with high-volume runs is often able to charge less than other vendors.

Falling prices (20-25 percent in 1994) resulted in slow PLD market growth in 1994. The PLD mar- ket increased just seven percent to $1.275 billion in 1994 but recovered with a 40 percent increase in 1995. The forecast through the end of the decade calls for greater market expansion. As shown earlier in this section, the overall PLD market is forecast to have a cumulative annual growth rate of 20 percent from 1995 through the year 2000. Complex PLDs and FPGAs will contribute the most to the expected growth.

One the major benefits driving PLD usage continues to be the time-to-market factor. Of three prof- itability factors (including excessive production costs and development cost overrun), time-to- market is oftentimes the most critical in an electronics industry where market windows seem to be continually shrinking.

PLD marketshare for 1995 is displayed in Figure 3-34. AMD, which held a 46 percent PLD mar- ketshare in 1988, secured only 18 percent in 1995. Its PLD market grip loosened quickly because of aggressive competition from some of the “younger” suppliers mentioned previously. In addi-

3-28 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Industry Trends

tion, up until around 1990, AMD emphasized bipolar PLDs. In fact, 1993 was the first year AMD produced a greater percentage of CMOS PLDs than bipolar PLDs (AMD is still the leading bipo- lar PLD supplier). AMD now vigorously pursues CMOS technology.

TOTAL PLD AT&T MARKET 4% Other Cypress 8% 5% Xilinx Actel 30% 6% Lattice $1,720M 9%

AMD Altera 20% National Other 18% <1% 6% Cypress 5% AT&T 5% Philips 11% Actel Xilinx 6% 32%

Lattice $1,660M TI $120M 10% 28% AMD 61% AMD Altera 15% 21%

CMOS BIPOLAR Source: ICE, "Status 1996" 13602P

Figure 3-34. 1995 PLD Marketshare

1994 1995 1995/1994 1995 Figure 3-35 shows the 1994 and 1995 1995 Company Sales Sales Percent Percent Rank FPGA sales leaders. Xilinx still ($M) ($M, EST) Change Marketshare holds a commanding 70 percent 1 Xilinx 300 525 75 70 share of the FPGA market. 2 Actel* 68 100 47 13 However, companies like Actel, 3 AT&T 43 75 74 10 AT&T, IBM, and Motorola all have 4 Cypress 2 13 550 2 — Others 47 37 –22 5 big plans to take larger percentages — Total 460 750 63 100 of the future FPGA market. *Purchased TI's antifuse FPGA business in 1995. Source: ICE, "Status 1996" 20401

Figure 3-35. Leading FPGA Suppliers

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-29 ASIC Industry Trends

Xilinx, which took over as the leading PLD supplier in 1994, increased its lead in 1995. Xilinx’s growth has come through aggressive market introduction of many, very well accepted new prod- ucts. During 1995, Xilinx expects to introduce almost as many new products as it previously has in the company’s entire history. Xilinx and Altera each significantly increased its share of the CMOS PLD market while most of the other companies listed remained relatively flat or lost mar- ketshare.

Flash Figure 3-36 shows the CMOS and 1% Bipolar bipolar PLD markets broken out 7% Antifuse EPLD further. In 1995, 42 percent of PLDs 9% 6% SRAM were based on EEPROM technology, 35% CMOS Type 93% 35 percent were SRAM-based.

It is interesting to note that only EEPLD 42% about 20 percent of PLD consump- tion comes from Japan or the ROW Source: ICE, "Status 1996" 17112H region (Figure 3-37). In part, the Figure 3-36. 1995 PLD Market Segment by Types ($1,780M) Japanese and ROW regions have been slow to adopt PLDs into sys- tem designs because of their emphasis on high-volume consumer electronics. Most of the current usage of PLDs in these regions is for prototyping eventual gate array and standard cell designs.

ROW Japan 8% 12% North $1,660M Europe American 20% 60%

MOS PLD Market

ROW ROW Japan 8% Japan 8% 13% 12% North North $120M $1,780M Europe American Europe American 20% 59% 20% 60%

Bipolar PLD Market Total PLD Market Source: ICE, "Status 1996" 19513B

Figure 3-37. 1995 PLD Markets by Region

3-30 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Industry Trends

Throughout 1995 many PLD suppliers reported that the market for PLDs in Japan was picking up steam. It seems that the tight supply of less-than-10K-gate gate arrays is partially responsible for this increased PLD usage.

REGIONAL ASIC MARKETSHARE

The 1995 company marketshare for various ASIC segments is shown in Figure 3-38. The areas include North America, Japan, Europe, and the Rest of the World (ROW). A company’s sales are classified into one of the categories based on the location of its headquarters. So, even though a company such as Texas Instruments has fabs located around the world, its headquarters are in North America and therefore all sales are credited to that region.

1% 3% 1% 5% 100

5% 11% 8% 90

23%

14% 80

70 20% 38% 58% 26% 60 98% 50

Percentage 40

30 57% 49% 49% 20 34% 10

0 Gate Standard PLDs Analog Total ASIC* Arrays Cells ($1,780M) Arrays ($12,910M) ($6,125M) ($4,770M) ($235M) North American Japanese European Rest of World

Companies Companies Companies Companies *Not including full custom Source: ICE, "Status 1996" 12910V

Figure 3-38. 1995 ASIC Segment Marketshare

When it comes to ASIC devices, North American manufacturers have control in three of the four major ASIC segments. With the exception of gate arrays, North American manufacturers domi- nated production in each major ASIC category in 1995.

Though North American firms can boast of significant ASIC production, the sum dollar total of all three markets in which it dominates is only slightly more than the gate array market—the market in which the Japanese have the highest share. Hyundai’s purchase of NCR (now Symbios) in 1994 accounted for the large increase (to 11 percent in 1995 from less than one percent in 1995) in ROW share of the standard cell market.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-31 ASIC Industry Trends

Japanese companies have been most successful in the gate array market. Figure 3-39 shows that almost three-fourths of Japanese companies’ ASIC sales are gate arrays. North American sales in 1995 were roughly split between the standard cell, gate array, and PLD business segments. European and ROW companies both emphasized standard cell products.

PLDs <1% Analog Arrays 1% Analog Arrays 2%

Standard Cells PLDs 27% 26% Standard Cells 38% $4.9B $6.3B Gate Arrays Gate Arrays 73% 33%

Japanese Companies North American Companies PLDs 2% Analog Arrays 5%

Gate Arrays 26% Standard Gate Arrays Standard $1.0B $0.7B Cells 29% Cells 64% 74%

European Companies ROW Companies *Not including full custom Source: ICE, "Status 1996" 17794F

Figure 3-39. 1995 ASIC* Sales by Product Type

The total worldwide ASIC market (not including full custom) forecast by region is shown in Figure 3-40. By the year 2000, the North American market is expected to be the largest consumer of ASICs. It should be noted that, although the Japanese ASIC market is very large, much of the ASIC IC value “consumed” in Japan is from internal transfers at the large electronics conglomer- ates (e.g., Fujitsu, Hitachi, NEC, etc.).

ROW ROW 8% 11% Europe Japan Europe North America 19% 1995 37% 20% 2000 36% $12.9B $28.6B

North America Japan 36% 33%

Source: ICE, "Status 1996" 20402

Figure 3-40. Worldwide ASIC Markets by Region (Not Including Full Custom)

3-32 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Industry Trends

ASIC TECHNOLOGY TRENDS

Standard Cells (i.e., Cell-Based)

The two main technology thrusts in the standard cell ASIC segment in 1995 were the announce- ments and early implementation of 0.35µm, or finer, three- to five-layer metal CMOS technology and the addition of sophisticated specialty cells and cores to the cell-based libraries. As was shown earlier, the standard cell portion of the ASIC market is one of the fastest growing segments. The fast-paced technology improvements in the cell-based segment mentioned above are respon- sible for this growth surge.

While 0.35µm cell-based ASICs will represent only a small portion of the total ASIC market through 1996, VLSI technology and Hitachi envision fast rising demand for the technology, from many different system segments. As shown in Figure 3-41, the average gate density of the five segments listed is forecast to go from about 35K gates in 1993 to 1.4M gates in 1997. Moreover, average performance of these five segments is forecast to surge from 35MHz in 1993 to 150MHz in 1997! There is little doubt that million plus gate devices operating at 150MHz or higher will demand 0.35µm technology.

250 Network Computing Systems

200 CY '97 CY '95 CY '93

150

Mobile PC

100 Consumer Performance (MHz)

50 Wireless

0 0.01 0.1 1.0 10 Integration (millions of gates)

Source: Hitachi/VLSI Technology/ICE, "Status 1996" 20056

Figure 3-41. New Digital Markets for Advanced Cell-Based ASICs

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-33 ASIC Industry Trends

Shown below are some selected standard cell offerings that are serving the diverse ASIC needs of the system manufacturer. Many of the process-related announcements (e.g., LSI Logic’s G10 tech- nology) are not standard cell specific but will be used for gate arrays as well.

• In 2Q94 Motorola announced its 0.65µm FlexCore program for customizing MPU-based ASICs using its cell-based technology. Typical NREs are $125K. The first processor cores available were the 68EC000 and 68020. A 68030 core (12 MIPS) surfaced in late 1994 and a 36 MIPS 68040 was due in 1995. Power PC601 and 68060 cores are expected in 1996 (Figure 3- 42). The FlexCore devices are targeting applications that typically use more than 100K units per year. Motorola states that turnaround time from concept to silicon for FlexCore devices will be about 6-9 engineering months.

100

10 Performance (MIPS)

0 EC000 '020 '030 '040 '060 1992 1Q94 4Q94 1995 1996 Source: Motorola/ICE, "Status 1996" 19185

Figure 3-42. FlexCore Core Processor Performance/Availability

• LSI Logic licensed the Rambus ASIC cell for use in its CoreWare cell-based library.

• Mitsubishi plans to incorporate its M36066A 64-bit Alpha MPU (licensed from DEC) as a core cell for internal use in 1996 and external cell-based sales in 1997.

• In 4Q94 LSI Logic introduced three MIPS R4000-architecture core MPUs into its cell-based library (CoreWare). Figure 3-43 describes these three cores.

3-34 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Industry Trends

CW4001 Uses 0.5µ technology, 5K gates, 4mm2 in size, operates up to 60MHz, targeting cost sensitive applications (e.g., portable telecom, consumer multimedia, etc.). CW4010 Uses 0.5µ technology, 9K gates, superscalar RISC MIPS-II processor, operates up to 80MHz, targeting data processing applications. CW4100 Will use 0.35µ technology, was due out in 2H95, 64-bit internal data path.

Source: ICE, "Status 1996" 20057A

Figure 3-43. LSI Logic’s “Mini RISC” MIPS R4000 Cores

• In 2Q95 VLSI Technology announced it had included a DSP core cell (Pine—from DSP Group) into its standard cell library. DSP Group’s second-generation DSP cell “Oak” is also expected to be licensed by VLSI at a later date.

• NEC introduced its cell-based 0.35µm CMOS ASIC technology (CB-C9) in 4Q95. Volume production of the CB-C9 devices is expected in 2Q96. Some key aspects of the process are shown below.

Technology: 0.35µm drawn (0.27µm Leff) CMOS Metal Layers: 2 or 3 Raw Gates: 80K to 3.5M Usable Gates: 50K to 1.6M Pad Count: 104 to 1,200 Performance: 113ps at F/O=2, L=0.44mm, Vdd= 3.3V 151ps at F/O=2, L=0.44mm, Vdd= 2.5V Special Macros: ARM7TDMI, RISC CPU, V30MX (Intel 80286 compatible), Multiplier, PLL, A/D +D/A, Rambus interface cell

• In 3Q95 SGS-Thomson introduced the first member (ST20C4) of its 0.5µm 32-bit RISC core processor (40MIPS at 50MHz) family.

• In 4Q95 Hitachi began offering its SH-1 32-bit RISC CPUs as part of its 0.5µm cell-based ASIC library. Hitachi also licensed an MPEG-3 decompression core from CompCore Multimedia Inc. for use in its cell-based library.

• In 4Q95 IBM unveiled an extensive plan to target the cell-based ASIC marketplace using a wide range of what it calls “system building blocks” (Figure 3-44). Figure 3-45 shows the advanced technologies IBM will use to target the leading-edge ASIC market.

• LSI Logic introduced its G10™ ASIC process in 3Q95. Figure 3-46 shows some of the new G10 characteristics as well as a history of previous LSI Logic ASIC technologies. Figure 3-47 shows the various sub-families of the G10 technology and their targeted applications. Volume production of ASICs using the new process is due in 1Q96.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-35 ASIC Industry Trends

Processors CISC PPC PPC PPC* Mwave* 403 586 CMC 186 602 603 401 DSP

PPC Periph. SRAM DRAM OPB DMA Serial INTRPT Ctrl Ctrl Ctrl Ctrl Port Ctrl

Tele Audio PC DSP Periph. Codec Codec Bus

Fiber I/O Ports PCI UART PCMCIA SSA SCSI ENET Channel

DATA/IMAGE Functions ATM MPEG ECC IIC NTSC/PAL Compression

Memory** ROM RAM

Volt Analog PLL DAC ADC Reg

= Available in 1995 *Available in 1996 **Researching Flash Memory

Source: IBM/ICE, "Status 1996" 20403

Figure 3-44. IBM’s System Building Block Roadmap

Lithographic 0.8µm 0.5µm 0.35µm Generations

DRAM CMOS 4 CMOS 5 CMOS 6 4M 16M 64M ASIC CMOS 4L CMOS 5L 5.0V 3.3V 0.87µm Leff 0.46µm Leff 260K Gates 1,470K Gates Enhanced CMOS 4LP CMOS 5S CMOS 6S ASIC 3.3V 3.3V 2.5V 0.45µm Leff 0.36µm Leff 260K Gates 1,600K Gates CMOS 5X CMOS 6X 2.5V 1.8V 0.25µm Leff 1,600K Gates

Source: IBM/ICE, "Status 1996" 20404

Figure 3-45. IBM’s Silicon Evolution

3-36 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Industry Trends

LSI CMOS Process G10ª Family 500K 600K 400K 405K 300K

Drawn 0.35µm 0.5µm 0.6µm 0.7µm 0.8µm 0.6µm Effective 0.25µm 0.38µm 0.45µm 0.55µm 0.65µm 0.45µm Architectures Cell Based Cell Based Cell Based Gate Array Cell Based Cell Based Embedded Array Embedded Array Embedded Array Embedded Array Gate Array Gate Array Gate Array Gate Array Metal Interconnect 2, 3, 4, & 5 Layer 2, 3, & 4 Layer 2 & 3 Layer 2 Layer 2 Layer 2 & 3 Layer Operating Voltages 3.3 & 2.5 Volts 3.3 Volts 3.3 Volts 3.3 Volts 5.0 Volts 5.0 Volts I/O Options GTL/NTL/HSTL GTL/NTL/HSTL GTL/NTL GTL/NTL GTL/NTL GTL/NTL PECL to 622 MHz PECL to 622MHz PECL to 155MHz Universal PCI PCI PECL to 155MHz PCI PCI PCI PCI Impedance Controlled Mixed Signal Mixed Signal Mixed Signal Mixed Signal Mixed Signal LVTTL LVDS to 1.2GHz Mixed Signal Gate Capacities Usable (max) 5,000,000 1,500,000 1,200,000 165,000 250,000 600,000 Typical (used) 100K to 2,500K 60 to 500K 40 to 400K 20 to 75K 20 to 100,000K 40 to 300K Power Dissipation 0.4-0.7µW/Gate/MHz 1.0µW/Gate/MHz 1.5µW/Gate/MHz 1.4µW/Gate/MHz 5.0µW/Gate/MHz 3.2µW/Gate/MHz

Source: LSI Logic/ICE, "Status 1996" 20405

Figure 3-46. LSI Logic ASIC Technology Trends

G10-p G10-i G10-m

Product Focus Performance Maximum Mainstream, (gate speed) integration low power Target Applications Workstations Servers, Desktop, and desktop, supercomputers, digital video, telecomm workststions mobile telecomm Secondary Markets Digital video Mobile High-end encoding computing consumer Core Voltage 3.3V 2.5V 3.3V I/O Voltages 5V compatible, 3.3V, 2.5V 5V compatible, 3.3V, 2.5V 3.3V, 2.5V Target Design Size (gates) 100,000 to 500,000 to 100,000 to 500,000 2 million 1 million Maximum Capacity Random Logic (gates) 3.5 million 5 million 5 million Memory (half die, Mbits) 8 10 10

Source: LSI Logic/EDN/ICE, "Status 1996" 20406

Figure 3-47. LSI Logic’s G10 Product Sub-Families

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-37 ASIC Industry Trends

• Toshiba described its new 0.3µm drawn CMOS ASIC process in 4Q95. Some characteristics of this technology are shown below.

Production Volumes: 3Q96 Technology: 0.3µm drawn CMOS Metal Layers: 2 or 3 Raw Gates: Up to 3M Usable Gates: 1.9M on 17.5mm x 17.5mm die

• In 3Q95 Toshiba introduced its TC203 0.4µm CMOS family of ASICs for mixed 3/5V opera- tion. The family contains up to 690K usable gates.

Gate Arrays

With the ASIC industry being such a large portion of the total IC market, it is well worth the time and money spent for the IC manufacturer to quickly move leading-edge process technologies into the ASIC arena or develop processes specifically for ASICs. In the mid-1980’s, ASIC devices were typically using processing technology that was 2-3 years behind the high-volume memory part types. Currently, ASIC process technology is oftentimes equal to state-of-the-art memory devices.

One example of the narrowing technology gap between memory and ASICs is the ASIC produc- er’s use of a 0.5/0.35-micron CMOS process for its gate arrays, and cell-based ICs. This is the same feature size used for 16M and 64M DRAMs, which are now in the growth stages of their lifecycles. Figure 3-48 shows Toshiba’s DRAM and ASIC technology convergence.

2.0 TC110G TC140G 1.0 1M-Bit TC160G

m) DRAM

µ 4M-Bit DRAM TC180G 0.5 16M-Bit DRAM TC200G 64M-Bit DRAM TC220G Design Rule ( 0.2 DRAM Toshiba's gate array 0.1 1984 1986 1988 1990 1992 1994 1996 1998 2000 Fiscal Year Source: Toshiba/JEE/ICE, "Status 1996" 19170A

Figure 3-48. Transition of the DRAM and Toshiba’s Gate Array Development

3-38 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Industry Trends

As was shown in the previous sub-section concerning standard cell technology trends, there are numerous system types that will be demanding gate counts from 100K to over a million. The gate array vendors are hoping to gain a significant portion of this market. By the end of 1995 there were fifteen gate array vendors that offered arrays with greater than 500K usable gates!

In order to increase the efficiency of gate usage (and also increase performance by about 20 per- cent), almost all of the leading manufacturers of high-density (greater than 50,000 gates) gate arrays have begun implementing at least three-layer metal processes for non-pad-limited designs. Gate array manufacturers using three layers of metal interconnection are now able to offer up to 70 percent gate utilization as opposed to about 35-45 percent for double-layer metal arrays. In today’s VLSI era, interconnect technology has become more of a limiting factor than feature size for ASIC performance.

As IC producers continue to advance the density and performance of their ASIC offerings, the design environment has struggled to keep pace. It is estimated that as ASIC technology moved from 1.0µm to 0.3µm, interconnect delays, as a percent of total delay, went from 20 percent to over 80 percent (Figure 3-49). Since actual interconnect delay is dependent upon the layout of the IC itself, physical layout information is needed very early in the design cycle in order to accurately estimate timing conditions.

Typical Gate Delay

1 Delay, ns

0.1

Average Wiring Delay

Feature Size: 1.5µm 1.2µm 1.0µm 0.8µm 0.5µm 0.3µm Circuit Size: 20 30 60 150 500 1,000 (thousands of gates) Source: OKI Semiconductor/ICE, "Status 1996" 20407

Figure 3-49. Wiring Delay (Interconnect) Versus Gate Delay

Overall, the major thrusts in the leading-edge non-bipolar gate array market continue to be the use of new embedded functions, three-, four-, or five-layer metal, 0.35µm and finer feature sizes, usable gate densities surpassing 1,000,000, and low-voltage and mixed-voltage operation.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-39 ASIC Industry Trends

A good example of a leading-edge gate array is NEC’s 0.35-micron 2.0 million-gate gate array* introduced at CICC 1995 (Figure 3-50). Imagine the advanced design tools needed for this array (which has more transistors than Intel’s P6 MPU). The device supports high-speed I/O interface standards at voltages from 5V to 1.4V using a unique I/O power ring structure. The IC die con- tains up to 1,188 I/O and 1,204 bonding pads (staggered in two rows)! NEC began shipping pro- totypes using this technology in June of 1995 (it stated at that time it had 15 designs completed).

Density : 2.0 million gates Process : 0.35µ, triple-level metal, CMOS I/O : 1188 I/O cells, 1204 pads in two staggered rows (60µ pitch) Voltage Level : 1.4V to 5V Performance : 156MHz at 3.3V, 112ps (F/O = 1, 0.47mm wire) Power Dissipation : 0.8µW/MHz/gate at 3.3V Packaging : Up to 696-pin BGA

Source: CICC 1995/ICE, "Status 1996" 20203

Figure 3-50. NEC’s Two-Million-Gate Gate Array

A couple of significant 4Q95 gate array technology announcements are shown below.

• NEC announced its QB-8 ASIC technology incorporating a new proprietary gate architecture called “PUZZLE.” The QB-8 technology is a 3.3V 0.5µm drawn (0.35µm Leff) simplified (“epi-less”) three-layer metal BiCMOS process that offers up to 379K raw gates (223K usable).

The gate architecture is comprised of three differently sized transistors that can be tightly interlocked (like puzzle pieces). Production of QB-8 devices is expected in early 1996.

• Vitesse introduced a new GLX™ family of 0.5µm GaAs-based gate arrays. The GLX family offers up to 250K raw gates with utilization of up to 70 percent. Prototypes are to be avail- able beginning in 1Q96 with volume pricing at 0.10¢ per gate.

* It is estimated that only about 20 percent of the 1995 MOS gate array market was for arrays having more than 50K gates.

3-40 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Industry Trends

PLDs/FPGAs

Overview

The first field programmable logic devices were introduced almost 25 years ago. Basically, the benefits of using programmable logic have been shortening time to market and risk reduction. This has been true for over 20 years and will continue to be true in the foreseeable future.

Over the twenty years of programmable logic offerings, the term PLD has evolved to encompass more than just low-density bipolar products. The PLD industry has gone from using strictly bipo- lar technology and simple architecture to using CMOS EPROM, EEPROM, SRAM, Flash, and anti- fuse processing with very elaborate circuit designs.

In an industry as dynamic as the IC industry, the natural trend has been toward high-density and high-performance technologies. In the PLD market this is very obvious as simple bipolar PLDs are now steadily losing marketshare to the more flexible and higher density CMOS PLD tech- nologies.

As was mentioned earlier, ASSPs (Application Specific Standard Products) are taking away some of the market previously served by traditional ASIC devices. Along these same lines, there is an increasing number of PLDs that are being tailored for specific applications. The ASSP-type PLDs include:

- address decoding, - state machine, and - system functions.

Overall, PLDs are moving away from being used only as peripheral logic and more toward core logic at the heart of the system. As PLD technology and capabilities increase, ICE expects the PLD logic segment to be a cornerstone of the ASIC industry.

As was discussed earlier, the CMOS CPLD and FPGA markets have been and will continue to be the star performers in the ASIC marketplace. This stellar growth has caused a significant increase in competition, which in turn has spurred a steady stream of new product innovations and intro- ductions.

PLD Pricing Considerations

The 1995 price-per-gate for the PLD device was six times the price of a similar density CMOS gate array. In 1993, the PLD was 15 times the cost of a similar density CMOS gate array.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-41 ASIC Industry Trends

Using a total cost formula, the breakeven point for the gate array and PLD can be derived. At the 10,000 usable gate level, the PLD solution was more cost effective at unit volumes below 1,386 in 1995 (Figure 3-51). This figure was 660 in 1993 for comparable 5,000 gate devices.

70 61,700 10K-Gate 59,200 60 1995 Gate Array 58,000 50 48,900 5K-Gate 1993 38,115 Gate Array 40 41,400 1995 30 5K-Gate Breakeven 1993 Units 20 PLD 1993 1,386 10K-Gate Breakeven Units 10 8,800 1995 Total Cost (Thousands of Dollars) PLD 660 7,100 0 0 100 200 300 400 500 600 700 800 900 1,000 1,100 1,200 1,300 1,400 1,500 Project Units Source: ICE, "Status 1996" 16723D

Figure 3-51. 1993 5,000 and 1995 10,000 Usable Gate Total Cost

As shown, it does not take a large number of units for the gate array approach to amortize its large fixed cost to the point where it becomes more cost effective than the PLD. The $39 PLD unit price versus the $6.50 gate array device price assures a fairly low-volume crossover point given almost any reasonable gate array NRE charge.

Because the NRE charge is such a small part of the total cost make-up of an FPGA, the total unit price of the 1995 10,000 usable gate device decreases only 42 percent when going from using 100 units to using 1,500 units. However, because such a large portion of the gate array total cost is NRE, the amortization of the NRE causes the 1995 10,000 usable gate array total unit price to decrease about 92 percent when going from using 100 units to 1,500 units.

Figure 3-52 shows that whether at 100 or 1500 units, a very high percentage of the gate array’s cost is due to fixed (i.e., NRE) costs. When the IC industry was slumping (1989-1991) and heavily dis- counted NRE charges were the norm, the choice to use a gate array was very clear from the begin- ning. However, now that NRE charges have firmed, the PLD choice looks more attractive, espe- cially at low unit volumes.

As shown, 95 percent of the cost of using PLDs at 1500 units is from variable costs (i.e., the unit price). This is the reason it is so critical for the PLD producer to reduce device costs by using advance processes (0.6µm or less) and interconnect (3 layers of metal or more) schemes, both of which result in reduced die sizes and lower unit costs.

3-42 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Industry Trends

1% 100

17% 90

80

55% 70

60

95% 50 99% Percent 83% 40

30

45% 20

10

5% 0 Gate Array PLD Gate Array PLD 100 Units 1,500 Units

= Fixed Cost

= Variable Cost Source: ICE, "Status 1996" 20101

Figure 3-52. 1995 10K-Gate PLD Versus Gate Array Cost Make-Up

If the FPGA and gate array price trends continue as mentioned in the previous paragraph, the rel- ative FPGA/gate array price ratio by the end of the decade would be less than 2:1 (Figure 3-53). Given the time-to-market benefits of FPGAs, and less than a 2x price difference, it would be safe to assume that FPGAs would serve the vast majority of low gate count (40,000 gates) needs at that time.

PLDs will continue to increase in density to compete with “low-end” gate arrays. Figure 3-54 shows ICE’s estimate for the 1995 PLD market by gate count. The current definition of low-end for the gate array market is devices with less than 20,000 gates and speeds of less than 40MHz.

ICE estimates that about 20 percent of the total CMOS gate array market in 1995 was “low-end.” Thus, advanced PLD producers are attempting to use their 3-layer metal 0.6µm PLDs to target the $1.1 billion low-end business of the CMOS gate array supplier.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-43 ASIC Industry Trends

10 8 6

4

2

1 1995 Actual 0.8 0.6 FPGA 33X Price Per Gate 0.4 ¥ Trend

15X 12X 0.2 6X Cents Per Usable Gate 0.1 7X 0.08 0.06 2X CMOS Gate Array 0.04 Price Per Gate Trend

0.02

1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 Year Source: ICE, "Status 1996" 18551C

Figure 3-53. Relative Price Per Gate for FPGAs Versus Low Gate Count Gate Arrays

>10,000 7% <1,500 10% >5,000 to 10,000 10%

1,500 to 3,000 $1.7B 33% >3,000 to 5,000 40%

Source: ICE, "Status 1996" 20408

Figure 3-54. 1995 MOS PLD Revenue by Gate Count

3-44 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Industry Trends

It is interesting to note that in most cases the CMOS gate array suppler is not fighting the PLDs’ attack on the low-end market. Most CMOS gate array suppliers are concentrating on the high- density, high-performance, and high unit volume segment of the gate array market. With busi- ness booming since 1992, gate array vendors have become very “selective” of the contracts they take for gate array devices. Oftentimes turning down business in the process!

What this now means as far as the trend lines shown in Figure 3-53 is that the low-end CMOS gate array price per gate may stay flat in the future. With little competitive pressure, the low-end CMOS gate array price per gate could even increase in the late 1990’s.

While an annual 30 percent or greater decline in the PLD price per gate may be difficult to sustain into the late 1990’s, there is little doubt that PLDs will become more competitive in price compared to low-end gate arrays. This is one reason that ICE is bullish about the future of the PLD/FPGA business.

There is no doubt that, when comparing specific unit costs of gate arrays (even including NREs) and PLDs, gate array devices look favorable at all but the lowest volume levels. Why then has there been a surge in the PLD market over the past few years? The answer is the increasing impor- tance of the “time to market” factor. For example, in today’s high-end disk-drive market, lifecy- cles of six months to a year are fairly common.

PLD Technology Trends

Over the last few years the PLD market has been the most dynamic of all IC markets with regard to new product introductions. Shown below is a sampling of some of the major PLD technology announcements made in 1995.

• Xilinx began taking production orders for its 0.6µm three-layer metal antifuse-based PLDs (XC8100) in June of 1995. The antifuse devices contain from 1,000 to 9,000 usable gates with all routing resources located above the underlying sea-of-gates logic.

• Xilinx introduced its flash-based (5V-only) PLDs in late 1995. The 0.6µm devices allow 10,000 program/erase cycles and in-system programming. The devices are offered in usable gate densities of 800 to 12K.

• In 4Q95 Xilinx introduced its XC4000E series of SRAM-based FPGAs that offer 2.5K to 25K usable gates as well as on-chip dual-port SRAM capability. The devices are produced using 0.5µm three-layer metal CMOS technology. One-hundred piece quantities of the XC4020E (20,000 usable gates) cost $300 in 4Q95 and were expected to sell for $125 in volume in 2H96.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-45 ASIC Industry Trends

• Xilinx is working on an optimized in-system reconfigurable SRAM-based PLD family (XC6200) that reconfigures in microseconds. The release date for these devices has not been given.

• Beginning in 2Q95, Xilinx began phasing-in its 0.5µm technology (from 0.6µm) for its XC5000 SRAM-based FPGA family. The 0.6µm XC5000 family is shown in Figure 3-55.

XC5202 XC5204 XC5206 XC5210 XC5215 Usable Gates 2,200 - 2,700 3,900 - 4,800 6,000 - 7,500 10,000 - 12,000 14,000 - 18,000 Max I/O 84 124 148 196 244 Flip-Flops 256 480 784 1296 1936 Pricing* $9 $15 $25 $38 $68 (10K Quantity) * 2Q95 prices for the XC5202, XC5204, XC5206 and XC5210 devices are in PC84 packages; the XC5215 device is in PQ208. Source: ICE, "Status 1996" 20177A

Figure 3-55. Xilinx’s XC5000 Family

Xilinx’s long-term PLD density roadmap is shown Figure 3-56.

Plan "Perhaps" 1985/6 1994 1995 1996/7 2001 2001 Feature Size (µm) 2.0 0.6 0.5 0.35 0.20 0.15 Die Size (mm) 7.5 x 7.5 17 x 17 17 x 17 17 x 17 25 x 25 38 x 38 Number of Gates 800 25,000 50,000 100,000 500,000 1.25M Metal Layers 2 3 3 3-4 4-5 5-6 Wafer Size (mm) 100 150 150 200 200 300

Source: Xilinx/ICE, "Status 1996" 20346A

Figure 3-56. Xilinx’s PLD Technology Roadmap

• In 1Q95 Xilinx purchased NeoCAD Inc., a developer of high performance design software for FPGAs.

• In 1Q95 AMD announced that it signed a five-year deal with software developer Minc, Inc. (Boulder, CO.). The deal calls for Minc to develop and sell all of AMD’s PLD design software for its MACH CPLDs and PALs.

3-46 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Industry Trends

• In 1Q95 Altera described its FLEX 10K family of devices that are architecturally optimized for implementing memory on the PLD. The FLEX 10K is also designed to support on-chip ROM, multipliers, ALUs, and DSP functions. Figure 3-57 shows how the FLEX 10K is at the leading-edge of Altera’s broad line of PLD products.

FLEX 10K

FLEX 8000

MAX 9000

I/O MAX 7000 FLASH- logic

Classic and MAX 5000

Usable Gates

Classic MAX 5000 FLASHlogic MAX 7000 MAX 9000 FLEX 8000 FLEX 10K

Usable Gates 150 - 900 600 - 3,750 800 - 3,200 600 - 5,000 6,000 - 12,000 2,500 - 50,000 10,000 - 100,000 Performance (MHz) 50 - 125 50 - 100 50 - 100 70 - 150 50 - 100 75 75 Pin count 24 - 68 24 - 100 44 - 208 44 - 208 84 - 304 84 - 304 84 - 560 Technology EPROM EPROM FLASH EEPROM EEPROM SRAM SRAM

Source: Altera/ICE, "Status 1996" 20182

Figure 3-57. Altera’s PLD Product Line

• In 4Q95 Altera announced sampling of its EPF10K50 (50K gates) SRAM-based PLD. The device offers up to 20K bits of RAM or ROM. One-hundred unit pricing was $850 in 4Q95 with 1997 pricing projected to be $150 in 5,000-unit quantities.

• In 3Q95 Altera introduced its MegaFunctions Partners Program (AMPP). The program is an alliance between Altera and intellectual property providers that will develop synthesizable functional blocks (e.g., display controllers, 8-bit 6502 processors, etc.) for insertion into Altera’s FLEX 10K family of SRAM-based PLDs. As of 3Q95 Altera was working with over 20 suppliers in the AMPP project.

• In 3Q95 aftermarket IC supplier Rochester Electronics agreed to carry Altera’s discontinued high-density PLD devices.

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-47 ASIC Industry Trends

• In 1Q95 Altera began shipping its gate array-to-PLD design conversion tools. The tools sup- port LSI Logic and Fujitsu gate arrays. Additional gate array vendors are to be announced.

• Actel introduced its 3200DX family in 3Q95. The 6,500-gate 3265DX was available in 3Q95 with the 20,000-gate A32200DX available in January of 1996. Initially offered in 0.6µm tech- nology , the family will move to 0.5µm processing in early 1996. Members of the 3200DX family of PLDs will be able to incorporate blocks of high-speed (5ns) dual-port SRAM (Figure 3-58).

JTAG

SRAM SRAM 32 x 8 32 x 8 or or 64 x 4 64 x 4

SRAM SRAM 32 x 8 32 x 8 or or 64 x 4 64 x 4

SRAM SRAM Logic 32 x 8 Logic 32 x 8 Logic Modules or Modules or Modules 64 x 4 64 x 4 JTAG JTAG SRAM SRAM 32 x 8 32 x 8 or or 64 x 4 64 x 4

SRAM SRAM 32 x 8 32 x 8 Fast or or Decode 64 x 4 64 x 4 Module

SRAM SRAM 32 x 8 32 x 8 or or 64 x 4 64 x 4

JTAG

Source: Actel/ICE, "Status 1996" 20409

Figure 3-58. Actel’s 3200DX FPGA Architecture

• AMD introduced its 0.5µm MACH 5 PLDs in 3Q95. The devices offer 7.5ns performance, PCI compliance, and JTAG capability. The family is expected to move to 0.35µm processing in 1996.

3-48 INTEGRATED CIRCUIT ENGINEERING CORPORATION ASIC Industry Trends

• AT&T introduced its 0.35µm ORCA™ Family of SRAM-based FPGAs in 4Q95. A 15K-gate device is due out in 1Q96 with densities of up to 60K-gates to follow (Figure 3-59).

1.8 100,000+ 1.7 95,000 1.6 90,000 85,000 1.5 Geometry Gates 80,000 1.4 75,000

m) 1.3 70,000 µ 1.2 60,000 gates 65,000 1.1 60,000 55,000 1.0 50,000 0.9 0.8µm 45,000 0.8 40,000 gates 40,000 0.7 0.6µm 35,000 Usable Gates/Chip 0.6 30,000 Minimum Geometry ( 26,000 gates 0.5 25,000 0.5µm 20,000 0.4 0.35µm 15,000 0.3 4,000 gates 10,000 0.2 7,000 gates 5,000 0.1 0 1992 1993 1994 1995 1996 1997 Year Source: AT&T Microelectronics/ICE, "Status 1996" 20431

Figure 3-59. AT&T FPGA Density and Feature Size Trends

• In 4Q95 Lattice introduced a 3.5ns 3.3V 20-pin 16LV8 EEPROM-based PLD using 0.5µm technology. A 3.5ns 22V10 device is expected by 2Q96.

• In 4Q95 Hitachi began selling FPGAs based on Crosspoint Solutions’ antifuse-based tech- nology in Japan. Hitachi will also co-develop libraries to convert Crosspoint FPGAs to Hitachi gate arrays.

• A new entrant emerged in the FPGA market in 2Q95—Gate Field, a division of EDA soft- ware supplier Zycad. The FPGAs are produced by Rohm using a 0.6µm flash-based process. Its 9K total gates (2.2K usable) devices were expected to be priced at $30/25K at the end of 1995. A 100K total gate device was due late in 1995.

• Production quantities of IMP’s electrically programmable analog circuit (EPAC) began ship- ping in 1Q95. The EPACs are produced using a mixed-signal 1.2µm CMOS process with on- chip EEPROM. The EPACs cost $25 (100) and are available in a mask-programmed version (MPAC).

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-49 ASIC Industry Trends

As discussed above, with a movement to high density PLD devices, the PLD producers are being asked to offer functions other than pure logic on-chip. Many PLD suppliers have begun offering PLDs with on-chip SRAM or ROM (e.g., Altera, Xilinx, etc.). Altera and Motorola are even con- templating adding MCU embedded functions to their PLD devices!

The in-system reprogrammable PLD topic is one that has only recently surfaced (1994). Some of the early players in this area include:

- AT&T (SRAM-based) - Altera (SRAM-based, MCM and monolithic) - AMD (EEPROM-based) - Atmel (SRAM-based) - Lattice (EEPROM-based) - Xilinx (SRAM-based and flash-based)

As an example of a reconfigurable application, Altera states that its reprogrammable PLD can be configured as a display accelerator or circuit simulator as needed. Altera says, “. . . that by using reprogrammable logic the potential exists to configure the hardware for more direct processing of the data.”

Chris DeMonico of AT&T states that there are three major reasons for logic reconfigurability. “First, to meet standards, which are evolving and therefore are in a constant state of flux; second, to keep up with system functionality changes; and third, to accommodate multiple data formats in a single device.” There is little doubt that reconfigurability will be a powerful tool to enhance a system’s efficiency.

Some possible early system applications for reprogrammable logic include telecommunications, geophysical information processing, medical imaging, and computer architecture simulation.

In the telecommunications area one can easily envision the need for a PLD device to dynamically reconfigure itself to accommodate multiple interface or telecommunications protocols and stan- dards (Figure 3-60).

Atmel describes its reconfigurable logic as “cache logic.” Since much of a system’s hardware logic is idle at a given time, the ability to reconfigure the logic on-the-fly to optimally serve the software’s immediate computational requirements can greatly accelerate the performance of the system.

It should be noted that reconfigurable PLD logic is still in its infancy. 1995 design tools and pro- grams were still not sufficient to manage dynamically reconfigurable hardware efficiently. However, as system designers continue to explore ways to increase system performance, ICE expects that reconfigurable PLDs will find an increasing market to serve.

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(a) Telecom T1/T1E 2.048 Mbits/s (Europe) DSP Algorithm Engine Line Interface Card 1.544 Mbits/s (U.S.)

Synchronizer Extract timing from T1/T1E source

(b) Sonet/Synchronous Networks

DSP Algorithm Engine Line Interface Card DS3: 45 Mbits/s STS1E: 52 Mbits/s

Synchronizer Extract timing from T1/T1E source or bits

(c) Algorithm Engine

Fixed Algorithm Engine

Dual-Port RAM DSP Core Microcontroller

(d) ATM

ATM Switch Fabric Line Interface Card Overhead channels Framing (e) Graphics-Accelerator Card

Hard Disk Compression/Decompression FPGA Video Engine

Source: AT&T Microelectronics/ICE, "Status 1996" 20180

Figure 3-60. FPGA Can Reconfigure to Meet Various Standards

INTEGRATED CIRCUIT ENGINEERING CORPORATION 3-51 ASIC Industry Trends

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