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Standard Cell Library Design with Transistor Folding Using

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Standard Cell Library Design with Transistor Folding Using STANDARD CELL LIBRARY DESIGN WITH TRANSISTOR FOLDING USING 65NM TECHNOLOGY BY GLOBAL FOUNDRIES by Vibhav Kumarswami Salimath APPROVED BY SUPERVISORY COMMITTEE: ___________________________________________ Dr. Carl M. Sechen, Chair ___________________________________________ Dr. William Swartz ___________________________________________ Dr. Benjamin Carrion Schaefer Copyright 2018 Vibhav Kumarswami Salimath All Rights Reserved To my family and my teachers STANDARD CELL LIBRARY DESIGN WITH TRANSISTOR FOLDING USING 65NM TECHNOLOGY BY GLOBAL FOUNDRIES by VIBHAV KUMARSWAMI SALIMATH, B.E. THESIS Presented to the Faculty of The University of Texas at Dallas in Partial Fulfillment of the Requirements for the Degree of MASTER OF SCIENCE IN ELECTRICAL ENGINEERING THE UNIVERSITY OF TEXAS AT DALLAS May 2018 ACKNOWLEDGMENTS I want to thank my advisor, Dr. Carl Sechen, for his continuous supervision and guidance. I took Dr. Sechen’s course during my first semester in the master’s degree program. I loved the way he taught and came away from the course with a clear idea of my research interests. Working at the Nanometer Design Lab has been an incredible experience and I am most grateful for this opportunity. Thank you to my friends at Nanometer Design Lab for their valuable input, especially Xiangyu Xu and Qiongdan Huang (Olivia). I wish to specially thank Dr. William Swartz Jr. for providing me with timely help and support. Thank you to Dr. William Swartz Jr. and Dr. Benjamin Carrion Schaefer for serving as the committee members for my defense and providing me with their support and advice. I am extremely grateful to my family and friends for their encouragement, which has motivated me to do my best academically. April 2018 v STANDARD CELL LIBRARY DESIGN WITH TRANSISTOR FOLDING USING 65NM TECHNOLOGY BY GLOBAL FOUNDRIES Vibhav Kumarswami Salimath, MSEE The University of Texas at Dallas, 2018 ABSTRACT Supervising Professor: Dr. Carl M. Sechen We use the concept of transistor folding to design some of the cells in the cell library. Transistor folding, also known as fingering of MOSFETs, is used when we require cells with larger drive strengths. By keeping the beta ratio (Wp / Wn) fixed, a greater number of transistors are arranged in parallel. Whenever there is a requirement of large current to the load, this technique of transistor folding is employed. The major advantage of using this technique is that it drastically reduces the resistances. To be more precise, if there are N transistors in parallel then the overall resistance reduces by a factor of N. Folding is used to optimize the resistance of the gate poly along the width of the transistor. Gate poly is driven from one end; hence, there is a reason to have a guideline that states maximum width of single finger. Folding is the only way to meet this guideline for large transistors. Our physical library has 16 functions, each with several drive sizes, giving a total of 83 cells. These 16 functions are comprised of simple functions as well as some complex functions. The complex functions were included in the library design because adding these complex functions improves the synthesis performance. Various parameters such as layout area, fall-time, rise-time, fall-transition time, and rise transition time are obtained during library characterization. The vi designed cells were characterized using Synopsys Siliconsmart ACE and we were able to automatically place and route various designs using Cadence Encounter. The static timing analysis was performed using Synopsys PrimeTime. vii TABLE OF CONTENTS ACKNOWLEDGEMENTS ...…………………………………………………………………… v ABSTRACT ……………………………………………………………………………………. vi LIST OF FIGURES ……...……………………………………………………………………... xi LIST OF TABLES ……………………………………………………………………………... xv CHAPTER 1 INTRODUCTION 1.1 Significance of a Quality Library …………………………………………… 1 1.2 Importance of Transistor Folding …………………………………………… 1 1.3 Literature Review …………………………………………………………… 2 1.4 Our Work ……………………………………………………………………. 3 CHAPTER 2 TRANSISTOR FOLDING 2.1 Introduction to Transistor Folding ………………………………………….. 4 2.2 Parasitic Capacitances and Parasitic Resistance ……………………………. 6 2.3 Two Ways of Transistor Folding .................................................................... 7 CHAPTER 3 CELL LIBRARY DESIGN 3.1 Inverter ……………………………………………………………………… 8 3.2 Buffer ………………………………………………………………………. 11 3.3 NAND2 …………………………………………………………………….. 13 3.4 NAND3 …………………………………………………………………….. 15 3.5 NOR2 ………………………………………………………………………. 17 3.6 AOI21 ……………………………………………………………………… 20 3.7 AOI22 ……………………………………………………………………… 22 viii 3.8 OAI21 ……………………………………………………………………… 24 3.9 OAI22 ……………………………………………………………………… 26 3.10 MUX 2:1 .…………………………………………………………………. 28 3.11 Mirror-Carry ….…………………………………………………………... 32 3.12 Mirror-Sum ……………………………………………………………….. 34 3.13 XOR2 ……………………………………………………………………... 37 3.14 XNOR2 …………………………………………………………………… 39 3.15 D Flip-Flop ……………………………………………………………….. 41 3.16 Scan Flip-Flop ……………………………………………………………..43 3.17 Filler ……………………………………………………………………… 45 CHAPTER 4 OVERALL DESIGN FLOW 4.1 DRC, LVS, PEX …………………………………………………………… 48 4.2 Abstract Generation and LEF file ………………………………………….. 48 4.3 Library Characterization using Siliconsmart ACE ………………………… 48 4.4 Library Compilation using LC Shell ……………………………………….. 49 4.5 Gate-Level Netlist using Design Vision …………………………………… 50 4.6 Automatic Place and Route in Encounter ………………………………….. 50 4.7 Static Timing Analysis by Primetime ……………………………………… 51 CHAPTER 5 RESULTS 5.1 DRC, LVS, PEX Results ……………………………………………………. 52 5.2 Abstract View ………………………………………………………………. 55 5.3 Library Characterization Results ……………………………………………. 55 ix 5.4 Library Compilation Results ………………………………………………... 57 5.5 Cell Report in Design Vision ………………………………………………... 58 5.6 Automatic Place and Route Results …………………………………………. 58 CHAPTER 6 CONCLUSIONS AND FUTURE WORK ……………………………………. 63 REFERENCES ………………………………………………………………………………… 65 BIOGRAPHICAL SKETCH …………………………………………………………………... 67 CURRICULUM VITAE ……………………………………………………………………….. 68 x LIST OF FIGURES Figure 2.1 Transistor Layout …………………………………………………………………….. 4 Figure 2.2 Transistor Folding Schematic ………………………………………………………... 5 Figure 2.3 Transistor Folding Layout …………………………………………………………… 5 Figure 2.4 Parasitic Capacitances ……………………………………………………………….. 6 Figure 2.5 (a) Parasitic Resistance of Transistor (b) Parasitic Resistance of Folded Transistor ... 6 Figure 2.6 (a) Unfolded Transistor (b) Even Fingered Transistor (c) Odd Fingered Transistor ... 7 Figure 3.1 Inverter Schematic ……………………........................................................................ 8 Figure 3.2 (a) Inverter 0.25x (b) Inverter 0.5x (c) Inverter 1x (d) Inverter 2x (e) Inverter 3x (f) Inverter 4x (g) Inverter 6x ……………………………………………………………………. 9 Figure 3.2 (h) Inverter 8x (i) Inverter 12x (j) Inverter 16x …………………………………….. 10 Figure 3.3 Buffer Schematic …………………………………………………………………… 11 Figure 3.4 (a) Buffer 0.25x (b) Buffer 0.5x (c) Buffer 1x (d) Buffer 2x ………………………. 11 Figure 3.4 (e) Buffer 3x (f) Buffer 4x (g) Buffer 6x (h) Buffer 8x (i) Buffer 12x …………….. 12 Figure 3.4 (j) Buffer 16x ……………………………………………………………………….. 13 Figure 3.5 NAND2 Schematic …………………………………………………………………. 13 Figure 3.6 (a) NAND2 0.5x(b) NAND2 1x (c) NAND2 2x (d) NAND2 3x (e) NAND2 4x (f) NAND2 6x ………………………………………………………………………………….. 14 Figure 3.6 (g) NAND2 8x ……………………………………………………………………… 15 Figure 3.7 NAND3 Schematic …………………………………………………………………. 15 Figure 3.8 (a) NAND3 0.5x (b) NAND3 1x (c) NAND3 2x (d) NAND3 3x (e) NAND3 5x …. 16 Figure 3.8 (f) NAND3 7x ………………………………………………………………………. 17 xi Figure 3.9 NOR2 Schematic …………………………………………………………………… 17 Figure 3.10 (a) NOR2 0.5x (b) NOR2 1x (c) NOR2 2x (d) NOR2 3x (e) NOR2 4x ………….. 18 Figure 3.10 (f) NOR2 6x (g) NOR2 8x ………………………………………………………….19 Figure 3.11 AOI21 Schematic …………………………………………………………………. 20 Figure 3.11 (a) AOI21 0.5x (b) AOI21 1x (c) AOI21 2x …………………………………….... 20 Figure 3.12 (d) AOI21 3x (e) AOI21 5x (f) AOI21 7x ………………………………………… 21 Figure 3.13 AOI22 Schematic …………………………………………………………………. 22 Figure 3.14 (a) AOI22 0.5x (b) AOI22 1x (c) AOI22 2x ……………………………………… 22 Figure 3.14 (d) AOI22 3x (e) AOI22 5x (f) AOI22 7x ………………………………………… 23 Figure 3.15 OAI21 Schematic …………………………………………………………………. 24 Figure 3.16 (a) OAI21 0.5x (b) OAI21 1x (c) OAI21 2x ……………………………………… 24 Figure 3.16 (d) OAI21 3x (e) OAI21 5x (f) OAI21 7x ………………………………………… 25 Figure 3.17 OAI22 Schematic …………………………………………………………………. 26 Figure 3.18 (a) OAI22 0.5x (b) OAI22 1x (c) OAI22 2x ……………………………………… 26 Figure 3.18 (d) OAI22 3x (e) OAI22 5x (f) OAI22 7x ………………………………………… 27 Figure 3.19 (a) Transmission gate MUX 2:1 (b) Static Timing Analysis viable MUX 2:1 (c) Final Design of MUX 2:1 …………………………………………………………………... 28 Figure 3.20 MUX 2:1 Schematic ………………………………………………………………. 29 Figure 3.21 (a) MUX 2:1 0.5x (b) MUX 2:1 1x ……………………………………………….. 29 Figure 3.21 (c) MUX 2:1 2x (d) MUX 2:1 3x (e) MUX 2:1 5x ……………………………….. 30 Figure 3.22 (a) Most Area Efficient Adder (b) Fast Adder (c) Comparison among different full-adders in a 16 column 16:2 compressor ………………... 31 xii Figure 3.23 Mirror-Carry Schematic …………………………………………………………... 32 Figure 3.24 (a) Mirror-Carry 0.5x (b) Mirror-Carry 1x (c) Mirror-Carry 2x (d) Mirror-Carry 3x …………………………………………………………………………….. 33 Figure 3.24 (e) Mirror-Carry 5x ………………………………………………………………... 34 Figure 3.25 Mirror-Sum Schematic ……………………………………………………………. 35 Figure 3.26 (a) Mirror-Sum 0.5x (b) Mirror-Sum 1x ………………………………………….. 35 Figure 3.26 (c) Mirror-Sum 2x (d) Mirror-Sum 3x ……………………………………………. 36 Figure 3.26 (e) Mirror-Sum
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