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UCLA Electronic Theses and Dissertations UCLA UCLA Electronic Theses and Dissertations Title Implications of Modern Semiconductor Technologies on Gate Sizing Permalink https://escholarship.org/uc/item/56s9b2tm Author Lee, John Publication Date 2012 Peer reviewed|Thesis/dissertation eScholarship.org Powered by the California Digital Library University of California University of California Los Angeles Implications of Modern Semiconductor Technologies on Gate Sizing A dissertation submitted in partial satisfaction of the requirements for the degree Doctor of Philosophy in Electrical Engineering by John Hyung Lee 2012 c Copyright by John Hyung Lee 2012 Abstract of the Dissertation Implications of Modern Semiconductor Technologies on Gate Sizing by John Hyung Lee Doctor of Philosophy in Electrical Engineering University of California, Los Angeles, 2012 Professor Puneet Gupta, Chair Gate sizing is one of the most flexible and powerful methods available for the timing and power optimization of digital circuits. As such, it has been a very well-studied topic over the past few decades. However, developments in modern semiconductor technologies have changed the context in which gate sizing is performed. The focus has shifted from custom design methods to standard cell based designs, which has been an enabler in the design of modern, large-scale designs. We start by providing benchmarking efforts to show where the state-of-the-art is in standard cell based gate sizing. Next, we develop a framework to assess the impact of the limited precision and range available in the standard cell library on the power-delay tradeoffs. In addition, shrinking dimensions and decreased manufacturing process control has led to variations in the performance and power of the resulting designs. We provide methods for gate sizing with statistical delay, and compute bounds to show that full statistical power optimization is not essential. Lastly, to address the complexities of doing in design in a yet immature process, we provide a method to perform incremental discrete gate sizing to account for both anticipated and unanticipated changes in the manufacturing process parameters. ii The dissertation of John Hyung Lee is approved. Dejan Markovic Jason Cong Lieven Vandenberghe Puneet Gupta, Committee Chair University of California, Los Angeles 2012 iii To my teachers. iv Table of Contents 1 Introduction ..................................... 1 1.1 Thephysicaldesignprocess . .. 6 1.2 Outline...................................... 9 2 Gate Sizing and Threshold Voltage Assignment Overview ........ 11 2.1 StaticTimingAnalysis ............................. 12 2.1.1 Conceptsandterminology . 12 2.1.2 Computingarrivaltimesandslacks . .. 16 2.1.3 Interconnect delay and slew propagation . .... 18 2.1.4 Additionaltopics ............................ 20 2.2 Continuous sizing methods for gate sizing and vt assignment: . 22 2.3 Discrete gate sizing and vt assignmentmethods . 25 2.3.1 Preliminaries .............................. 25 2.3.2 ScoreandRankalgorithms. 30 2.3.3 Greedymethods............................. 33 2.3.4 Globalsizing .............................. 35 2.3.5 SlackandDelaybudgetingmethods. 36 2.3.6 MethodsbasedonContinuousSizing . 39 2.3.7 Dynamicprogrammingbasedalgorithms . .. 41 2.3.8 Lagrangianrelaxation . 46 2.3.9 Slewtargetingmethods. 49 2.3.10 Linear programming based assignment methods . ..... 52 v 2.3.11 Summaryofmethods. 55 3 Benchmarking Discrete Gate Sizing and Threshold Voltage Assignment Methods ......................................... 57 3.1 Thestandardcelllibrary . .. 60 3.1.1 Delay .................................. 61 3.1.2 Delaymodels .............................. 63 3.2 Powertradeoffs ................................. 69 3.2.1 Powermodels .............................. 73 3.2.2 Benchmarksandsynthesisoptions. .. 75 3.3 Post-layoutconsiderations . .... 76 3.3.1 Post-layouttimingconsiderations . .... 78 3.3.2 Incremental placement and routing considerations . ........ 80 3.4 Comparisons................................... 80 3.4.1 ComparisonsusingUCLATimer . 82 3.4.2 Comparisonsusingeyecharts. 83 3.4.3 Comparisonsusingcommercialtools . .. 86 4 Parametric Variation and Gate Sizing .................... 91 4.1 Motivatingexamples .............................. 92 4.1.1 Theslackwall.............................. 92 4.1.2 Worst-casecornersandover-design . ... 94 4.2 Statisticalpoweroptimization . ..... 96 4.2.1 Preliminaries .............................. 98 4.2.2 Circuitexamples ............................ 107 vi 4.2.3 Analysisviarankcorrelations . 107 4.2.4 Suboptimalitybounds . 109 4.2.5 Experiments............................... 115 4.2.6 Bridgingthesuboptimalitygap . 128 4.2.7 Summary ................................ 132 4.3 Statisticaldelayoptimization . ..... 132 4.3.1 Statisticaldelaymodels . 134 4.3.2 TheMeanExcessDelay . 136 4.3.3 Minimizationalgorithm . 140 4.3.4 Results.................................. 141 4.3.5 Summary ................................ 144 5 Manufacturing Processes, Gate Sizing and Threshold Assignment ... 146 5.1 Impact of precision and range in standard cell libraries ........... 146 5.1.1 Suboptimality of vt Assignment .................... 149 5.1.2 Suboptimalityingatesizing . 157 5.1.3 Post-layoutexperiments . 163 5.1.4 Dynamicrangeandprecisionselection . 166 5.1.5 Multi-gatelibraryconsiderations . .... 169 5.1.6 Summary ................................ 171 5.2 ECO Gate sizing for Manufacturing Process Changes . ....... 171 5.2.1 ECOCost................................ 173 5.2.2 Solvingtheredesignproblem. 177 5.2.3 Creatinginitialdesigns . 184 vii 5.2.4 Experimentalresults . 186 5.2.5 Summary ................................ 187 6 Conclusions ..................................... 188 References ........................................ 191 viii List of Figures 1.1 ElectronicDesignAutomationflow. ... 8 2.1 Plot of the transition and delay times for an size 1 inverter driving a .05pF load........................................ 14 2.2 Output transition (slew) dilemma. The input waveforms to a two input gate areshown..................................... 19 2.3 Mesh example from [GKK10]. The optimum sizes for minimum delay are shown....................................... 21 2.4 Forward topological order dynamic programming example. A simple delay vs. power model is used for the gates, where either Delay=1 and Power=2, orDelay=2andPower=1. ........................... 42 2.5 reverse topological order dynamic programming example. A simple delay vs. power model is used for the gates, where either Delay=1 and Power=2, or Delay=2 and Power=1. The required arrival time at the primary output isassumedtobe4. ............................... 43 2.6 Design with reconvergent fanout. This structure is problematic in Dynamic Programmingformulations. 45 3.1 Normalized inverter gate delays for a commercial 45nm library........ 62 3.2 Normalized inverter input pin capacitances in a commercial 45nm library. 63 3.3 Example of effective capacitance: an inverter driving an RC tree. The effective capacitance is less than the total capacitance of the tree: Ceff < 4 i=1 Ci.Adaptedfrom[Sap04]. .. .. ... .. .. .. .. .. ... .. .. 67 3.4 NormalizedP inverter gate internal powers a commercial 45nm library. 70 3.5 Sourcesofleakagepower.. .. 70 ix 3.6 Normalized inverter gate leakage powers in a commercial 45nm library. 72 3.7 Plot of (a) the gate-length bias vs. power and (b) gate-length bias vs. delay. The data is for a nominal sized inverter in a commercial 45nm process, with anominalgatelengthof40nm. 72 3.8 Mismatch between the timing estimates at place and route and at sign-off. The gray line indicates when the two estimates match. Data adapted from, andcourtesyof[JK10].............................. 79 3.9 Histogram of the change in the timing after incremental placement and routing. There are 64 different examples. The majority of the cases have a zero change in timing, and most of the changes increase the timing (the change is positive). The maximum decrease and increase are -.007ns and .057ns,respectively.. 82 3.10 The effects of disabling slew in sizing experiments; the performance im- provement is relative to the timing-feasible greedy method. Disabling slew increases the difference between sizing methods. ...... 83 3.11 The basic structures used in the eyechart benchmarks. .......... 84 3.12 Eyechart comparisons of different gate sizing and threshold voltage assign- ment methods. (a) represents a gate-sizing comparison, (b) represents a vt assignment comparison with 3 threshold voltages, (c) represents a gate lengthassignmentwith3gatelengths. .. 85 3.13 The effect of the number of gate sizes available in the library on the subop- timalityofthegatesizingmethod. 86 x 3.14 Comparison between sizing methods using the Nangate 45nm Library. The y-axis gives the % suboptimality relative to the best solution found. The x-axis is the delay constraint – 0.0 is the minimum delay and 1.0 is the maximum delay. When the data point is omitted, it indicated that algorithm didnotreturnatiming-feasiblesolution. ..... 87 3.15 Comparison between sizing methods using a Commercial 65nm Library=. The y-axis gives the % suboptimality relative to the best solution found. The x-axis is the delay constraint – 0.0 is the minimum delay and 1.0 is the maximum delay. When the data point is omitted, it indicated that algorithm did not return a timing-feasible solution. ........ 89 3.16 Comparison between vt assignment methods using a Commercial 65nm Li- brary. The y-axis gives the % suboptimality relative to the best solution
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