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Cell Libraries and Verification

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Cell Libraries and Verification Cell libraries and verification Citation for published version (APA): Raffelsieper, M. (2011). Cell libraries and verification. Technische Universiteit Eindhoven. https://doi.org/10.6100/IR717717 DOI: 10.6100/IR717717 Document status and date: Published: 01/01/2011 Document Version: Publisher’s PDF, also known as Version of Record (includes final page, issue and volume numbers) Please check the document version of this publication: • A submitted manuscript is the version of the article upon submission and before peer-review. There can be important differences between the submitted version and the official published version of record. People interested in the research are advised to contact the author for the final version of the publication, or visit the DOI to the publisher's website. • The final author version and the galley proof are versions of the publication after peer review. • The final published version features the final layout of the paper including the volume, issue and page numbers. Link to publication General rights Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights. • Users may download and print one copy of any publication from the public portal for the purpose of private study or research. • You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the public portal. If the publication is distributed under the terms of Article 25fa of the Dutch Copyright Act, indicated by the “Taverne” license above, please follow below link for the End User Agreement: www.tue.nl/taverne Take down policy If you believe that this document breaches copyright please contact us at: [email protected] providing details and we will investigate your claim. Download date: 02. Oct. 2021 Cell Libraries and Verification PROEFSCHRIFT ter verkrijging van de graad van doctor aan de Technische Universiteit Eindhoven, op gezag van de rector magnificus, prof.dr.ir. C.J. van Duijn, voor een commissie aangewezen door het College voor Promoties in het openbaar te verdedigen op woensdag 2 november 2011 om 16.00 uur door Matthias Raffelsieper geboren te Recklinghausen, Duitsland Dit proefschrift is goedgekeurd door de promotoren: prof.dr. H. Zantema en prof.dr.ir. J.F. Groote Copromotor: dr. M.R. Mousavi c 2011 Matthias Raffelsieper IPA dissertation series 2011-15 The work in this thesis has been carried out under the auspices of the research school IPA (Institute for Programming research and Algorithmics). A catalogue record is available from the Eindhoven University of Technology Library ISBN: 978-90-386-2799-1 Contents Preface iii 1 Introduction1 2 Introduction to Cell Libraries7 2.1 Different Views of a Cell........................ 7 2.2 Transistor Netlist............................ 8 2.3 Verilog Simulation Description .................... 11 3 Equivalence Checking in Cell Libraries 15 3.1 Semantics of VeriCell ........................ 16 3.2 Encoding VeriCell into Boolean Transition Systems . 26 3.3 Equivalence Checking VeriCell and Transistor Netlist Descriptions 29 3.4 Experimental Results.......................... 30 3.5 Summary ................................ 31 4 Efficient Analysis of Non-Determinism in Cell Libraries 33 4.1 Order-Independence of VeriCell Descriptions............ 34 4.2 Order-Independence of Transistor Netlists............... 44 4.3 Using Non-Determinism to Reduce Power Consumption . 61 4.4 Summary ................................ 71 5 Relating Functional and Timing Behavior 75 5.1 Timing Checks ............................. 76 5.2 Module Paths.............................. 83 5.3 Summary ................................ 92 6 Productivity Analysis by Context-Sensitive Termination 95 6.1 Term Rewriting, Specifications, and Productivity........... 96 6.2 Productivity of Orthogonal Specifications . 103 6.3 Productivity of Non-Orthogonal Specifications . 113 6.4 Proving Productivity of Hardware Cells . 119 6.5 Summary ................................123 7 Productivity Analysis by Outermost Termination 125 7.1 Proving Productivity by Balanced Outermost Termination . 125 7.2 Transformational Outermost Termination Analysis . 131 7.3 Summary ................................149 8 Conclusion 151 i Contents Bibliography 155 Summary 163 Curriculum Vitae 165 A Nangate Open Cell Library License 167 ii Preface While finishing my diploma thesis at the RWTH Aachen, I was approached by my then supervisor Jürgen Giesl whether I would be interested in a PhD position in Eindhoven. Thanks to one the regular TeReSe meetings, that in Aachen were dubbed the “Dutch term rewriting community meetings” (including Aken), I was able to meet in Eindhoven with my future supervisors Hans Zantema and Jan Friso Groote, and also with Chris Strolenberg who would be involved in the ValiChip project. Due to the friendly atmosphere and the interesting ValiChip project, that would combine theory with practical applications from the hardware domain, I accepted the position and moved to Eindhoven. In the beginning, it took me some time to become acquainted with the hardware domain, in particular cell libraries, that was to be the topic of my research. However, both Chris Strolenberg and Jan-Willem Roorda of the industrial partner Fenix Design Automation gave me good pointers, for which I am very thankful. Furthermore, I am grateful for their expert input during the rest of the ValiChip project, which led to the research questions treated in this thesis. It was quite sad that the economic crisis did not spare Fenix Design Automation, so that it had to go out of business in 2009. I would also like to thank my daily supervisors and (co-)promotors Hans Zantema and MohammadReza Mousavi, who both gave me good advice and helpful technical feedback. Especially, I appreciated their different backgrounds which complemented each other well and that I could always walk into their offices with any problems I had. It was a pleasure working together with both Hans and Mohammad, and resulted in numerous co-authored publications which form the basis of this thesis. My second promotor was Jan Friso Groote, head of the OAS group and the later MDSE section. He entrusted my daily supervision with Hans and Mohammad, which I believe was a wise choice. I enjoyed working in his group, and profited from the discussions I had with him. The constructive comments and suggestions I received from the members of my thesis committee, Twan Basten, Hubert Garavel, Jürgen Giesl, Jan Friso Groote, MohammadReza Mousavi, and Hans Zantema, helped to improve the text substantially. I am therefore indebted to the aforementioned people for carefully reviewing my manuscript. Also, I would like to thank Wan Fokkink for agreeing to serve as an opponent in the defense. During the last four years, I enjoyed meeting numerous people, mostly as members of the MDSE section, on joint projects, at conferences, and through the IPA research school. I really appreciated the inspiring conversations I had with them, which sometimes also went beyond just technical discussions. Finally, I want to thank my family and friends. I feel deep gratitude towards you for supporting me both before and throughout my PhD period. Thank you. Matthias Raffelsieper, September 2011 iii Chapter 1 Introduction Electronic devices have become ubiquitous in modern life. This trend is expected to continue, with devices becoming even faster and even smaller at the same time. Such a development would not have been possible without the tremendous advances in the implementation of digital logic. Moore’s Law [Moo65, Sch97], which states that the transistor count of integrated circuits doubles approximately every 18 months, continues to explain these trends, despite having been declared expired a number of times. The most prominent force driving Moore’s law is technology scaling; smaller structures consume less power and operate faster. Furthermore, as more transistors are available, there is more opportunity to parallelize computations, thereby leading to another performance improvement. Due to the increase in transistor count, the functionality implemented in a specific piece of hardware become larger and more complex. Thus, techniques are sought to verify hardware correct, as bugs are inevitable once a certain size or complexity of the hardware design has been reached. One approach to guarantee correct behavior is by testing. However, testing can only investigate a limited number of test cases, thus there can still be untested corner cases in which the device does not function properly. Formal verification is another approach that is not limited to pre-conceived test cases. Instead, it tries to mathematically prove that a model of the device behaves as expected under all circumstances. This approach of formally verifying correctness is the technique used in this thesis to guarantee correctness of hardware devices. Guaranteeing correctness is especially important for hardware, since more and more safety-critical applications make use of it, where a failure can be devastating. Computer hardware is nowadays mainly designed in a top-down fashion: First, high level descriptions are created which are iteratively refined into a gate-level description (consisting only of simple logic functions and registers) and finally into transistors.
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