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Reliability-Aware Design to Suppress Aging

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Reliability-Aware Design to Suppress Aging Reliability-Aware Design to Suppress Aging Hussam Amrouch∗, Behnam Khaleghiy, Andreas Gerstlauerz and Jörg Henkel∗ ∗Karlsruhe Institute of Technology, Karlsruhe, Germany, ySharif University of Technology, Tehran, Iran, zUniversity of Texas, Austin, USA {amrouch; henkel}@kit.edu, [email protected], [email protected] ABSTRACT (when Si-H bonds break at the Si-SiO2 interface) and ox- Due to aging, circuit reliability has become extraordinary ide traps (when charges are captured in the oxide vacancies challenging. Reliability-aware circuit design flows do virtu- within the dielectric). Over time, generated defects (i.e. in- ally not exist and even research is in its infancy. In this pa- terface/oxide traps) accumulate inside the transistor, mani- per, we propose to bring aging awareness to EDA tool flows festing themselves as degradations in its electrical character- based on so-called degradation-aware cell libraries. These istics (Vth, µ, etc.). Hence, aged transistors become slower, libraries include detailed delay information of gates/cells which increases the likelihood of timing violations. BTI has under the impact that aging has on both threshold volt- also instantaneous effects in which degradations are observed age (V ) and carrier mobility (µ) of transistors. This is within a very short time domain (e.g., 1µs) [2]. However, th this work considers only the long-term effects of aging. unlike state of the art which considers Vth only. We show how ignoring µ degradation leads to underestimating guard- Timing Guardband: To overcome aging, manufacturers bands by 19% on average. Our investigation revealed that typically employ a guardband (TG) on top of the critical path the impact of aging is strongly dependent on the operating delay (T ) of a design [3] to guarantee that it will always be conditions of gates (i.e. input signal slew and output load clocked at a sustainable frequency for the projected lifetime. f = 1 ; T (t = lifetime) = T (t = 0) + T . capacitance), and not solely on the duty cycle of transistors. T (t=lifetime) G Neglecting this fact results in employing insufficient guard- Recent technology nodes operating under decreased supply bands and thus not sustaining reliability during lifetime. voltages steadily narrow the available design space for these We demonstrate that degradation-aware libraries and tool guardbands. Thus, minimizing guardbands becomes an in- flows are indispensable for not only accurately estimating evitable design task that additionally needs to be considered. guardbands, but also efficiently containing them. By consid- Traditionally, guardbanding is treated as a post-synthesis ering aging degradations during logic synthesis, significantly optimization. However, to avoid large guardbands (which more resilient circuits can be obtained. We further quantify may not be tolerated any longer), aging degradations should the impact of aging on the degradation of image process- be considered during the logic synthesis itself in order to ob- ing circuits. This goes far beyond investigating aging with tain circuits that are inherently more resilient against aging. respect to path delays solely. We show that in a standard Commercial EDA flows have evolved over three decades of design without any guardbanding, aging leads to unaccept- research. They provide powerful capabilities for analyzing able image quality after just one year. By contrast, if the the timing behavior of circuits and thus precisely determin- synthesis tool is provided with the degradation-aware cell ing their critical path delay based on information provided library, high image quality is sustained for 10 years (even within the targeted cell library. In addition, logic synthesis under worst-case aging and without a guardband). Hence, can (also based on delay information within the targeted cell using our approach, aging can be effectively suppressed. library) efficiently optimize the circuit's netlist to maximize the performance. Therefore, bringing reliability awareness 1. INTRODUCTION to tool flows is essential not only to accurately estimate Technology scaling is reaching limits where displacing a guardbands (i.e. without under/over-estimation) but also few atoms within transistors due to aging phenomena may to optimize the circuits against aging and thus containing endanger the functionality of the entire design. Negative and guardbands (i.e. having small, yet sufficient guardbands). Positive Bias Temperature Instability (NBTI and PBTI) are In this paper, we propose to provide the synthesis tool with the most prominent of these phenomena, with the potential the degradation-aware cell library to allow it addressing ag- to remarkably degrade the electrical characteristics of pMOS ing concerns { even if it was not designed for that purpose. and nMOS transistors, respectively. They occur due to elec- Our main contributions are as follows: trical field stresses in transistors resulting in interface traps (1) We explore the role of operating conditions of a gate/cell in determining the overall impact of aging in the scope of both timing analysis and logic synthesis { this holds even Permission to make digital or hard copies of all or part of this work for personal or more for complex designs like processors. classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full cita- (2) By providing logic synthesis tools with the delay infor- tion on the first page. Copyrights for components of this work owned by others than mation of gates/cells under aging, we leverage mature opti- ACM must be honored. Abstracting with credit is permitted. To copy otherwise, or re- mization algorithms to effectively suppress aging effects. publish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee. Request permissions from [email protected]. (3) To achieve our goals, we created 121 degradation-aware DAC’16, June 05-09, 2016, Austin, TX, USA cell libraries under varied aging scenarios. Libraries are pub- licly available at [1] and ready to be used with existing tool c 2016 ACM. ISBN 978-1-4503-4236-0/16/06. $15.00 flows (e.g., Synopsys) without requiring any modifications. DOI: http://dx.doi.org/10.1145/2897937.2898082 (a) NAND Gate (b) NOR Gate 0 46ps 31ps 37ps (Total) 64ps 18ps 26ps (Total) 350 -10 114ps 108ps -20 X4 X4 300 300 X1 X1 -30 1 X2 D Q 1 X2 D Q 250 +20 250 -40 X1 X1 200 0 Path1 200 -50 Path2 150 -20 150 -60 43ps (Total) 73ps (Total) 100 -40 -70 36ps 40ps 21ps 28ps 50 100 119ps 121ps -60 20 X4 X4 Delay Increase [%] X1 X1 0 50 16 1 X2 D Q 1 X2 D Q 0.96 -80 0.80 0.96 12 X1 X1 Input slew0.64 [ns] 20 0.80 16 0.64 8 0.48 12 0.48 -6.5% +16.1% +8.1% +14.3% +13.2% +8.5% 0.32 8 Input slew [ns]0.32 4 0.16 4 0.16 +4.4% +12.5% 0 0 Load capacitance [fF] 0 0 Load capacitance [fF] Figure 1: Impact of aging on the delay of NAND and NOR gates Figure 3: Motivational example showing how path1, which was demonstrating how it is driven by its operating conditions. critical before aging, became uncritical after aging. Single (OP C) Multiple (OP Cs) role in determining the impact that aging has on a gates' ] delay increase. Importantly, our results also revealed that 3 80 40 under some OP Cs, the delay of some gates improves instead 60 30 84% of being degraded. Figs. 1(a, b) show the impact of aging on two different gates (NAND and NOR, respectively). As 40 20 16% is shown in Fig. 1(a), a larger input signal slew magnifies the impact of aging on increasing the NAND's delay as it 20 10 leads to activating both the pull-up (pMOS) and pull-down Occurrence [#] 0 0 (nMOS) networks of the NAND simultaneously. Since the Occurrence [# x 10 degradations of NBTI in pMOS transistors are higher than 0 4 8 12 16 -60 -30 0 30 60 the degradations of PBTI in nMOS transistors [6], the pull- Delay increase [%] Delay increase [%] down network becomes relatively stronger and thus opposes Figure 2: Considering a single operating condition (OP C) solely, the pull-up network { especially for larger slews in which instead of multiple OP Cs, leads to erroneous aging estimations. the \ON" periods of pMOS and nMOS transistors overlap further. On the other hand, increasing the output load ca- 2. MOTIVATIONAL ANALYSIS: LINKING pacitance diminishes the impact of aging. Since it makes the NAND slower, it allows the gate to tolerate the degradations THE PHYSICAL AND SYSTEM LEVELS in its pMOS and nMOS transistors. The NOR gate exhibits In the following, we briefly explain how aging-induced de- a different behavior (Fig. 1(b)). Here, NBTI degradations fects at the physical level may propagate all the way up to make the opposing current from the pull-up network become the system level where they finally manifest themselves as smaller and hence the fall delay improves1 { especially for timing errors. The complexity of having to jointly consider larger input slews. Note that even though aging may im- multiple levels motivates the necessity of addressing aging prove the delay of some gates under specific OP Cs, it will within EDA tools to effectively optimize reliability. We ob- still make the overall circuit slower. The high increase in tained our results in Figs. (1, 2 and 3) from our proposed the delay of other gates within each path will usually com- methods in Section 4 which presents the core of this work. pensate the small decrease in some individual gates. Fig. 2 1) Physical/Device-Level: During the operation of a summarizes the impact that worst-case aging (i.e.
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