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SPICE Netlist Generation for Electrical Parasitic Modeling of Multi-Chip Power Module Designs Peter Tucker University of Arkansas, Fayetteville

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SPICE Netlist Generation for Electrical Parasitic Modeling of Multi-Chip Power Module Designs Peter Tucker University of Arkansas, Fayetteville University of Arkansas, Fayetteville ScholarWorks@UARK Electrical Engineering Undergraduate Honors Electrical Engineering Theses 5-2013 SPICE netlist generation for electrical parasitic modeling of multi-chip power module designs Peter Tucker University of Arkansas, Fayetteville Follow this and additional works at: http://scholarworks.uark.edu/eleguht Recommended Citation Tucker, Peter, "SPICE netlist generation for electrical parasitic modeling of multi-chip power module designs" (2013). Electrical Engineering Undergraduate Honors Theses. 4. http://scholarworks.uark.edu/eleguht/4 This Thesis is brought to you for free and open access by the Electrical Engineering at ScholarWorks@UARK. It has been accepted for inclusion in Electrical Engineering Undergraduate Honors Theses by an authorized administrator of ScholarWorks@UARK. For more information, please contact [email protected]. SPICE NETLIST GENERATION FOR ELECTRICAL PARASITIC MODELING OF MULTI-CHIP POWER MODULE DESIGNS SPICE NETLIST GENERATION FOR ELECTRICAL PARASITIC MODELING OF MULTI-CHIP POWER MODULE DESIGNS An Undergraduate Honors College Thesis in the Department of Electrical Engineering College of Engineering University of Arkansas Fayetteville, AR by Peter Nathaniel Tucker April 2013 ABSTRACT Multi-Chip Power Module (MCPM) designs are widely used in the area of power electronics to control multiple power semiconductor devices in a single package. The work described in this thesis is part of a larger ongoing project aimed at designing and implementing a computer aided drafting tool to assist in analysis and optimization of MCPM designs. This thesis work adds to the software tool the ability to export an electrical parasitic model of a power module layout into a SPICE format that can be run through an external SPICE circuit simulator. The code was implemented in python using NetworkX graphs to build parasitic circuit models and then write a netlist that can be interpreted by SPICE. Upon completion of the code, sample layouts were exported to netlists and run through circuit simulations using Synopsys® HSpice. An example simulation result is shown in this thesis and compared to an ideal case and a high parasitic case. ACKNOWLEDGMENTS I would like to take this opportunity to show my extreme appreciation to everyone who has helped me in both my thesis work and my entire undergraduate journey. I would first like to give a big thanks to Dr. Alan Mantooth for his guidance as both the advisor of this thesis work and as a trusted mentor through his personal advice and lessons. I would also like to thank Dr. Matt Francis for his guidance on this thesis work and management role in the overall project. Another big thanks goes to Mr. Brett Shook, a true friend. As a graduate student on the project, Brett taught me a great deal about the area of power module designs, along with a wide array of various other stimulating topics. It has truly been an honor to work with Brett. I would also like to thank the National Science Foundation’s GRid-connected Advanced Power Electronic Systems (GRAPES) Research Center for the funding and feedback of the overall project and my individual thesis work. I would finally like to give a very special thanks to my family and friends who have stood beside me from the beginning. Without their love and support, I would not be where I am today. I would particularly like to thank my parents, Tom and Peggy Tucker, for their unconditional love, support, and guidance even when my trips home fell few and far between. I am truly blessed to have the support I do from everyone around me. TABLE OF CONTENTS Abstract .......................................................................................................................................... iv Acknowledgments........................................................................................................................... v Table of Contents ........................................................................................................................... vi List of Figures .............................................................................................................................. viii 1. Introduction ............................................................................................................................... 1 2. Background ............................................................................................................................... 4 2.1 Power Module Layout and Structure ................................................................................... 4 2.2 Electrical Parasitic Modeling ............................................................................................... 6 2.3 HSpice and Netlists .............................................................................................................. 7 3. Approach and Implementation ................................................................................................ 10 3.1 Research Approach ............................................................................................................ 10 3.2 Generating NetworkX Graph For SPICE Export............................................................... 12 3.2.1 Reading Electrical Parasitic Network ......................................................................... 12 3.2.2 NetworkX Nodes versus. SPICE Nodes ..................................................................... 12 3.2.3 Creating Wire Delay Models ...................................................................................... 14 3.2.4 Creating SPICE Devices ............................................................................................. 18 3.3 Writing SPICE Subcircuit Netlist from NetworkX Graph ................................................ 22 4. Simulation Results .................................................................................................................. 24 4.1 Ideal Full-Bridge ................................................................................................................ 25 4.2 Full-Bridge with Large Parasitics ...................................................................................... 27 4.3 Two Exported Half-Bridge Modules configured as Full-Bridge ....................................... 29 5. Conclusions and Future Research ........................................................................................... 33 6. References ............................................................................................................................... 34 Appendix A. Half-Bridge Power Module Netlist ........................................................................ 35 A.1 Half-Bridge Subcircuit ...................................................................................................... 35 A.2 Application Circuit Netlist ................................................................................................ 40 LIST OF FIGURES Fig. 1. Multi-chip power module (R&D 100 award-winning design by UA and APEI). ............... 1 Fig. 2. PowerSynth solution browser displays Pareto front of optimal layout solutions. ............... 2 Fig. 3. Half-Bridge power module topographical layout. ............................................................... 4 Fig. 4. Module stack (exploded view). ........................................................................................... 5 Fig. 5. Wire delay models for modeling electrical parasitics. ........................................................ 7 Fig. 6. Half-Bridge power module layout solution with electrical parasitic network................... 11 Fig. 7. NetworkX inserted node. ................................................................................................... 13 Fig. 8. NetworkX graph before and after wire delay model generation. ...................................... 18 Fig. 9. Basic full-bridge single switch schematic. ........................................................................ 25 Fig. 10. Ideal full-bridge gate voltage switching characteristic. ................................................... 26 Fig. 11. Ideal full-bridge output voltage switching characteristic. ............................................... 26 Fig. 12. Ideal full-bridge output current switching characteristic. ................................................ 27 Fig. 13. High parasitic full-bridge setup. ...................................................................................... 27 Fig. 14. High parasitic full-bridge gate voltage switching characteristic. .................................... 28 Fig. 15. High parasitic full-bridge output voltage switching characteristic. ................................. 29 Fig. 16. High parasitic full-bridge output current switching characteristic. ................................. 29 Fig. 17. PowerSynth half-bridge module layout. .......................................................................... 30 Fig. 18. PowerSynth module gate voltage switching characteristic. ............................................ 31 Fig. 19. PowerSynth module output voltage switching characteristic. ......................................... 32 Fig. 20. PowerSynth module output current switching characteristic. ......................................... 32 1. INTRODUCTION Power semiconductor devices are the driving force behind today’s high-performance power electronics systems, and they play an integral role in alternative energy systems
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