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Netlist Grammar & Parser Implementation

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Netlist Grammar & Parser Implementation INTRODUCTION TO DESIGN AUTOMATION LectureLecture 5.5. NetlistNetlist GrammarGrammar (brief)(brief) && ParserParser ImplementationImplementation Guoyong Shi, PhD [email protected] School of Microelectronics Shanghai Jiao Tong University Fall 2010 2010-9-27 Slide 1 OutlineOutline • Netlist Grammar Spice background Spice devices and analyses • Netlist parser implementation Symbol table Data structure for models & devices Loading and solving flow in Spice * This lecture can be used as a simple Spice simulator manual. 2010-9-27 Lecture 5 slide 2 SPICESPICE • Simulation Program with IC Emphasis • First developed at UC Berkeley by Laurence Nagel (1972) • First version contained simple diode, BJT and MOS transistor models • Spawned many other programs with similar netlist syntax (HSPICE, PSpice, ...) as well as many other simulators (Eldo, Spectre, Sabre, ADS, ...) 2010-9-27 Lecture 5 slide 3 SPICESPICE HistoryHistory 1969-70 The CANCER Project (Ron Rohrer and Class project) 1970-72 CANCER Program (Ron Rohrer and Larry Nagel) May 1972 SPICE I released to Public Domain July 1975 SPICE 2A E. Cohen following Nagel’s Research Fall 1975 SPICE 2C Mid 1976 SPICE 2D New MOS Models Jan 1979 SPICE 2E MOS Model Levels Jan 1980 SPICE 2F SPICE in C, new MOS charge models Sep 1980 SPICE 2G Pivoting in linear solver Aug 1982 SPICE 2G Aug 1986 SPICE 3 (Sparse package by Ken Kundert) ..... 1990 SPICE not maintained anymore until today BSIM modeling continued (BSIM3/BSIM4) 2010-9-27 Lecture 5 slide 4 TheThe LatestLatest spice3f4spice3f4 SourceSource • http://embedded.eecs.berkeley.edu/pubs/down loads/spice/index.htm • You may download all source code there. • Try to install it in your computer. Easier on Linux machine Harder in cygwin • Read the source code if you like challenges !! • I’ll introduce some of the algorithms used in SPICE in this course. 2010-9-27 Lecture 5 slide 5 SpiceSpice NetlistNetlist FormatFormat • The first line is supposed to be the title of a circuit; • The last line must be ".END". • The order of the lines between the 1st and the last is arbitrary (except for the continuation lines.) • A line is continued by entering a '+' (plus) in column 1 of the following line. • A circuit is defined by a set of devices and their connections; a device is described by a name, nodes in the circuit, and values or models that specify the electric property of this device. • A set of control lines that define the model parameters or the run controls. • A name field must begin with a letter (A through Z) and cannot contain any delimiters. • Spice3 nodes names may be arbitrary character strings. 2010-9-27 Lecture 5 slide 6 SpiceSpice NetlistNetlist FormatFormat • The ground node must be named '0'. • The circuit cannot contain: 1. a loop of voltage sources and/or inductors; 2. a cutset of current sources and/or capacitors. • Each node in the circuit must have a DC path to the ground. • Every node must have at least two connections except for transmission line nodes (to permit unterminated transmission lines) and MOSFET substrate nodes (which have two internal connections.) 2010-9-27 Lecture 5 slide 7 ResistorResistor • Lumped Resistor Grammar: Rname <node> <node> <val> • Examples R1 1 2 100 RC1 12 17 1K • Semiconductor Resistor Grammar: Rname <node> <node> [<val>] <M_NAME> <L=len> <W=width> <TEMP=T> • Example Rm 3 7 RMODEL L=10u W=1u 2010-9-27 Lecture 5 slide 8 ResistorResistor • Grammar Rname <node> <node> [<val>] <M_NAME> <L=len> <W=width> <TEMP=T> • Example (Resistor with model) Rm 3 7 RMODEL L=10u W=1u • If <val> is specified, it overrides the geometric info following the <val> • If <M_NAME> is specified, then resistance is calculated from the process info in the model using the given length (L) and width (W). 2010-9-27 Lecture 5 slide 9 CapacitorCapacitor • CXXXXXXX N+ N- VALUE < IC=INCOND > • N+ and N- are the positive and negative element nodes, respectively. VALUE is the capacitance in Farads. • The (optional) initial condition is the initial (time-zero) value of capacitor voltage (in Volts). • Note that the initial conditions (if any) apply only if the UIC option is specified on the .TRAN control line. • Examples: CBYP 13 0 1UF COSC 17 23 10U IC=3V 2010-9-27 Lecture 5 slide 10 SemiconductorSemiconductor CapacitorsCapacitors • CXXXXXXX N1 N2 < VALUE> < MNAME > < L=LENGTH > < W=WIDTH> < IC=VAL > • This allows for the calculation of the actual capacitance value from strictly geometric information and the specifications of the process. • If VALUE is specified, it defines the capacitance. • If MNAME is specified, then the capacitance is calculated from the process information in the model MNAME and the given LENGTH and WIDTH. • If VALUE is not specified, then MNAME and LENGTH must be specified. If WIDTH is not specified, then it is taken from the default width given in the model. • Either VALUE or MNAME, LENGTH, and WIDTH may be specified, but not both sets. • Examples: • CLOAD 2 10 10P • CMOD 3 7 CMODEL L=10u W=1u 2010-9-27 Lecture 5 slide 11 InductorInductor • LYYYYYYY N+ N- VALUE < IC=INCOND > • N+ and N- are the positive and negative element nodes, respectively. VALUE is the inductance in Henries. • The (optional) initial condition is the initial (time-zero) value of inductor current (in Amps) that flows from N+, through the inductor, to N-. • Note that the initial conditions (if any) apply only if the UIC option is specified on the .TRAN analysis line. • Examples: LLINK 42 69 1UH LSHUNT 23 51 10U IC=15.7MA 2010-9-27 Lecture 5 slide 12 MutualMutual InductorsInductors • KXXXXXXX LYYYYYYY LZZZZZZZ VALUE • LYYYYYYY and LZZZZZZZ are the names of the two coupled inductors, and VALUE is the coefficient of coupling, 0 < K ≤ 1. • Using the 'dot' convention, place a 'dot' on the first node of each inductor. • Examples: K43 LAA LBB 0.999 KXFRMR L1 L2 0.87 2010-9-27 Lecture 5 slide 13 DiodeDiode (D)(D) • DXXXXXXX N+ N- MNAME <AREA> <OFF> <IC=VD> <TEMP=T> • Examples: • DBRIDGE 2 10 DIODE1 DCLMP 3 7 DMOD 3.0 IC=0.2 • MNAME is the model name, • AREA is the area factor (default to 1.0), • OFF indicates an (optional) starting condition on the device for dc analysis. 2010-9-27 Lecture 5 slide 14 DiodeDiode D1 1 2 0V 88.03e-24V D1N4148 VOFF = 0 V3 *DIODE01.CIR – Half-wave rectifier VAMPL = 12.6 R1 FREQ = 1000 1k .lib "nom.lib" 0 0V V1 1 0 SIN(0 12.6 1000) D1 1 2 D1N4148 0 R1 2 0 1K .TRAN 0.1M 10M 5M 0.01M .PROBE .END 2010-9-27 Lecture 5 slide 15 BJTBJT (Q)(Q) • Bipolar Junction Transistors (BJTs) • QXXXXXXX NC NB NE <NS> MNAME <AREA> <OFF> <IC=VBE, VCE> <TEMP=T> • Examples: • Q23 10 24 13 QMOD IC=0.6, 5.0 Q50A 11 26 4 20 MOD1 • NC, NB, and NE are the collector, base, and emitter nodes, respectively. NS is the (optional) substrate node. If unspecified, ground is used. • MNAME is the model name, AREA is the area factor, and OFF indicates an (optional) initial condition on the device for the DC analysis. • If the area factor is omitted, a value of 1.0 is assumed. • The (optional) initial condition specification using IC=VBE, VCE is intended for use with the UIC option on the .TRAN control line. • The (optional) TEMP value is the temperature at which this device is to operate, and overrides the temperature specification on the .OPTION control line. 2010-9-27 Lecture 5 slide 16 TransistorTransistor CircuitCircuit 5.000V R2 * source ONE_TRANSISTOR 1k 4.910V5 5Vdc V2 R_R1 1 2 10k Q1 R_R2 3 5 1k R1 600.0mV 592.0mV Q2N2222 3 R_R3 0 4 100 110k 2 VOFF = 0.6 V3 9.125mV V_V2 5 0 5Vdc VAMPL = 0.05 FREQ = 1000 R34 Q_Q1 3 2 4 Q2N2222 100 V_V3 1 0 0V +SIN 0.6 0.05 1000 0 0 0 0 2010-9-27 Lecture 5 slide 17 JFETJFET (J)(J) • Junction Field-Effect Transistors (JFETs) • JXXXXXXX ND NG NS MNAME < AREA > < OFF > < IC=VDS, VGS > < TEMP=T > • Examples: • J1 7 2 3 JM1 OFF 2010-9-27 Lecture 5 slide 18 IndependentIndependent VoltageVoltage SourcesSources • VXXXXXXX N+ N- << DC > DC/TRAN VALUE> < AC < ACMAG < ACPHASE >>> < DISTOF1 < F1MAG < F1PHASE >>> < DISTOF2 < F2MAG < F2PHASE >>> Examples: • VCC 10 0 DC 6 VIN 13 2 0.001 AC 1 SIN(0 1 1MEG) 0.001 is DC value. AC 1 is for AC analysis with magnitude 1. • SIN(0 1 1MEG) is a for transient analysis. • A source can be assigned values for DC, AC, and tran analysis. • VMEAS 12 9 VCARRIER 1 0 DISTOF1 0.1 -90.0 VMODULATOR 2 0 DISTOF2 0.01 • Zero-valued voltage sources (representing short-circuits) can be used for measuring current (ammeters). 2010-9-27 Lecture 5 slide 19 IndependentIndependent CurrentCurrent SourcesSources • General form: IYYYYYYY N+ N- << DC> DC/TRAN VALUE> < AC < ACMAG < ACPHASE >>> < DISTOF1 < F1MAG > F1PHASE>>> < DISTOF2 < F2MAG < F2PHASE >>> • Positive current is assumed to flow from the positive (+) node, through the source, to the negative (-) node. • A current source of positive value forces current to flow out of the N+ node, through the source, and into the N- node. 21 • Examples: ISRC 23 21 AC 0.333 45.0 SFFM(0 1 10K 5 1K) • SFFM stands for Frequency-Modulated Sinusoidal Function. 23 • Its standard form is SFFM(V0 Va fc mdi fs) • Its mathematical form is v(t) = V0 + Va * [sin(2*pi*fc*t + mdi*sin(2*pi*fs*t))]. • IIN1 1 5 AC 1 DISTOF1 DISTOF2 0.001 2010-9-27 Lecture 5 slide 20 TimeTime--DependentDependent IndependentIndependent SourcesSources • Any independent source can be assigned a time- dependent value for transient analysis.
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