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International Journal of Artificial Intelligence and Mechatronics Volume 4, Issue 3, ISSN 2320 – 5121

Design of a Multivalue Ternary and Quaternary

Miss. Manjushri . Hande Mr. Ashish Raghuwanshi M.Tech. Student of IES College of Technology Bhopal (M.P) Asst. Prof. IES College of Technology Bhopal, M.P

Abstract – The system use in binary requires large (-4). Two logic systems are available in ternary logic, number of interconnect which occupy around seventy logic -1, 0 and 1 and simple ternary logic percent area on an integrated chip. This limitation of area is 0, 1 and 2. The quaternary logic uses 0, 1, 2 and 3 logic reducing by using multivalue logic number system. The two levels. Figure 1 shows ternary logic with a voltage level. logic number systems are available in multivalue logic system i.. ternary number system and quaternary number system. Figure 2 shows quaternary logic levels with voltage level. The circuit design using multivalue system is more advantageous if it use with binary logic system. This can be done by using binary to multivalue logic conversions. In this work the multivalue logic system operation is present. It involves the MVL circuit for half and full adder circuit.

Keywords – MVL, Binary, Ternary Multiplexer, Quaternary Addition, , , , .

I. INTRODUCTION

A digital system operates on system. The number system uses in digital circuits are binary number Fig.1. Ternary logic level system instead of using number system. Other than this binary number system various other number systems are also use the fundamental concept of ten digit decimal number system. These are ternary, quaternary, senary, Octal, duodecimal, quodradecimal, hexadecimal and .The ternary number uses first three decimal number, quaternary uses first four decimal number, senary uses first six decimal numbers, octal uses first eight decimal numbers, duodecimal uses twelve, quodradecimal uses fourteen and hexadecimal uses sixteen decimal number system along with alphabetical characters. In binary the number system the two voltage level indicates the one binary i.e. logic '1' and logic '0'. The voltage level 0V represents the binary logic '0' and the Fig.2. Quaternary logic levels. voltage level of 5V represents binary logic '1'. While the ternary logic number system uses three voltage levels of III. NUMBER SYSTEM INTER-CONVERSIONS 0V, Vdd/3 and Vdd V, whereas the quaternary number system represents the four voltage levels of 0V, Vdd/2, The number systems whose radix is greater than 10 uses 2Vdd/3, Vdd V. This voltage level may differ for both the alphabetic characters in their number system. For the ternary and quaternary logic system. The encoder and arithmetic and logical operation and design of digital decoder circuits to convert binary logic to multivalued devices using these number systems it is very necessary to logic and multivalued logic to binary logic. The number understand the structure of number systems and its system logic in ternary uses logic 0, 1 and 2 while the interconversions. For the arithmetic and logical operation quaternary number system uses logic 0, 1, 2 and 3. and design of digital devices using these number systems

it is very necessary to understand the structure of number II. TERNARY/QUATERNARY LOGIC LEVEL systems and its interconversions. In this work the concepts of the mainly common number systems, their One can achieve a more cost-effective way of utilizing representation, arithmetic and logical, compliments and interconnections by using a larger set of signals over the inter conversion is consider. It will present a simple same area in multiple valued logic (MVL) devices, understanding and practising of these number systems to allowing easy implementation of circuits. In MVL devices, know as well as memorise them. The table 1 shows the the noise advantage of binary logic is retained. The higher number system and its conversions. radix in use is the ternary (radix-3) and the quaternary Copyright © 2015 IJAIM right reserved 121 International Journal of Artificial Intelligence and Mechatronics Volume 4, Issue 3, ISSN 2320 – 5121

Table 1: Various number system Decimal Binary Ternary Quaternary Senery Octal Duodecimal Quodradecimal Hexadecimal 0 0000 0 0 0 0 0 0 0 1 0001 1 1 1 1 1 1 1 2 0010 2 2 2 2 2 2 2 3 0011 10 3 3 3 3 3 3 4 0100 11 10 4 4 4 4 4 5 0101 12 11 5 5 5 5 5 6 0110 20 12 10 6 6 6 6 7 0111 21 13 11 7 7 7 7 8 1000 22 20 12 10 8 8 8 9 1001 100 21 13 11 9 9 9 10 1010 101 22 14 12 A A A 11 1011 102 23 15 13 B B B 12 1100 110 30 20 14 10 C 13 1101 111 31 21 15 11 D 14 1110 112 32 22 16 12 10 E 15 1111 120 33 23 17 13 11 F

IV. RELATED WORK using operational Amplifier (OPAMP) is design which consists of n-channel MOS transistor having a gate In [1] the quaternary 16 1 multiplexer logic design electrode, which is electrically floating which is less using transmission gate on 130nm technology with tolerable for radiations. maximum supply voltage of 1.2V. The maximum power In [6] the ternary logic base circuit is design. The consumption of this work was 122uW. The architecture is resistance of channels can be change by altering the base on switch like structure of transmission gate but is length-to-width of the PMOS and NMOS channels. not immune to noise in circuit. Thus, the resistance of the circuit is directly proportional In [2] multivalue logic gates was design on 0.35 um to its L/W ratio which can be effectively used to change technology for maximum 2.2V power supply. The logic the resistance of transistors to suit design needs. On the levels are design for 0V, 0.7V, 1.4V and 2.2V voltage other hand, there is a lower limit to the value of L and W supply. The operators: extended AND (eAND1, eAND2, due to the limitations imposed by the design rules of the eAND3, Successor (SUC), and Maximum (MAX) have foundry [6]. The proposed designs have much lower been implemented to illustrate the design of any Multiple- power dissipation relative to other known ternary circuits Valued Logic (MV Logic) digital circuit. A voltage reported in the literature [6]. CMOS divider is designed to set the logic voltages in the In [7] the multi-valued logic design consisting of two output. It obtains the maximum power consumption, from drivers and a transistor matrix was simulated on Mentor all possible logic conditions. For measuring the power Graphic software. Its timing analysis for four levels of consumption, a resistor was added between the source voltages i.e. 0V, 1.0V, 1.63V and 2.5V is simulates on this voltage and the IC source pin. They get power mentor graphic tool. consumption in the range of 721uw to 1370 uW and the delay in the range of 30ns to 550ns. V. TERNARY AND QUATERNARY ADDITION In [3] multivalue logic base 2-digit modulo-16 up counter is design on micrometer technology. For this Addition rules are the same as in the decimal system. author design the pass transistor base current mode latch The sum or product of two digits may only produce one or and flip-flop circuit. But their design needs improvement two digit numbers. In the latter case, if necessary, the first in circuit level, power dissipation, speed and extended digit is carried over to the next operation (on the left) For system level design. example, in base 7, 36 + 144 = 213. Indeed, from right to In [4] Quaternary to binary and binary to quaternary left, 6 + 4 = 13. Then 3 + 4 + 1 = 11, and finally 1 + 1 = 2. converters are designed on schematic level on H-spice As everyone knows, 2 + 2 = 4. This is true in all base simulator tool. Author design the H-spice code for systems. That is, except bases 2, 3, and 4. In base 4, we multiplier, adder, circuit for multi threshold have 2 + 2 = 10. In base 3, 2 + 2 = 11. However, recollect voltage transistor with) altering the width to length ratio of that (4)10 = (10)4 = (11)3, and everything falls into its CMOS transistors, by ii) using pad MOS transistors and right place again. Numbers equal in one base are equal in by iii) using multithreshold CMOS transistors. any other base. Conversion between bases does not violate In [5] the quaternary logic circuit base sign arithmetic arithmetic identities. In base 2, 2 + 2 = 4 appears as 10 + logic is presented on micrometer technology level. For this 10 = 100 - looking differently but having exactly the same they require three extra logical states. The converter circuit meaning. Copyright © 2015 IJAIM right reserved 122 International Journal of Artificial Intelligence and Mechatronics Volume 4, Issue 3, ISSN 2320 – 5121

The same, of course, is true of 2 × 2 = 4 which is true in [3] Milton Ernesto Romero, Evandro Mazina Martins, Ricardo all bases starting with 5. In bases 4, 3, and 2 it appears as Ribeiro dos Santos, and Mario Enrique Duarte Gonzalez "Universal Set of CMOS Gates for the Synthesis of Multiple 2 × 2 = 10 Valued Logic Digital Circuits" IEEE Transactions On Circuits 2 × 2 = 11 And Systems—I: Regular Papers, Vol. 61, No. 3, March 2014 10 × 10 = 100, pp. No. 736. respectively. [4] Fatma Sarica1 and Avni Morgul "Basic Circuits for Multi- Valued Sequential Logic" ELECO 2011 7th International Table 2: Ternary addition Conference on Electrical and Electronics Engineering, 1-4 Input Ta Input Tb Sum Carry December, Bursa, TURKEY 0 0 0 0 [5] Vasundara Patel k s, k s gurumurthy "Arithmatic Operation in Multivalue Logic" International journalo of VLSI design and 0 1 1 0 Communicationn System Vol.1 no.1 March 2010. 0 2 2 0 [6] Tanay Chattopadhyay and Tamal Sarkar "Logical Design of 1 0 1 0 Quaternary Signed Digit Conversion Circuit and its Effectuation 1 1 2 0 using Operational Amplifier" International Journal of Power Systems and Integrated Circuits, Vol. 2, No. 3, December 2012 1 2 0 1 pp no. 7. 2 0 2 0 [7] V. . Gaikwad & P R. Deshmukh “Design of CMOS Ternary 2 1 0 1 Logic Gates" in International Journal of Electrical and Electronics Engineering Research (IJEEER) Vol. 4, Issue 4, Aug 2 2 1 1 2014.

Table 3: Quaternary Addition Input Qa Input Qb Sum Carry 0 0 0 0 0 1 1 0 0 2 2 0 0 3 3 0 1 0 1 0 1 1 2 0 1 2 3 0 1 3 1 0 2 0 2 0 2 1 3 0 2 2 0 1 2 3 1 1 3 0 3 0 3 1 0 1 3 2 1 1 3 3 2 1

VI. CONCLUSION

In this paper the number system base on the fundamental concept of decimal number system and its equivalent other number systems is discuss. The arithmetic addition of ternary and quaternary number system is similar to that of decimal addition. Digital circuit design is possible by using ternary and quaternary number system is possible to design. But the digital circuit using other number system is not mostly design because the voltage levels use for this number system operates below the threshold voltage of transistor.

REFERENCES

[1] Diogo Brito, Taimur G. Rabuske,Jorge R. Fernandes, Paulo Flores, and José Monteiro "Quaternary Logic Lookup Table in Standard CMOS" IEEE Transactions On Very Large Integration (VLSI) Systems Vol.12 Jan 2015. [2] Flores, and Jose Monteiro “Quaternary Logic Lookup Table in Standard CMOS" in IEEE Transactions On Very Large Scale Integration (VLSI) Systems.

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