Electrostatic Discharge in Semiconductor Devices: Protection Techniques
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Electrostatic Discharge in Semiconductor Devices: Protection Techniques JAMES E. VINSON AND J. J. LIOU, SENIOR MEMBER, IEEE Invited Paper Electrostatic discharges (ESDs) are everywhere—in our homes charge transfer by controlling the environment where parts and businesses. Even the manufacturers of the electronics experi- are handled and stored. The next aspect focuses on the circuit ence ESD failures in their factories. Electronic devices are sensitive elements. Here, protection techniques look for ways to make to ESD. ESD results in failure of our computers, calculators, and car phones. There are ways to protect these sensitive components. the individual elements more robust to the currents induced This paper looks at ESD protection from a two-pronged approach: while at the same time adding additional circuit elements to reducing the likelihood of having an ESD event and improving the alter the conduction paths the charge takes through a circuit. robustness of the devices themselves. The first approach focuses on reducing the amount of charge that is developed and controlling the redistribution of any charges that are developed. The second ap- B. Real-World Events proach reviews ways to improve the circuit robustness by improving The movement of objects generates ESD events by pro- individual circuit elements and by adding additional elements for charge flow control and voltage clamping. viding the charging mechanism to produce a charge imbal- ance. No work area is immune to ESD events. The areas in- Keywords—Air ionizers, electrostatic discharge, ESD protection, clude office environments, homes, laboratories, wafer fabri- ESD safe packaging, ESD safe workstation, floor finishes, input protection, static clamps, static dissipation, transient clamps. cation facilities, and assembly/test sites. People as well as equipment generate ESD events. People are charged to high voltages when they walk across the carpet. If a shock is felt I. INTRODUCTION from the ESD event, then the event had more than 3000 V A. ESD Environment of potential [3]. Computer monitors in homes and offices are sources for inductive charging of parts and produce ESD Electrostatic discharge (ESD) is a subclass of the failure events in parts and equipment used around them [4]. causes known as electrical overstress (EOS). This class ap- These two sources of ESD generated events—people plies electrical stimulus to a part outside of its designed tol- and equipment—produce current discharges that are quite erance. ESD is a charge driven mechanism because the event different in shape, peak current, and duration. In fact, ESD occurs as a result of a charge imbalance [1]. The current in- from a person can be very different based on the footwear duced by an ESD event balances the charge between two ob- worn, whether they are sitting or standing, and whether they jects. Our previous paper [2] gave an overview on the various have a metal object (tool) in their hand. Chase and Unger, aspects of the ESD event. This paper will cover the specifics in [5], showed that the selection of footwear defines the of protection techniques for preventing the ESD damages person’s capacitance which ranged from 100 to 500 pF. If in semiconductor devices. The ESD event has four major 4 C were developed by the charging process, the induced stages: 1) charge generation; 2) charge transfer; 3) charge voltage would range from 800 V for the 500-pF case to conduction; and 4) charge-induced damage. ESD protection 4000 V for the 100-pF case. The generated voltage is the looks first to minimize the charge generation and slow the driving force behind the ESD event. The capacitance of a person could double if they were sitting versus standing [6]. In addition to these inconsistencies, Calvin et al.,in Manuscript received February 26, 2000; revised June 20, 2000. J. E. Vinson is with Reliability Engineering, Intersil Corporation, Mel- [7], showed that real-life ESD from people can consist of bourne, FL 32902 USA (e-mail: [email protected]). multiple discharges with each one progressively smaller in J. J. Liou is with the Electrical and Computer Engineering Department, magnitude. Holding a metal object during an ESD event can University of Central Florida, Orlando, FL 3286-2450 USA (e-mail: [email protected]). lower the series resistance of the discharge increasing the Publisher Item Identifier S 0018-9219(00)10760-1. current generated by the event [8]–[10]. The large variability 0018–9219/00$10.00 © 2000 IEEE 1878 PROCEEDINGS OF THE IEEE, VOL. 88, NO. 12, DECEMBER 2000 Fig. 1. Human body model ESD schematic diagram with parasitic elements. Fig. 2. HBM ESD current waveforms resulting from parasitic elements. in real-life ESD events makes it clear that a set of standards A schematic diagram of the HBM model is shown in Fig. 1 is needed to judge a circuit’s response to ESD. [12], [13]. A plot of the current pulses as a function of these The integrated circuit industry has standardized on three elements is shown in Fig. 2. The inductance controls the rise basic models related to ESD events. The models are based time of the current pulse. The parasitic capacitor C1 provides on the charge storage location. These are: 1) the human body current overshoot. The parasitic capacitor C2 can generate an model (HBM); 2) the machine model (MM); and 3) the additional current pulse if the device under test (DUT) has a charged device model (CDM). Each model is described by protection element that suddenly changes state such as a sil- standards or draft standards. The ESD Association of Rome, icon controlled rectifier (SCR). C2 represents the test board NY, publishes one such group of standards. The three stan- capacitance. Modern ESD testers are designed to minimize dards are ESD STM5.1-1998 Sensitivity Testing—Human these parasitic elements however many times the user designs Body Model (HBM)—Component Level; ESD S5.2-1999 and builds the DUT socket for their device. The user must Sensitivity Testing—Machine Model (MM)—Component take care not to introduce stray impedance into the current Level; and ESD DS5.3—1996 Charged Device Model path, or undesired results would occur. (CDM) Nonsocketed Mode—Component Level. These standards were accurate at the time of this writing, but the C. Damage Caused reader should contact the ESD Association directly for the latest revision. These methods of testing are intended to The currents induced by ESD are extremely high. In Fig. 2, simulate the average ESD event. As such, results obtained the HBM-generated current peaks are in excess of 2 A. CDM using these test methods are for comparisons of the robust- and MM ESD generate currents even higher than this. These ness of various designs and not as an absolute measure of a current levels are in excess of the normal operational cur- parts capability in the real-world environment [11]. rents. It is this current, directly or indirectly, that causes the VINSON AND LIOU: ELECTROSTATIC DISCHARGE IN SEMICONDUCTOR DEVICES 1879 Fig. 4. Voltage-induced damage mechanisms. ESD event damage electrical junctions as well as rupture dielectrics materials. The damage caused by ESD is a result of five damage mechanisms. More than one damage mecha- nism may be active in a single failure. The current induced damage mechanisms are thin-film fusing, filamentation, and junction spiking. The voltage-induced mechanisms are charge injection and dielectric rupture. These mechanisms are illustrated schematically in Figs. 3 and 4 for the current- and voltage-induced mechanisms, respectively. An overview of these damage mechanisms is presented here. Fig. 3. Current-induced damage mechanisms. Thin-film resister damage is shown in Fig. 5. This is a photo of the input structure on a silicon-on-sapphire (SOS) physical damage observed in an ESD failure. Direct damage logic part. This photo illustrates a limitation of this design. is caused by the power generated during the event. It melts The ESD current entered the bond pad and traveled through a section of the device causing failure. Indirectly, the current the resistor to the active device. The 90 bend in the resistor generates a voltage by the ohmic resistance and nonlinear caused current crowding along the inside edge of this resistor. conduction along its path. Small voltages are generated when The temperature of the polysilicon rose by joule heating until junctions are operated in forward bias mode, but large volt- it melted and damaged the resistor. The inside edge no longer ages are generated when they are in reverse bias mode. The conducts. The resistor fused at this point. It is important to reverse bias conduction causes thermal damage at lower cur- consider the large currents present during an ESD event and rent levels because the power dissipation is higher from the lay the structure out to account for the larger currents. Sharp higher voltage across the junction. In addition, the voltage corners should be avoided for both current paths and voltage generated by this event weakens dielectrics by charge injec- fields. The sharp corners cause current crowding as well as tion. The limiting case for this charge injection is dielectric high electric fields. High electric fields increase the proba- rupture. bility of having charge injection and dielectric rupture. Electrical testing of damaged parts shows increases in Filamentation damage is difficult to see in a transistor. It is leakage current. The high currents generated during an typically seen based on the electrical signature. A degraded 1880 PROCEEDINGS OF THE IEEE, VOL. 88, NO. 12, DECEMBER 2000 Fig. 5. Blown polysilicon resistor. Fig. 6. Zener diode with junction spiking. – trace is observed resulting in a leaky junction. The ex- treme case of filamentation is junction spiking.